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authorWolfgang Denk <wd@denx.de>2008-07-06 01:15:17 +0200
committerWolfgang Denk <wd@denx.de>2008-07-06 01:15:17 +0200
commitd86a0a6f7fe433787edf06aecba9fd6abfecab48 (patch)
tree005ba8a000e7bdcab42c1df6339bf7e51dcda2ca /doc/README.mvblm7
parenta524e112b424c6843800ea2f19d3a8cf01d0aa94 (diff)
parentf492dd636fbbae529e17533995bc6e5813c007f6 (diff)
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Merge branch 'master' of ssh+git://mercury.denx.de/home/wd/git/u-boot/master
Conflicts: board/amirix/ap1000/serial.c board/exbitgen/exbitgen.c board/exbitgen/flash.c board/ml2/serial.c board/xilinx/ml300/serial.c Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'doc/README.mvblm7')
-rw-r--r--doc/README.mvblm75
1 files changed, 2 insertions, 3 deletions
diff --git a/doc/README.mvblm7 b/doc/README.mvblm7
index 6a40888..3ee9396 100644
--- a/doc/README.mvblm7
+++ b/doc/README.mvblm7
@@ -11,7 +11,7 @@ Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
2 System Components
-2.1 CPU
+2.1 CPU
Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
512MByte DDR-II memory @ 133MHz.
8 MByte Nor Flash on local bus.
@@ -23,7 +23,7 @@ Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
2.2 PCI
A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
-
+
2.3 FPGA
Altera Cyclone-II EP2C20/35 with PCI DMA engines.
Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
@@ -82,4 +82,3 @@ Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
2. Initrd - name is stored in "initrd_name"
3. device tree blob - name is stored in "dtb_name"
Fallback files are the flash versions.
-