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authorWolfgang Denk <wd@pollux.denx.de>2005-08-05 20:03:38 +0200
committerWolfgang Denk <wd@pollux.denx.de>2005-08-05 20:03:38 +0200
commitb4f15fdaf77b7339e2984703c83269c7cdf680a9 (patch)
tree32bb3b65d98a229aead643ae11ef2dc433146411 /doc/README.mpc85xxcds
parentb20d00328c5486a4b2cdf07ce7afaf2139dc741e (diff)
parent07a2505f67e091ff70506ae6a5022b416211df44 (diff)
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Merge with /home/wd/git/u-boot/jon_loeliger
Diffstat (limited to 'doc/README.mpc85xxcds')
-rw-r--r--doc/README.mpc85xxcds43
1 files changed, 41 insertions, 2 deletions
diff --git a/doc/README.mpc85xxcds b/doc/README.mpc85xxcds
index e0f4916..bc5db0c 100644
--- a/doc/README.mpc85xxcds
+++ b/doc/README.mpc85xxcds
@@ -135,8 +135,8 @@ The default setting of all switches on the carrier board is:
SW4=10001000
-CPU Card Switches
------------------
+8555/41 CPU Card Switches
+-------------------------
Most switches on the CPU Card should not be changed. However, the
frequency can be changed by setting SW3:
@@ -160,6 +160,45 @@ A safe default setting for all switches on the CPU board is:
SW4=11111110
+8548 CPU Card Switches
+----------------------
+And, just to be confusing, in this set of switches:
+
+ ON = 1
+ OFF = 0
+
+Default
+ SW1=11111101
+ SW2=10011111
+ SW3=11001000 (8X) (2:1)
+ SW4=11110011
+
+ SW3=X000XXXX == CORE:CCB 4:1
+ X001XXXX == CORE:CCB 9:2
+ X010XXXX == CORE:CCB 1:1
+ X011XXXX == CORE:CCB 3:2
+ X100XXXX == CORE:CCB 2:1
+ X101XXXX == CORE:CCB 5:2
+ X110XXXX == CORE:CCB 3:1
+ X111XXXX == CORE:CCB 7:2
+ XXXX0000 == CCB:SYSCLK 16:1
+ XXXX0001 == RESERVED
+ XXXX0010 == CCB:SYSCLK 2:1
+ XXXX0011 == CCB:SYSCLK 3:1
+ XXXX0100 == CCB:SYSCLK 4:1
+ XXXX0101 == CCB:SYSCLK 5:1
+ XXXX0110 == CCB:SYSCLK 6:1
+ XXXX0111 == RESERVED
+ XXXX1000 == CCB:SYSCLK 8:1
+ XXXX1001 == CCB:SYSCLK 9:1
+ XXXX1010 == CCB:SYSCLK 10:1
+ XXXX1011 == RESERVED
+ XXXX1100 == CCB:SYSCLK 12:1
+ XXXX1101 == CCB:SYSCLK 20:1
+ XXXX1110 == RESERVED
+ XXXX1111 == RESERVED
+
+
eDINK Info
----------