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| author | Anish Trivedi <anish@freescale.com> | 2011-01-05 11:48:14 -0600 |
|---|---|---|
| committer | Anish Trivedi <anish@freescale.com> | 2011-01-05 12:11:47 -0600 |
| commit | 5d92b32e22a49b32a35b5d456c8d38af04f53422 (patch) | |
| tree | 1db8abc326346dc6d7945ff88828f57a6225acb8 /doc/README.mpc85xxcds | |
| parent | 57c938c25c39fce91192ad9703457367e11f7809 (diff) | |
| download | u-boot-imx-5d92b32e22a49b32a35b5d456c8d38af04f53422.zip u-boot-imx-5d92b32e22a49b32a35b5d456c8d38af04f53422.tar.gz u-boot-imx-5d92b32e22a49b32a35b5d456c8d38af04f53422.tar.bz2 | |
ENGR00137642 MX53 Uboot Align DDR3 script for Loco and SMD boards
Changed the value of one register, offset 0x88, of the ESDCTL controller
to match the official script for the boards, entitled "MX53_TO2_DDR3_LCB.inc",
found at
http://compass.freescale.net/livelink/livelink/221435668/
MX53_TO2_DDR3_LCB.inc.txt?func=doc.Fetch&nodeid=221435668
The register value sets read delay lines. The change is minor.
Signed-off-by: Anish Trivedi <anish@freescale.com>
Diffstat (limited to 'doc/README.mpc85xxcds')
0 files changed, 0 insertions, 0 deletions