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| author | Peter Tyser <ptyser@xes-inc.com> | 2010-10-29 17:59:27 -0500 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-11-14 23:46:46 +0100 |
| commit | 983eb9d1628a7363f98c8c125522815c429ddf97 (patch) | |
| tree | 4b139cd39ff73ca59fea3af472011ca1fe5e1b0c /doc/README.mpc8572ds | |
| parent | 37d03fce9c0a8cf3119e15652aa6c4b0053cb8ed (diff) | |
| download | u-boot-imx-983eb9d1628a7363f98c8c125522815c429ddf97.zip u-boot-imx-983eb9d1628a7363f98c8c125522815c429ddf97.tar.gz u-boot-imx-983eb9d1628a7363f98c8c125522815c429ddf97.tar.bz2 | |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW
This change does the following:
- Removes the printing of the PCI interrupt line value. This is
normally set to 0 by U-Boot on bootup and is rarely used during
everyday operation.
- Prints out the PCI function number of a device. Previously a device
with multiple functions would be printed identically 2 times, which is
generally confusing. For example, on an Intel 2 port gigabit Ethernet
card the following was displayed:
...
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
...
- Prints a text description of each device's PCI class instead of the
raw PCI class code. The textual description makes it much easier to
determine what devices are installed on a PCI bus.
- Changes the general formatting of the PCI device output.
Previous output:
PCIE1: connected as Root Complex
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0d
Updated output:
PCIE1: connected as Root Complex
04:01.0 - 8086:1010 - Network controller
04:01.1 - 8086:1010 - Network controller
03:00.0 - 10b5:8112 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
02:02.0 - 10b5:8518 - Bridge device
08:00.0 - 1957:0040 - Processor
07:00.0 - 10b5:8518 - Bridge device
09:00.0 - 10b5:8112 - Bridge device
07:01.0 - 10b5:8518 - Bridge device
07:02.0 - 10b5:8518 - Bridge device
06:00.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
01:00.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d:00.0 - 1957:0040 - Processor
PCIE2: Bus 0c - 0d
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'doc/README.mpc8572ds')
0 files changed, 0 insertions, 0 deletions