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authorShinya Kuribayashi <skuribay@ruby.dti.ne.jp>2008-04-22 22:47:27 +0900
committerWolfgang Denk <wd@denx.de>2008-04-25 00:03:53 +0200
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doc/README.mips: Add MIPS notes
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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+
+Notes for the MIPS architecture port of U-Boot
+
+Toolchains
+----------
+
+ http://www.denx.de/wiki/DULG/ELDK
+ ELDK < DULG < DENX
+
+ http://www.emdebian.org/crosstools.html
+ Embedded Debian -- Cross-development toolchains
+
+ http://buildroot.uclibc.org/
+ Buildroot
+
+Known Issues
+------------
+
+ * Little endian build problem
+
+ If use non-ELDK toolchains, -EB will be set to CPPFLAGS. Therefore all
+ objects will be generated in big-endian format.
+
+ * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
+
+ Cache will be disabled before entering the loaded ELF image without
+ writing back and invalidating cache lines. This leads to cache
+ incoherency in most cases, unless the code gets loaded after U-Boot
+ re-initializes the cache. The more common uImage 'bootm' command does
+ not suffer this problem.
+
+ [workaround] To avoid this cache incoherency,
+ 1) insert flush_cache(all) before calling dcache_disable(), or
+ 2) fix dcache_disable() to do both flushing and disabling cache.
+
+ * Note that Linux users need to kill dcache_disable() in do_bootelf_exec()
+ or override do_bootelf_exec() not to disable I-/D-caches, because most
+ Linux/MIPS ports don't re-enable caches after entering kernel_entry.
+
+TODOs
+-----
+
+ * Probe CPU types, I-/D-cache and TLB size etc. automatically
+
+ * Secondary cache support missing
+
+ * Centralize the link directive files
+
+ * Initialize TLB entries redardless of their use
+
+ * R2000/R3000 class parts are not supported
+
+ * Limited testing across different MIPS variants
+
+ * Due to cache initialization issues, the DRAM on board must be
+ initialized in board specific assembler language before the cache init
+ code is run -- that is, initialize the DRAM in lowlevel_init().