Merge 'next' branch

Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

1 files changed, 41 insertions, 41 deletions

diff --git a/doc/README.m54455evb b/doc/README.m54455evb
index 5c01f0d..f695da5 100644
--- a/doc/README.m54455evb
+++ b/doc/README.m54455evb
@@ -71,12 +71,12 @@ CONFIG_M54455		-- define for all Freescale MCF54455 CPUs
 CONFIG_M54455EVB	-- define for M54455EVB board
 
 CONFIG_MCFUART		-- define to use common CF Uart driver
-CFG_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CONFIG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
 CONFIG_BAUDRATE		-- define UART baudrate
 
 CONFIG_MCFRTC		-- define to use common CF RTC driver
-CFG_MCFRTC_BASE		-- provide base address for RTC in immap.h
-CFG_RTC_OSCILLATOR	-- define RTC clock frequency
+CONFIG_SYS_MCFRTC_BASE		-- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR	-- define RTC clock frequency
 RTC_DEBUG		-- define to show RTC debug message
 CONFIG_CMD_DATE		-- enable to use date feature in u-boot
 
@@ -84,13 +84,13 @@ CONFIG_MCFFEC		-- define to use common CF FEC driver
 CONFIG_NET_MULTI	-- define to use multi FEC in u-boot
 CONFIG_MII		-- enable to use MII driver
 CONFIG_CF_DOMII		-- enable to use MII feature in cmd_mii.c
-CFG_DISCOVER_PHY	-- enable PHY discovery
-CFG_RX_ETH_BUFFER	-- Set FEC Receive buffer
-CFG_FAULT_ECHO_LINK_DOWN--
-CFG_FEC0_PINMUX		-- Set FEC0 Pin configuration
-CFG_FEC1_PINMUX		-- Set FEC1 Pin configuration
-CFG_FEC0_MIIBASE	-- Set FEC0 MII base register
-CFG_FEC1_MIIBASE	-- Set FEC0 MII base register
+CONFIG_SYS_DISCOVER_PHY	-- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER	-- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
+CONFIG_SYS_FEC0_PINMUX		-- Set FEC0 Pin configuration
+CONFIG_SYS_FEC1_PINMUX		-- Set FEC1 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE	-- Set FEC0 MII base register
+CONFIG_SYS_FEC1_MIIBASE	-- Set FEC0 MII base register
 MCFFEC_TOUT_LOOP	-- set FEC timeout loop
 CONFIG_HAS_ETH1		-- define to enable second FEC in u-boot
 
@@ -100,14 +100,14 @@ CONFIG_IDE_RESET	-- define ide_reset()
 CONFIG_IDE_PREINIT	-- define ide_preinit()
 CONFIG_ATAPI		-- define ATAPI support
 CONFIG_LBA48		-- define LBA48 (larger than 120GB) support
-CFG_IDE_MAXBUS		-- define max channel
-CFG_IDE_MAXDEVICE	-- define max devices per channel
-CFG_ATA_BASE_ADDR	-- define ATA base address
-CFG_ATA_IDE0_OFFSET	-- define ATA IDE0 offset
-CFG_ATA_DATA_OFFSET	-- define ATA data IO
-CFG_ATA_REG_OFFSET	-- define for normal register accesses
-CFG_ATA_ALT_OFFSET	-- define for alternate registers
-CFG_ATA_STRIDE		-- define for Interval between registers
+CONFIG_SYS_IDE_MAXBUS		-- define max channel
+CONFIG_SYS_IDE_MAXDEVICE	-- define max devices per channel
+CONFIG_SYS_ATA_BASE_ADDR	-- define ATA base address
+CONFIG_SYS_ATA_IDE0_OFFSET	-- define ATA IDE0 offset
+CONFIG_SYS_ATA_DATA_OFFSET	-- define ATA data IO
+CONFIG_SYS_ATA_REG_OFFSET	-- define for normal register accesses
+CONFIG_SYS_ATA_ALT_OFFSET	-- define for alternate registers
+CONFIG_SYS_ATA_STRIDE		-- define for Interval between registers
 _IO_BASE		-- define for IO base address
 
 CONFIG_MCFTMR		-- define to use DMA timer
@@ -116,42 +116,42 @@ CONFIG_MCFPIT		-- define to use PIT timer
 CONFIG_FSL_I2C		-- define to use FSL common I2C driver
 CONFIG_HARD_I2C		-- define for I2C hardware support
 CONFIG_SOFT_I2C		-- define for I2C bit-banged
-CFG_I2C_SPEED		-- define for I2C speed
-CFG_I2C_SLAVE		-- define for I2C slave address
-CFG_I2C_OFFSET		-- define for I2C base address offset
-CFG_IMMR		-- define for MBAR offset
+CONFIG_SYS_I2C_SPEED		-- define for I2C speed
+CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
+CONFIG_SYS_IMMR		-- define for MBAR offset
 
 CONFIG_PCI              -- define for PCI support
 CONFIG_PCI_PNP          -- define for Plug n play support
-CFG_PCI_MEM_BUS		-- PCI memory logical offset
-CFG_PCI_MEM_PHYS	-- PCI memory physical offset
-CFG_PCI_MEM_SIZE	-- PCI memory size
-CFG_PCI_IO_BUS		-- PCI IO logical offset
-CFG_PCI_IO_PHYS		-- PCI IO physical offset
-CFG_PCI_IO_SIZE		-- PCI IO size
-CFG_PCI_CFG_BUS		-- PCI Configuration logical offset
-CFG_PCI_CFG_PHYS	-- PCI Configuration physical offset
-CFG_PCI_CFG_SIZE	-- PCI Configuration size
+CONFIG_SYS_PCI_MEM_BUS		-- PCI memory logical offset
+CONFIG_SYS_PCI_MEM_PHYS	-- PCI memory physical offset
+CONFIG_SYS_PCI_MEM_SIZE	-- PCI memory size
+CONFIG_SYS_PCI_IO_BUS		-- PCI IO logical offset
+CONFIG_SYS_PCI_IO_PHYS		-- PCI IO physical offset
+CONFIG_SYS_PCI_IO_SIZE		-- PCI IO size
+CONFIG_SYS_PCI_CFG_BUS		-- PCI Configuration logical offset
+CONFIG_SYS_PCI_CFG_PHYS	-- PCI Configuration physical offset
+CONFIG_SYS_PCI_CFG_SIZE	-- PCI Configuration size
 
 CONFIG_EXTRA_CLOCK	-- Enable extra clock such as vco, flexbus, pci, etc
 
-CFG_MBAR		-- define MBAR offset
+CONFIG_SYS_MBAR		-- define MBAR offset
 
-CFG_ATMEL_BOOT		-- To determine the u-boot is booted from Atmel or Intel
+CONFIG_SYS_ATMEL_BOOT		-- To determine the u-boot is booted from Atmel or Intel
 
 CONFIG_MONITOR_IS_IN_RAM -- Not support
 
-CFG_INIT_RAM_ADDR	-- defines the base address of the MCF54455 internal SRAM
+CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF54455 internal SRAM
 
-CFG_CSn_BASE	-- defines the Chip Select Base register
-CFG_CSn_MASK	-- defines the Chip Select Mask register
-CFG_CSn_CTRL	-- defines the Chip Select Control register
+CONFIG_SYS_CSn_BASE	-- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK	-- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL	-- defines the Chip Select Control register
 
-CFG_ATMEL_BASE	-- defines the Atmel Flash base
-CFG_INTEL_BASE	-- defines the Intel Flash base
+CONFIG_SYS_ATMEL_BASE	-- defines the Atmel Flash base
+CONFIG_SYS_INTEL_BASE	-- defines the Intel Flash base
 
-CFG_SDRAM_BASE	-- defines the DRAM Base
-CFG_SDRAM_BASE1	-- defines the DRAM Base 1
+CONFIG_SYS_SDRAM_BASE	-- defines the DRAM Base
+CONFIG_SYS_SDRAM_BASE1	-- defines the DRAM Base 1
 
 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
 ===========================================