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authorYork Sun <yorksun@freescale.com>2014-12-02 11:18:09 -0800
committerYork Sun <yorksun@freescale.com>2014-12-15 09:15:12 -0800
commit938bbb6013f051808c08204184e94d0cdcb6dbff (patch)
tree8102d1ed2cb0ef18f642c606d4ade71219c62f64 /doc/README.kconfig
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driver/ddr/fsl: Fix MRC_CYC calculation for DDR3
For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun <yorksun@freescale.com>
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