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| author | Tom Rini <trini@ti.com> | 2012-10-22 16:54:38 -0700 |
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| committer | Tom Rini <trini@ti.com> | 2012-10-22 16:54:38 -0700 |
| commit | c7656bab411433f987baa2288eff8c78ddc0f378 (patch) | |
| tree | 18fe8fa515ecdea19afa83d1af0c6eff4946a5d4 /doc/README.fsl-ddr | |
| parent | bdc3ff6e4f75813d01e51081799d10e4a9c7fbcb (diff) | |
| parent | 23028d69e950023a3cb605751dbcb1e314be8b36 (diff) | |
| download | u-boot-imx-c7656bab411433f987baa2288eff8c78ddc0f378.zip u-boot-imx-c7656bab411433f987baa2288eff8c78ddc0f378.tar.gz u-boot-imx-c7656bab411433f987baa2288eff8c78ddc0f378.tar.bz2 | |
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Diffstat (limited to 'doc/README.fsl-ddr')
| -rw-r--r-- | doc/README.fsl-ddr | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index f94b56f..3992640 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -103,6 +103,11 @@ The ways to configure the ddr interleaving mode # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" + # bank(chip-select) interleaving (auto) + setenv hwconfig "fsl_ddr:bank_intlv=auto" + This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings + on DIMMs. + Memory controller address hashing ================================== If the DDR controller supports address hashing, it can be enabled by hwconfig. |