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| author | Stefano Babic <sbabic@denx.de> | 2012-11-10 08:05:54 +0100 |
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| committer | Stefano Babic <sbabic@denx.de> | 2012-11-10 08:05:54 +0100 |
| commit | 3e4d27b06d7484040355e22eec2cbce7335d6dab (patch) | |
| tree | 9672a2bb2e4ce0edc0ab776ddf0e2ca8e39a5f62 /doc/README.fsl-ddr | |
| parent | bad05afe083eec0467220de21683443292c5012e (diff) | |
| parent | 59852d03867108217fe88e3bfc3e1e9cedfe63c5 (diff) | |
| download | u-boot-imx-3e4d27b06d7484040355e22eec2cbce7335d6dab.zip u-boot-imx-3e4d27b06d7484040355e22eec2cbce7335d6dab.tar.gz u-boot-imx-3e4d27b06d7484040355e22eec2cbce7335d6dab.tar.bz2 | |
Merge git://git.denx.de/u-boot
Diffstat (limited to 'doc/README.fsl-ddr')
| -rw-r--r-- | doc/README.fsl-ddr | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index f94b56f..3992640 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -103,6 +103,11 @@ The ways to configure the ddr interleaving mode # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" + # bank(chip-select) interleaving (auto) + setenv hwconfig "fsl_ddr:bank_intlv=auto" + This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings + on DIMMs. + Memory controller address hashing ================================== If the DDR controller supports address hashing, it can be enabled by hwconfig. |