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| author | Tom Warren <twarren@nvidia.com> | 2013-03-25 16:22:26 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-04-15 11:01:38 -0700 |
| commit | d0edce4fa394325a0ccfd38a5d668fb5ee1af34d (patch) | |
| tree | 5a7ea0c182d9b2c33699fcfff230f83ba7b4ff84 /doc/README.displaying-bmps | |
| parent | 85434f9d7123c283b2233614178e7cfc968d329b (diff) | |
| download | u-boot-imx-d0edce4fa394325a0ccfd38a5d668fb5ee1af34d.zip u-boot-imx-d0edce4fa394325a0ccfd38a5d668fb5ee1af34d.tar.gz u-boot-imx-d0edce4fa394325a0ccfd38a5d668fb5ee1af34d.tar.bz2 | |
Tegra: Configure L2 cache control reg properly.
Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.
Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'doc/README.displaying-bmps')
0 files changed, 0 insertions, 0 deletions