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| author | York Sun <yorksun@freescale.com> | 2012-08-17 08:22:37 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-08-23 12:16:55 -0500 |
| commit | 73b5396b25c52463aa71c782316e2d77a4b8d5ed (patch) | |
| tree | b6e82b205f1dc1a2d4a1eac37ec136cbe22822fa /doc/README.davinci.nand_spl | |
| parent | 744713a6a3ca19c77585a9452829a2e2a55693ad (diff) | |
| download | u-boot-imx-73b5396b25c52463aa71c782316e2d77a4b8d5ed.zip u-boot-imx-73b5396b25c52463aa71c782316e2d77a4b8d5ed.tar.gz u-boot-imx-73b5396b25c52463aa71c782316e2d77a4b8d5ed.tar.bz2 | |
powerpc/mpc8xxx: Add fine timing support for DDR3
When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'doc/README.davinci.nand_spl')
0 files changed, 0 insertions, 0 deletions