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| author | J. German Rivera <German.Rivera@freescale.com> | 2014-06-23 15:15:55 -0700 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-07-03 08:40:58 +0200 |
| commit | b940ca64b22ba8980fd4ec8dda028f6b1a2ed79d (patch) | |
| tree | b10ed6b9111d3a6522957b1a85eed5492f09f65a /doc/README.440-DDR-performance | |
| parent | 2f78eae5064728d6cd907148cfeaf8ba3e63b0ef (diff) | |
| download | u-boot-imx-b940ca64b22ba8980fd4ec8dda028f6b1a2ed79d.zip u-boot-imx-b940ca64b22ba8980fd4ec8dda028f6b1a2ed79d.tar.gz u-boot-imx-b940ca64b22ba8980fd4ec8dda028f6b1a2ed79d.tar.bz2 | |
armv8/fsl-lsch3: Add support to load and start MC Firmware
Adding support to load and start the Layerscape Management Complex (MC)
firmware. First, the MC GCR register is set to 0 to reset all cores. MC
firmware and DPL images are copied from their location in NOR flash to
DDR. MC registers are updated with the location of these images.
Deasserting the reset bit of MC GCR register releases core 0 to run.
Core 1 will be released by MC firmware. Stop bits are not touched for
this step. U-boot waits for MC until it boots up. In case of a failure,
device tree is updated accordingly. The MC firmware image uses FIT format.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
Diffstat (limited to 'doc/README.440-DDR-performance')
0 files changed, 0 insertions, 0 deletions