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authorZang Roy-r61911 <tie-fei.zang@freescale.com>2006-12-20 11:01:00 +0800
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2007-04-23 19:58:27 -0500
commit63247a5acd58032e6cf33f525bc3923b467bac88 (patch)
treed962daa227037cfe8011f5c90965ceb6838a4e21 /cpu
parent0b1934ba12fd408fcc3b8bd9f4b04864c42a42bf (diff)
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u-boot: v2: Remove the fixed TLB and LAW entrynubmer
Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW entry number to control the loop. This can reduce the potential risk for the 85xx processor increasing its TLB adn LAW entry number. Signed-off-by: Swarthout Edward <swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc85xx/start.S16
1 files changed, 4 insertions, 12 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index f96a4c3..20c7ebc 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -251,13 +251,10 @@ _start_e500:
*/
bl tlb1_entry
mr r5,r0
- li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */
- mtctr r1
lwzu r4,0(r5) /* how many TLB1 entries we actually use */
+ mtctr r4
-0: cmpwi r4,0
- beq 1f
- lwzu r0,4(r5)
+0: lwzu r0,4(r5)
lwzu r1,4(r5)
lwzu r2,4(r5)
lwzu r3,4(r5)
@@ -269,7 +266,6 @@ _start_e500:
msync
tlbwe
isync
- addi r4,r4,-1
bdnz 0b
1:
@@ -301,20 +297,16 @@ _start_e500:
bl law_entry
mr r6,r0
- li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */
- mtctr r1
lwzu r5,0(r6) /* how many windows we actually use */
+ mtctr r5
li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
li r1,0x0c30
-0: cmpwi r5,0
- beq 1f
- lwzu r4,4(r6)
+0: lwzu r4,4(r6)
lwzu r3,4(r6)
stwx r4,r7,r2
stwx r3,r7,r1
- addi r5,r5,-1
addi r2,r2,0x0020
addi r1,r1,0x0020
bdnz 0b