diff options
| author | Alessandro Rubini <rubini@unipv.it> | 2009-11-25 23:41:51 +0100 |
|---|---|---|
| committer | trix <trix@windriver.com> | 2010-04-03 15:24:27 -0500 |
| commit | 4b894a97d307c3207af40031d9e820e2960de57f (patch) | |
| tree | 45deb796599283759f8ec3b5d0a426f55fb6a037 /cpu | |
| parent | f936aa0528fe4f5d86168575528e0c52b485c642 (diff) | |
| download | u-boot-imx-4b894a97d307c3207af40031d9e820e2960de57f.zip u-boot-imx-4b894a97d307c3207af40031d9e820e2960de57f.tar.gz u-boot-imx-4b894a97d307c3207af40031d9e820e2960de57f.tar.bz2 | |
Nomadik: fix reset_timer()
Previous code was failing when reading back the timer less than
400us after resetting it. This lead nand operations to incorrectly
timeout any now and then. Moreover, writing the load register isn't
immediately reflected in the value register. We must wait for a clock
edge, so read_timer now waits for the value to change at least once,
otherwise nand operation would timeout anyways (though less frequently).
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm926ejs/nomadik/timer.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c index 047b9e3..1d98ef3 100644 --- a/cpu/arm926ejs/nomadik/timer.c +++ b/cpu/arm926ejs/nomadik/timer.c @@ -34,8 +34,8 @@ #define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) #define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) -/* macro to read the 32 bit timer: since it decrements, we invert read value */ -#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0))) +/* macro to read the decrementing 32 bit timer as an increasing count */ +#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0))) /* Configure a free-running, auto-wrap counter with no prescaler */ int timer_init(void) @@ -49,7 +49,16 @@ int timer_init(void) /* Restart counting from 0 */ void reset_timer(void) { - writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */ + ulong val; + writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); + /* + * The load-register isn't really immediate: it changes on clock + * edges, so we must wait for our newly-written value to appear. + * Since we might miss reading 0, wait for any change in value. + */ + val = READ_TIMER(); + while (READ_TIMER() == val) + ; } /* Return how many HZ passed since "base" */ |