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| author | Kumar Gala <galak@kernel.crashing.org> | 2007-11-27 23:25:02 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2007-12-11 22:34:19 -0600 |
| commit | f59b55a5b8fcadaa99781ba48e7a38e956afa527 (patch) | |
| tree | 6760b9b27fea80ab62af85758bfd18c902fa4760 /cpu | |
| parent | 50c03c8cf494d91cdec39670d95337c743e16ec9 (diff) | |
| download | u-boot-imx-f59b55a5b8fcadaa99781ba48e7a38e956afa527.zip u-boot-imx-f59b55a5b8fcadaa99781ba48e7a38e956afa527.tar.gz u-boot-imx-f59b55a5b8fcadaa99781ba48e7a38e956afa527.tar.bz2 | |
Stop using immap_t for guts offset on 85xx
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers
instead of getting it via &immap->im_gur.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc85xx/pci.c | 2 | ||||
| -rw-r--r-- | cpu/mpc85xx/qe_io.c | 4 | ||||
| -rw-r--r-- | cpu/mpc85xx/spd_sdram.c | 2 | ||||
| -rw-r--r-- | cpu/mpc85xx/speed.c | 3 |
4 files changed, 5 insertions, 6 deletions
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index db09e45..35e96d9 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -48,7 +48,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) #ifdef CONFIG_MPC85XX_PCI2 volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2; #endif - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); struct pci_controller * hose; pci_hose = board_hose; diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c index 8878bc5..98075bb 100644 --- a/cpu/mpc85xx/qe_io.c +++ b/cpu/mpc85xx/qe_io.c @@ -34,9 +34,9 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile par_io_t *par_io = (volatile par_io_t *) - &(im->im_gur.qe_par_io); + &(gur->qe_par_io); /* Caculate pin location and 2bit mask and dir */ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 5dc223a..307ba3b 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -309,7 +309,7 @@ spd_sdram(void) if ((SVR_VER(get_svr()) == SVR_8548_E) && (SVR_MJREV(get_svr()) == 1) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); gur->ddrioovcr = (0x80000000 /* Enable */ | 0x10000000);/* VSEL to 1.8V */ } diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 12359a2..5c35d4a 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -35,8 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info (sys_info_t * sysInfo) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint plat_ratio,e500_ratio,half_freqSystemBus; plat_ratio = (gur->porpllsr) & 0x0000003e; |