arm: clean cache management

unify arm cache management except for non standard cache as ARM7TDMI

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

13 files changed, 103 insertions, 620 deletions

diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
index 0abe307..78f6e92 100644
--- a/cpu/arm1136/cpu.c
+++ b/cpu/arm1136/cpu.c
@@ -39,13 +39,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-static void cp_delay (void)
-{
-	volatile int i;
-
-	/* Many OMAP regs need at least 2 nops  */
-	for (i = 0; i < 100; i++);
-}
+static void cache_flush(void);
 
 int cpu_init (void)
 {
@@ -68,8 +62,6 @@ int cleanup_before_linux (void)
 	 * we turn off caches etc ...
 	 */
 
-	unsigned long i;
-
 	disable_interrupts ();
 
 #ifdef CONFIG_LCD
@@ -83,15 +75,12 @@ int cleanup_before_linux (void)
 #endif
 
 	/* turn off I/D-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(CR_C | CR_I);
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
+	icache_disable();
+	dcache_disable();
 	/* flush I/D-cache */
-	i = 0;
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
-	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
-	return(0);
+	cache_flush();
+
+	return 0;
 }
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -102,25 +91,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return(0);
 }
 
-void icache_enable (void)
+static void cache_flush(void)
 {
-	ulong reg;
+	unsigned long i = 0;
 
-	reg = get_cr ();	/* get control reg. */
-	cp_delay ();
-	set_cr (reg | CR_I);
-}
-
-void icache_disable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg & ~CR_I);
-}
-
-int icache_status (void)
-{
-	return(get_cr () & CR_I) != 0;
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
+	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
 }
diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c
index ef78bd9..8aefbe3 100644
--- a/cpu/arm1176/cpu.c
+++ b/cpu/arm1176/cpu.c
@@ -38,15 +38,6 @@
 
 static void cache_flush (void);
 
-static void cp_delay (void)
-{
-	volatile int i;
-
-	/* Many OMAP regs need at least 2 nops  */
-	for (i = 0; i < 100; i++)
-		__asm__ __volatile__("nop\n");
-}
-
 int cpu_init (void)
 {
 	return 0;
@@ -66,6 +57,7 @@ int cleanup_before_linux (void)
 	/* turn off I/D-cache */
 	icache_disable();
 	dcache_disable();
+	/* flush I/D-cache */
 	cache_flush();
 
 	return 0;
@@ -95,53 +87,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-void icache_enable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();	/* get control reg. */
-	cp_delay ();
-	set_cr (reg | CR_I);
-}
-
-void icache_disable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg & ~CR_I);
-}
-
-int icache_status (void)
-{
-	return (get_cr () & CR_I) != 0;
-}
-
-/* It makes no sense to use the dcache if the MMU is not enabled */
-void dcache_enable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg | CR_C);
-}
-
-void dcache_disable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg & ~CR_C);
-}
-
-int dcache_status (void)
-{
-	return (get_cr () & CR_C) != 0;
-}
-
 /* flush I/D-cache */
 static void cache_flush (void)
 {
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c
index d178e41..a6f5c4d 100644
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -36,6 +36,10 @@
 #include <asm/hardware.h>
 #include <asm/system.h>
 
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
+static void cache_flush(void);
+#endif
+
 int cpu_init (void)
 {
 	/*
@@ -59,17 +63,14 @@ int cleanup_before_linux (void)
 	 */
 
 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-	unsigned long i;
-
 	disable_interrupts ();
 
 	/* turn off I-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~0x1000;
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	icache_disable();
+	dcache_disable();
 
 	/* flush I-cache */
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+	cache_flush();
 #ifdef CONFIG_ARM7_REVD
 	/* go to high speed */
 	IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
@@ -93,64 +94,13 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (0);
 }
 
-/*
- * Instruction and Data cache enable and disable functions
- *
- */
-
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
-static void cp_delay (void)
-{
-	volatile int i;
-
-	/* copro seems to need some delay between reading and writing */
-	for (i = 0; i < 100; i++);
-}
-
-void icache_enable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg | CR_C);
-}
-
-void icache_disable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg & ~CR_C);
-}
-
-int icache_status (void)
-{
-	return (get_cr () & CR_C) != 0;
-}
-
-void dcache_enable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg | CR_C);
-}
-
-void dcache_disable (void)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-	ulong reg;
+	unsigned long i = 0;
 
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg & ~CR_C);
-}
-
-int dcache_status (void)
-{
-	return (get_cr () & CR_C) != 0;
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
 }
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 	/* No specific cache setup for IntegratorAP/CM720T as yet */
diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c
index 83ee3f3..08c9339 100644
--- a/cpu/arm920t/cpu.c
+++ b/cpu/arm920t/cpu.c
@@ -38,13 +38,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-static void cp_delay (void)
-{
-	volatile int i;
-
-	/* copro seems to need some delay between reading and writing */
-	for (i = 0; i < 100; i++);
-}
+static void cache_flush(void);
 
 int cpu_init (void)
 {
@@ -67,20 +61,15 @@ int cleanup_before_linux (void)
 	 * we turn off caches etc ...
 	 */
 
-	unsigned long i;
-
 	disable_interrupts ();
 
 	/* turn off I/D-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(CR_C | CR_I);
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
+	icache_disable();
+	dcache_disable();
 	/* flush I/D-cache */
-	i = 0;
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+	cache_flush();
 
-	return (0);
+	return 0;
 }
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -88,55 +77,13 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	disable_interrupts ();
 	reset_cpu (0);
 	/*NOTREACHED*/
-	return (0);
-}
-
-void icache_enable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();		/* get control reg. */
-	cp_delay ();
-	set_cr (reg | CR_I);
-}
-
-void icache_disable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg & ~CR_I);
-}
-
-int icache_status (void)
-{
-	return (get_cr () & CR_I) != 0;
-}
-
-#ifdef USE_920T_MMU
-/* It makes no sense to use the dcache if the MMU is not enabled */
-void dcache_enable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg | CR_C);
+	return 0;
 }
 
-void dcache_disable (void)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	reg &= ~CR_C;
-	set_cr (reg);
-}
+	unsigned long i = 0;
 
-int dcache_status (void)
-{
-	return (get_cr () & CR_C) != 0;
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
 }
-#endif
diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c
index 8d1b562..eb6364d 100644
--- a/cpu/arm925t/cpu.c
+++ b/cpu/arm925t/cpu.c
@@ -38,13 +38,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-static void cp_delay (void)
-{
-	volatile int i;
-
-	/* Many OMAP regs need at least 2 nops  */
-	for (i = 0; i < 100; i++);
-}
+static void cache_flush(void);
 
 int cpu_init (void)
 {
@@ -67,19 +61,16 @@ int cleanup_before_linux (void)
 	 * we turn off caches etc ...
 	 */
 
-	unsigned long i;
-
 	disable_interrupts ();
 
-	/* turn off I/D-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(CR_C | CR_I);
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
 	/* flush I/D-cache */
-	i = 0;
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-	return (0);
+	cache_flush();
+
+	return 0;
 }
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -90,25 +81,11 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (0);
 }
 
-void icache_enable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();		/* get control reg. */
-	cp_delay ();
-	set_cr (reg | CR_I);
-}
-
-void icache_disable (void)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-	ulong reg;
+	unsigned long i = 0;
 
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg & ~CR_I);
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
 }
 
-int icache_status (void)
-{
-	return (get_cr () & CR_I) != 0;
-}
diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index d1748c9..84c169e 100644
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -38,13 +38,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-static void cp_delay (void)
-{
-	volatile int i;
-
-	/* copro seems to need some delay between reading and writing */
-	for (i = 0; i < 100; i++);
-}
+static void cache_flush(void);
 
 int cpu_init (void)
 {
@@ -67,20 +61,16 @@ int cleanup_before_linux (void)
 	 * we turn off caches etc ...
 	 */
 
-	unsigned long i;
-
 	disable_interrupts ();
 
-	/* turn off I/D-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(CR_C | CR_I);
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
 	/* flush I/D-cache */
-	i = 0;
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+	cache_flush();
 
-	return (0);
+	return 0;
 }
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -91,52 +81,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (0);
 }
 
-/* cache_bit must be either CR_I or CR_C */
-static void cache_enable(uint32_t cache_bit)
-{
-	uint32_t reg;
-
-	reg = get_cr();	/* get control reg. */
-	cp_delay();
-	set_cr(reg | cache_bit);
-}
-
-/* cache_bit must be either CR_I or CR_C */
-static void cache_disable(uint32_t cache_bit)
-{
-	uint32_t reg;
-
-	reg = get_cr();
-	cp_delay();
-	set_cr(reg & ~cache_bit);
-}
-
-void icache_enable(void)
-{
-	cache_enable(CR_I);
-}
-
-void icache_disable(void)
-{
-	cache_disable(CR_I);
-}
-
-int icache_status(void)
-{
-	return (get_cr() & CR_I) != 0;
-}
-
-void dcache_enable(void)
-{
-	cache_enable(CR_C);
-}
-
-void dcache_disable(void)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-	cache_disable(CR_C);
-}
+	unsigned long i = 0;
 
-int dcache_status(void)
-{
-	return (get_cr() & CR_C) != 0;
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
 }
diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c
index 25684f2..8d0c533 100644
--- a/cpu/arm946es/cpu.c
+++ b/cpu/arm946es/cpu.c
@@ -38,13 +38,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-static void cp_delay (void)
-{
-	volatile int i;
-
-	/* copro seems to need some delay between reading and writing */
-	for (i = 0; i < 100; i++);
-}
+static void cache_flush(void);
 
 int cpu_init (void)
 {
@@ -67,8 +61,6 @@ int cleanup_before_linux (void)
 	 * we turn off caches etc ...
 	 */
 
-	unsigned long i;
-
 	disable_interrupts ();
 
 	/* ARM926E-S needs the protection unit enabled for the icache to have
@@ -76,15 +68,12 @@ int cleanup_before_linux (void)
 	 * should turn off the protection unit as well....
 	 */
 	/* turn off I/D-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(CR_C | CR_I);
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
+	icache_disable();
+	dcache_disable();
 	/* flush I/D-cache */
-	i = 0;
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-	asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
-	return (0);
+	cache_flush();
+
+	return 0;
 }
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -96,27 +85,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	/*NOTREACHED*/
 	return (0);
 }
-/* ARM926E-S needs the protection unit enabled for this to have any effect
-   - left for possible later use */
-void icache_enable (void)
-{
-	ulong reg;
 
-	reg = get_cr ();		/* get control reg. */
-	cp_delay ();
-	set_cr (reg | CR_I);
-}
-
-void icache_disable (void)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-	ulong reg;
+	unsigned long i = 0;
 
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg & ~CR_I);
-}
-
-int icache_status (void)
-{
-	return (get_cr () & CR_I) != 0;
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+	asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
 }
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 506dbec..64ee972 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -46,13 +46,6 @@ void l2cache_disable(void);
 
 static void cache_flush(void);
 
-static void cp_delay(void)
-{
-	/* Many OMAP regs need at least 2 nops */
-	asm("nop");
-	asm("nop");
-}
-
 int cpu_init(void)
 {
 	/*
@@ -111,33 +104,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-void icache_enable(void)
-{
-	ulong reg;
-
-	reg = get_cr();	/* get control reg. */
-	cp_delay();
-	set_cr(reg | CR_I);
-}
-
-void icache_disable(void)
-{
-	ulong reg;
-
-	reg = get_cr();
-	cp_delay();
-	set_cr(reg & ~CR_I);
-}
-
-void dcache_disable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg & ~CR_C);
-}
-
 void l2cache_enable()
 {
 	unsigned long i;
@@ -197,11 +163,6 @@ void l2cache_disable()
 	}
 }
 
-int icache_status(void)
-{
-	return (get_cr() & CR_I) != 0;
-}
-
 static void cache_flush(void)
 {
 	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c
index ccf7fd5..ea6747a 100644
--- a/cpu/arm_intcm/cpu.c
+++ b/cpu/arm_intcm/cpu.c
@@ -76,18 +76,3 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	/*NOTREACHED*/
 	return (0);
 }
-
-/* May not be cahed processor on the CM - do nothing */
-void icache_enable (void)
-{
-}
-
-void icache_disable (void)
-{
-}
-
-/* return "disabled" */
-int icache_status (void)
-{
-	return 0;
-}
diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c
index 265c820..d9cfbab 100644
--- a/cpu/ixp/cpu.c
+++ b/cpu/ixp/cpu.c
@@ -42,6 +42,8 @@ ulong loops_per_jiffy;
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
+static void cache_flush(void);
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo (void)
 {
@@ -99,19 +101,16 @@ int cleanup_before_linux (void)
 	 * just disable everything that can disturb booting linux
 	 */
 
-	unsigned long i;
-
 	disable_interrupts ();
 
 	/* turn off I-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~0x1000;
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	icache_disable();
+	dcache_disable();
 
 	/* flush I-cache */
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+	cache_flush();
 
-	return (0);
+	return 0;
 }
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -126,55 +125,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (0);
 }
 
-/* cache_bit must be either CR_I or CR_C */
-static void cache_enable(uint32_t cache_bit)
-{
-	uint32_t reg;
-
-	reg = get_cr();	/* get control reg. */
-	cp_delay();
-	set_cr(reg | cache_bit);
-}
-
-/* cache_bit must be either CR_I or CR_C */
-static void cache_disable(uint32_t cache_bit)
-{
-	uint32_t reg;
-
-	reg = get_cr();
-	cp_delay();
-	set_cr(reg & ~cache_bit);
-}
-
-void icache_enable(void)
-{
-	cache_enable(CR_I);
-}
-
-void icache_disable(void)
-{
-	cache_disable(CR_I);
-}
-
-int icache_status(void)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-	return (get_cr() & CR_I) != 0;
-}
+	unsigned long i = 0;
 
-/* we will never enable dcache, because we have to setup MMU first */
-void dcache_enable (void)
-{
-	return;
-}
-
-void dcache_disable (void)
-{
-	return;
-}
-
-int dcache_status (void)
-{
-	return 0;					/* always off */
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
 }
 
 /* FIXME */
diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c
index 2c6799f..e862251 100644
--- a/cpu/lh7a40x/cpu.c
+++ b/cpu/lh7a40x/cpu.c
@@ -38,13 +38,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-static void cp_delay (void)
-{
-	volatile int i;
-
-	/* copro seems to need some delay between reading and writing */
-	for (i = 0; i < 100; i++);
-}
+static void cache_flush(void);
 
 int cpu_init (void)
 {
@@ -67,19 +61,16 @@ int cleanup_before_linux (void)
 	 * we turn off caches etc ...
 	 */
 
-	unsigned long i;
-
 	disable_interrupts ();
 
 	/* turn off I/D-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(CR_C | CR_I);
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	icache_disable();
+	dcache_disable();
 
 	/* flush I/D-cache */
-	i = 0;
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-	return (0);
+	cache_flush();
+
+	return 0;
 }
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -90,52 +81,11 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (0);
 }
 
-void icache_enable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg | CR_I);
-}
 
-void icache_disable (void)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-	ulong reg;
+	unsigned long i = 0;
 
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg & ~CR_I);
-}
-
-int icache_status (void)
-{
-	return (get_cr () & CR_I) != 0;
-}
-
-#ifdef USE_920T_MMU
-/* It makes no sense to use the dcache if the MMU is not enabled */
-void dcache_enable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg | CR_C);
-}
-
-void dcache_disable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	reg &= ~CR_C;
-	set_cr (reg);
-}
-
-int dcache_status (void)
-{
-	return (get_cr () & CR_C) != 0;
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
 }
-#endif
diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index e27b6b9..ab58d39 100644
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -39,6 +39,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
+static void cache_flush(void);
+
 int cpu_init (void)
 {
 	/*
@@ -60,17 +62,14 @@ int cleanup_before_linux (void)
 	 * just disable everything that can disturb booting linux
 	 */
 
-	unsigned long i;
-
 	disable_interrupts ();
 
 	/* turn off I-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~0x1000;
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	icache_disable();
+	dcache_disable();
 
 	/* flush I-cache */
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+	cache_flush();
 
 	return (0);
 }
@@ -87,55 +86,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (0);
 }
 
-/* cache_bit must be either CR_I or CR_C */
-static void cache_enable(uint32_t cache_bit)
-{
-	uint32_t reg;
-
-	reg = get_cr();	/* get control reg. */
-	cp_delay();
-	set_cr(reg | cache_bit);
-}
-
-/* cache_bit must be either CR_I or CR_C */
-static void cache_disable(uint32_t cache_bit)
-{
-	uint32_t reg;
-
-	reg = get_cr();
-	cp_delay();
-	set_cr(reg & ~cache_bit);
-}
-
-void icache_enable(void)
-{
-	cache_enable(CR_I);
-}
-
-void icache_disable(void)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-	cache_disable(CR_I);
-}
+	unsigned long i = 0;
 
-int icache_status(void)
-{
-	return (get_cr() & CR_I) != 0;
-}
-
-/* we will never enable dcache, because we have to setup MMU first */
-void dcache_enable (void)
-{
-	return;
-}
-
-void dcache_disable (void)
-{
-	return;
-}
-
-int dcache_status (void)
-{
-	return 0;					/* always off */
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
 }
 
 #ifndef CONFIG_CPU_MONAHANS
diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c
index d0dfa3d..6c897d0 100644
--- a/cpu/sa1100/cpu.c
+++ b/cpu/sa1100/cpu.c
@@ -38,6 +38,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
+static void cache_flush(void);
+
 int cpu_init (void)
 {
 	/*
@@ -59,17 +61,14 @@ int cleanup_before_linux (void)
 	 * just disable everything that can disturb booting linux
 	 */
 
-	unsigned long i;
-
 	disable_interrupts ();
 
 	/* turn off I-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~0x1000;
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	icache_disable();
+	dcache_disable();
 
 	/* flush I-cache */
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+	cache_flush();
 
 	return (0);
 }
@@ -86,49 +85,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (0);
 }
 
-static void cp_delay (void)
-{
-	volatile int i;
-
-	/* copro seems to need some delay between reading and writing */
-	for (i = 0; i < 100; i++);
-}
-
-void icache_enable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg | CR_C);
-}
-
-void icache_disable (void)
-{
-	ulong reg;
-
-	reg = get_cr ();
-	cp_delay ();
-	set_cr (reg & ~CR_C);
-}
-
-int icache_status (void)
-{
-	return (get_cr () & CR_C) != 0;
-}
-
-/* we will never enable dcache, because we have to setup MMU first */
-void dcache_enable (void)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-	return;
-}
-
-void dcache_disable (void)
-{
-	return;
-}
+	unsigned long i = 0;
 
-int dcache_status (void)
-{
-	return 0;					/* always off */
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
 }