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| author | Stefan Roese <sr@denx.de> | 2007-10-13 16:43:23 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-10-31 21:20:50 +0100 |
| commit | d4cb2d17946466740afeb195a57d6cb290bf4cc0 (patch) | |
| tree | 81e5eee8d2e12c4714cd7ff213696b1a3b8f74ef /cpu | |
| parent | fd671802b67a0ef37a06124fa2ce85f00aa22c6f (diff) | |
| download | u-boot-imx-d4cb2d17946466740afeb195a57d6cb290bf4cc0.zip u-boot-imx-d4cb2d17946466740afeb195a57d6cb290bf4cc0.tar.gz u-boot-imx-d4cb2d17946466740afeb195a57d6cb290bf4cc0.tar.bz2 | |
ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode
This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.
This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:
pcie_mode=RP:EP:EP
This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.
Per default Yucca will be configured as:
pcie_mode=RP:EP:EP
Per default Katmai will be configured as:
pcie_mode=RP:RP:REP
Per default Kilauea will be configured as:
pcie_mode=RP:RP
Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/ppc4xx/4xx_pcie.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 7ee0e5b..9ab3588 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -46,6 +46,20 @@ enum { LNKW_X8 = 0x8 }; +static int validate_endpoint(struct pci_controller *hose) +{ + if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE) + return (is_end_point(0)); + else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE) + return (is_end_point(1)); +#if CFG_PCIE_NR_PORTS > 2 + else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE) + return (is_end_point(2)); +#endif + + return 0; +} + static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) { u8 *base = (u8*)hose->cfg_data; @@ -95,6 +109,9 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, u8 *address; *val = 0; + if (validate_endpoint(hose)) + return 0; /* No upstream config access */ + /* * Bus numbers are relative to hose->first_busno */ @@ -150,6 +167,9 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, u8 *address; + if (validate_endpoint(hose)) + return 0; /* No upstream config access */ + /* * Bus numbers are relative to hose->first_busno */ @@ -595,9 +615,9 @@ int ppc4xx_init_pcie_port(int port, int rootport) u32 low, high; if (!core_init) { - ++core_init; if (ppc4xx_init_pcie()) return -1; + ++core_init; } /* |