Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board.

Patch by John Otken, 23 Nov 2005

8 files changed, 189 insertions, 103 deletions

diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 6a4128c..64431ab 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -437,11 +437,11 @@ void pci_440_init (struct pci_controller *hose)
 	 * The PCI initialization sequence enable bit must be set ... if not abort
 	 * pci setup since updating the bit requires chip reset.
 	 *--------------------------------------------------------------------------*/
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 	unsigned long strap;
 
 	mfsdr(sdr_sdstp1,strap);
-	if ( (strap & 0x00010000) == 0 ){
+	if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
 		printf("PCI: SDR0_STRP1[PISE] not set.\n");
 		printf("PCI: Configuration aborted.\n");
 		return;
@@ -450,7 +450,7 @@ void pci_440_init (struct pci_controller *hose)
 	unsigned long strap;
 
 	strap = mfdcr(cpc0_strp1);
-	if( (strap & 0x00040000) == 0 ){
+	if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
 		printf("PCI: CPC0_STRP1[PISE] not set.\n");
 		printf("PCI: Configuration aborted.\n");
 		return;
@@ -466,26 +466,26 @@ void pci_440_init (struct pci_controller *hose)
 
 	pci_set_region(hose->regions + reg_num++,
 		       0x00000000,
-			   PCIX0_IOBASE,
-			   0x10000,
-			   PCI_REGION_IO);
+		       PCIX0_IOBASE,
+		       0x10000,
+		       PCI_REGION_IO);
 
 	pci_set_region(hose->regions + reg_num++,
 		       CFG_PCI_TARGBASE,
-			   CFG_PCI_MEMBASE,
-			   0x10000000,
-			   PCI_REGION_MEM );
+		       CFG_PCI_MEMBASE,
+		       0x10000000,
+		       PCI_REGION_MEM );
 	hose->region_count = reg_num;
 
 	pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
 
 #if defined(CFG_PCI_PRE_INIT)
-    /* Let board change/modify hose & do initial checks */
-    if( pci_pre_init (hose) == 0 ){
-	printf("PCI: Board-specific initialization failed.\n");
-	printf("PCI: Configuration aborted.\n");
-	return;
-    }
+	/* Let board change/modify hose & do initial checks */
+	if (pci_pre_init (hose) == 0) {
+		printf("PCI: Board-specific initialization failed.\n");
+		printf("PCI: Configuration aborted.\n");
+		return;
+	}
 #endif
 
 	pci_register_hose( hose );
@@ -496,9 +496,9 @@ void pci_440_init (struct pci_controller *hose)
 #if defined(CFG_PCI_TARGET_INIT)
 	pci_target_init(hose);                /* Let board setup pci target */
 #else
-    out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-    out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
-    out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
+	out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
 #endif
 
 #if defined(CONFIG_440GX)
@@ -524,24 +524,24 @@ void pci_440_init (struct pci_controller *hose)
 	out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
 	out32r( PCIX0_POM0PCIAH, 0x00000000 );
 	out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
-    out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
+	out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
 #endif
 
 	/*--------------------------------------------------------------------------+
 	 * PCI host configuration -- we don't make any assumptions here ... the
-     * _board_must_indicate_ what to do -- there's just too many runtime
-     * scenarios in environments like cPCI, PPMC, etc. to make a determination
-     * based on hard-coded values or state of arbiter enable.
+	 * _board_must_indicate_ what to do -- there's just too many runtime
+	 * scenarios in environments like cPCI, PPMC, etc. to make a determination
+	 * based on hard-coded values or state of arbiter enable.
 	 *--------------------------------------------------------------------------*/
-    if( is_pci_host(hose) ){
+	if (is_pci_host(hose)) {
 #ifdef CONFIG_PCI_SCAN_SHOW
-	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+		printf("PCI:   Bus Dev VenId DevId Class Int\n");
 #endif
 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
-	out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
+		out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
 #endif
-	hose->last_busno = pci_hose_scan(hose);
-    }
+		hose->last_busno = pci_hose_scan(hose);
+	}
 }
 
 
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 8423cc3..86dc2d0 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -314,9 +314,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	unsigned mode_reg;
 	unsigned short devnum;
 	unsigned short reg_short;
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 	sys_info_t sysinfo;
-	int ethgroup;
+#if defined(CONFIG_440GX)
+	int ethgroup = -1;
+#endif
 #endif
 
 	EMAC_4XX_HW_PST hw_p = dev->priv;
@@ -328,7 +330,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		return -1;
 	}
 
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 	/* Need to get the OPB frequency so we can access the PHY */
 	get_sys_info (&sysinfo);
 #endif
@@ -371,7 +373,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	hw_p->tx_i_index = 0;	/* Transmit Interrupt Queue Index */
 	hw_p->tx_u_index = 0;	/* Transmit User Queue Index */
 
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) && !defined(CONFIG_440SP)
 	/* set RMII mode */
 	/* NOTE: 440GX spec states that mode is mutually exclusive */
 	/* NOTE: Therefore, disable all other EMACS, since we handle */
@@ -399,7 +401,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #endif
 
 	out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
-#endif /* defined(CONFIG_440) */
+#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
 
 	__asm__ volatile ("eieio");
 
@@ -414,7 +416,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		failsafe--;
 	}
 
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 	/* Whack the M1 register */
 	mode_reg = 0x0;
 	mode_reg &= ~0x00000038;
@@ -429,7 +431,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		mode_reg |= EMAC_M1_OBCI_GT100;
 
 	out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
-#endif /*  defined(CONFIG_440GX) */
+#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
 
 	/* wait for PHY to complete auto negotiation */
 	reg_short = 0;
@@ -466,7 +468,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	if (hw_p->first_init == 0) {
 		miiphy_reset (dev->name, reg);
 
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 #if defined(CONFIG_CIS8201_PHY)
 		/*
 		 * Cicada 8201 PHY needs to have an extended register whacked
@@ -542,7 +544,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 			(int) speed, (duplex == HALF) ? "HALF" : "FULL");
 	}
 
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) && !defined(CONFIG_440SP)
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	mfsdr(sdr_mfr, reg);
 	if (speed == 100) {
@@ -570,10 +572,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 
 		out32 (RGMII_SSR, reg);
 	}
-#endif /* defined(CONFIG_440) */
+#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
 
 	/* set the Mal configuration reg */
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 	mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
 	       MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
 #else
@@ -756,9 +758,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
 
 	/* set speed */
-	if (speed == _1000BASET)
+	if (speed == _1000BASET) {
+#if defined(CONFIG_440SP)
+#define SDR0_PFC1_EM_1000	0x00200000
+		unsigned long pfc1;
+		mfsdr (sdr_pfc1, pfc1);
+		pfc1 |= SDR0_PFC1_EM_1000;
+		mtsdr (sdr_pfc1, pfc1);
+#endif
 		mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
-	else if (speed == _100BASET)
+	} else if (speed == _100BASET)
 		mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
 	else
 		mode_reg = mode_reg & ~0x00C00000;	/* 10 MBPS */
@@ -883,8 +892,21 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
 	}
 }
 
+
 #if defined (CONFIG_440)
 
+#if defined(CONFIG_440SP)
+/*
+ * Hack: On 440SP all enet irq sources are located on UIC1
+ * Needs some cleanup. --sr
+ */
+#define UIC0MSR		uic1msr
+#define UIC0SR		uic1sr
+#else
+#define UIC0MSR		uic0msr
+#define UIC0SR		uic0sr
+#endif
+
 int enetInt (struct eth_device *dev)
 {
 	int serviced;
@@ -911,20 +933,17 @@ int enetInt (struct eth_device *dev)
 
 	hw_p = dev->priv;
 
-
 	/* enter loop that stays in interrupt code until nothing to service */
 	do {
 		serviced = 0;
 
-		my_uic0msr = mfdcr (uic0msr);
+		my_uic0msr = mfdcr (UIC0MSR);
 		my_uic1msr = mfdcr (uic1msr);
 #if defined(CONFIG_440GX)
 		my_uic2msr = mfdcr (uic2msr);
 #endif
 		if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
-		    && !(my_uic1msr &
-			 (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
-			  UIC_MRDE))) {
+		    && !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
 			/* not for us */
 			return (rc);
 		}
@@ -962,12 +981,13 @@ int enetInt (struct eth_device *dev)
 			}
 			if ((hw_p->emac_ier & emac_isr)
 			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
-				mtdcr (uic0sr, UIC_MRE | UIC_MTE);	/* Clear */
+				mtdcr (UIC0SR, UIC_MRE | UIC_MTE);	/* Clear */
 				mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
 				return (rc);	/* we had errors so get out */
 			}
 		}
 
+#if !defined(CONFIG_440SP)
 		if (hw_p->devnum == 1) {
 			if (UIC_ETH1 & my_uic1msr) {	/* look for EMAC errors */
 				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
@@ -979,7 +999,7 @@ int enetInt (struct eth_device *dev)
 			}
 			if ((hw_p->emac_ier & emac_isr)
 			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
-				mtdcr (uic0sr, UIC_MRE | UIC_MTE);	/* Clear */
+				mtdcr (UIC0SR, UIC_MRE | UIC_MTE);	/* Clear */
 				mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
 				return (rc);	/* we had errors so get out */
 			}
@@ -996,7 +1016,7 @@ int enetInt (struct eth_device *dev)
 			}
 			if ((hw_p->emac_ier & emac_isr)
 			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
-				mtdcr (uic0sr, UIC_MRE | UIC_MTE);	/* Clear */
+				mtdcr (UIC0SR, UIC_MRE | UIC_MTE);	/* Clear */
 				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
 				mtdcr (uic2sr, UIC_ETH2);
 				return (rc);	/* we had errors so get out */
@@ -1014,18 +1034,20 @@ int enetInt (struct eth_device *dev)
 			}
 			if ((hw_p->emac_ier & emac_isr)
 			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
-				mtdcr (uic0sr, UIC_MRE | UIC_MTE);	/* Clear */
+				mtdcr (UIC0SR, UIC_MRE | UIC_MTE);	/* Clear */
 				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
 				mtdcr (uic2sr, UIC_ETH3);
 				return (rc);	/* we had errors so get out */
 			}
 		}
 #endif /* CONFIG_440GX */
+#endif /* !CONFIG_440SP */
+
 		/* handle MAX TX EOB interrupt from a tx */
 		if (my_uic0msr & UIC_MTE) {
 			mal_rx_eob = mfdcr (maltxeobisr);
 			mtdcr (maltxeobisr, mal_rx_eob);
-			mtdcr (uic0sr, UIC_MTE);
+			mtdcr (UIC0SR, UIC_MTE);
 		}
 		/* handle MAL RX EOB  interupt from a receive */
 		/* check for EOB on valid channels	      */
@@ -1040,7 +1062,8 @@ int enetInt (struct eth_device *dev)
 				rc = 0;
 			}
 		}
-		mtdcr (uic0sr, UIC_MRE);	/* Clear */
+
+		mtdcr (UIC0SR, UIC_MRE);	/* Clear */
 		mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
 		switch (hw_p->devnum) {
 		case 0:
@@ -1489,7 +1512,7 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 #endif
 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
 		miiphy_register (dev->name,
-				emac4xx_miiphy_read, emac4xx_miiphy_write);
+				 emac4xx_miiphy_read, emac4xx_miiphy_write);
 #endif
 
 	}			/* end for each supported device */
@@ -1531,7 +1554,7 @@ int emac4xx_miiphy_initialize (bd_t * bis)
 {
 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
 	miiphy_register ("ppc_4xx_eth0",
-			emac4xx_miiphy_read, emac4xx_miiphy_write);
+			 emac4xx_miiphy_read, emac4xx_miiphy_write);
 #endif
 
 	return 0;
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 6c61953..0b5883c 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -38,40 +38,73 @@
 #include <ppc4xx.h>
 
 
-#if defined(CONFIG_405GP)
-#define PCI_ARBITER_ENABLED	(mfdcr(strap) & PSR_PCI_ARBIT_EN)
-#define PCI_ASYNC_ENABLED	(mfdcr(strap) & PSR_PCI_ASYNC_EN)
+#if defined(CONFIG_440)
+#define FREQ_EBC		(sys_info.freqEPB)
+#else
+#define FREQ_EBC		(sys_info.freqPLB / sys_info.pllExtBusDiv)
 #endif
 
-#if defined(CONFIG_405EP)
-#define PCI_ARBITER_ENABLED	(mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN)
-#define I2C_BOOTROM_ENABLED	(mfdcr(cpc0_boot) & CPC0_BOOT_SEP)
+#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+#define PCI_ASYNC
+
+int pci_async_enabled(void)
+{
+#if defined(CONFIG_405GP)
+	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
 #endif
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define SDR0_SDSTP1_PAE		(0x80000000 >> 21)
-#define SDR0_SDSTP1_PAME	(0x80000000 >> 27)
+	unsigned long val;
 
-#define PCI_ARBITER_ENABLED	(mfdcr(cpc0_strp1) & SDR0_SDSTP1_PAE)
-#define PCI_ASYNC_ENABLED	(mfdcr(cpc0_strp1) & SDR0_SDSTP1_PAME)
+	mfsdr(cpc0_strp1, val);
+	return (val & SDR0_SDSTP1_PAME_MASK);
+#endif
+}
+#endif
+
+#if defined(CONFIG_PCI)
+int pci_arbiter_enabled(void)
+{
+#if defined(CONFIG_405GP)
+	return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
+#endif
+
+#if defined(CONFIG_405EP)
+	return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
 #endif
 
 #if defined(CONFIG_440GP)
-#define CPC0_STRP1_PAE		(0x80000000 >> 11)
+	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+	unsigned long val;
 
-#define PCI_ARBITER_ENABLED	(mfdcr(cpc0_strp1) & CPC0_STRP1_PAE)
+	mfsdr(sdr_sdstp1, val);
+	return (val & SDR0_SDSTP1_PAE_MASK);
 #endif
+}
+#endif
+
+#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+	defined(CONFIG_440GX) || defined(CONFIG_440SP)
 
-#if defined(CONFIG_440GX)
-#define SDR0_SDSTP1_PAE		(0x80000000 >> 13)
+#define I2C_BOOTROM
 
-#define PCI_ARBITER_ENABLED	(mfdcr(cpc0_strp1) & SDR0_SDSTP1_PAE)
+int i2c_bootrom_enabled(void)
+{
+#if defined(CONFIG_405EP)
+	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
 #endif
 
-#if defined(CONFIG_440)
-#define FREQ_EBC		(sys_info.freqEPB)
-#else
-#define FREQ_EBC		(sys_info.freqPLB / sys_info.pllExtBusDiv)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+	unsigned long val;
+
+	mfsdr(sdr_sdcs, val);
+	return (val & SDR0_SDCS_SDD);
+#endif
+}
 #endif
 
 
@@ -196,6 +229,14 @@ int checkcpu (void)
 #endif /* CONFIG_440GR */
 #endif /* CONFIG_440 */
 
+	case PVR_440SP_RA:
+		puts("SP Rev. A");
+		break;
+
+	case PVR_440SP_RB:
+		puts("SP Rev. B");
+		break;
+
 	default:
 		printf (" UNKNOWN (PVR=%08x)", pvr);
 		break;
@@ -206,17 +247,16 @@ int checkcpu (void)
 	       sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
 	       FREQ_EBC / 1000000);
 
-#if defined(I2C_BOOTROM_ENABLED)
-	printf ("       IIC Boot EEPROM %sabled\n", I2C_BOOTROM_ENABLED ? "en" : "dis");
+#if defined(I2C_BOOTROM)
+	printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
 #endif
 
-#if defined(PCI_ARBITER_ENABLED)
-	printf ("       %sternal PCI arbiter enabled",
-		(PCI_ARBITER_ENABLED) ? "In" : "Ex");
+#if defined(CONFIG_PCI)
+	printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
 #endif
 
-#if defined(PCI_ASYNC_ENABLED)
-	if (PCI_ASYNC_ENABLED) {
+#if defined(PCI_ASYNC)
+	if (pci_async_enabled()) {
 		printf (", PCI async ext clock used");
 	} else {
 		printf (", PCI sync clock at %lu MHz",
@@ -224,7 +264,7 @@ int checkcpu (void)
 	}
 #endif
 
-#if defined(PCI_ARBITER_ENABLED) || defined(PCI_ASYNC_ENABLED)
+#if defined(CONFIG_PCI)
 	putc('\n');
 #endif
 
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index f319eb8..f26f2a2 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -104,7 +104,7 @@ int phy_setup_aneg (char *devname, unsigned char addr)
 /***********************************************************/
 unsigned int miiphy_getemac_offset (void)
 {
-#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
+#if (defined(CONFIG_440) && !defined(CONFIG_440SP)) && defined(CONFIG_NET_MULTI)
 	unsigned long zmii;
 	unsigned long eoffset;
 
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index e06fb0d..e7f6bcb 100644
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -276,7 +276,12 @@ int serial_tstc ()
 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000200
 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000300
 #endif
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+#if defined(CONFIG_440SP)
+#define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000600
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
 #define CR0_MASK        0xdfffffff
 #define CR0_EXTCLK_ENA  0x00800000
 #define CR0_UDIV_POS    0
@@ -306,14 +311,14 @@ int serial_tstc ()
 #if defined(CONFIG_UART1_CONSOLE)
 #define ACTING_UART0_BASE	UART1_BASE
 #define ACTING_UART1_BASE	UART0_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
 #define UART0_SDR           sdr_uart1
 #define UART1_SDR           sdr_uart0
 #endif /* CONFIG_440GX */
 #else
 #define ACTING_UART0_BASE	UART0_BASE
 #define ACTING_UART1_BASE	UART1_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
 #define UART0_SDR           sdr_uart0
 #define UART1_SDR           sdr_uart1
 #endif /* CONFIG_440GX */
@@ -436,7 +441,7 @@ int serial_init(void)
 	unsigned long tmp;
 #endif
 
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 #if defined(CONFIG_SERIAL_MULTI)
 	if (UART0_BASE == dev_base) {
 		mfsdr(UART0_SDR,reg);
@@ -465,7 +470,7 @@ int serial_init(void)
 	serial_divs (gd->baudrate, &udiv, &bdiv);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
 	reg |= udiv << CR0_UDIV_POS;	/* set the UART divisor */
 #if defined(CONFIG_SERIAL_MULTI)
 	if (UART0_BASE == dev_base) {
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index cbd7b24..553c491 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -283,7 +283,7 @@ ulong get_PCI_freq (void)
 	return sys_info.freqPCI;
 }
 
-#elif !defined(CONFIG_440GX)
+#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP)
 void get_sys_info (sys_info_t * sysInfo)
 {
 	unsigned long strp0;
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 8f7e817..48b430d 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -166,7 +166,7 @@ _start_440:
 	mtspr	srr1,r0
 	mtspr	csrr0,r0
 	mtspr	csrr1,r0
-#if defined (CONFIG_440GX) /* NOTE: 440GX adds machine check status regs */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) /* NOTE: 440GX adds machine check status regs */
 	mtspr	mcsrr0,r0
 	mtspr	mcsrr1,r0
 	mfspr	r1, mcsr
@@ -394,7 +394,7 @@ __440gx_msr_continue:
 	addi	r3,r3,32
 	bdnz	..d_ag
 #else
-#if defined (CONFIG_440GX)
+#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
 	mtdcr	l2_cache_cfg,r0		/* Ensure L2 Cache is off */
 #endif
 	mtdcr	isram0_sb1cr,r0		/* Disable bank 1 */
@@ -409,7 +409,7 @@ __440gx_msr_continue:
 	mtdcr	isram0_pmeg,r1
 
 	lis	r1,0x8000		/* BAS = 8000_0000 */
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 	ori	r1,r1,0x0980		/* first 64k */
 	mtdcr	isram0_sb0cr,r1
 	lis	r1,0x8001
@@ -432,7 +432,6 @@ __440gx_msr_continue:
 	/*----------------------------------------------------------------*/
 	lis	r1,CFG_INIT_RAM_ADDR@h
 	ori	r1,r1,CFG_INIT_SP_OFFSET@l
-
 	li	r0,0
 	stwu	r0,-4(r1)
 	stwu	r0,-4(r1)		/* Terminate call chain */
@@ -977,12 +976,8 @@ invalidate_icache:
 invalidate_dcache:
 	addi	r6,0,0x0000		/* clear GPR 6 */
 	/* Do loop for # of dcache congruence classes. */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	lis	r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS for large sized cache */
 	ori	r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
-#else
-	addi	r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
-#endif
 					/* NOTE: dccci invalidates both */
 	mtctr	r7			/* ways in the D cache */
 ..dcloop:
@@ -1003,15 +998,10 @@ flush_dcache:
 	mtdccr	r10
 
 	/* do loop for # of congruence classes. */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	lis	r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS: for large cache sizes */
 	ori	r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
 	lis	r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
 	ori	r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
-#else
-	addi	r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
-	addi	r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
-#endif
 	mtctr	r10
 	addi	r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
 	add	r11,r10,r11		/* add to get to other side of cache line */
@@ -1233,9 +1223,9 @@ relocate_code:
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	dccci	0,0			    /* Invalidate data cache, now no longer our stack */
 	sync
-	addi	r1,r0,0x0000	    /* Tlb entry #0 */
+	addi	r1,r0,0x0000		/* TLB entry #0 */
 	tlbre	r0,r1,0x0002		/* Read contents */
-	ori	r0,r0,0x0c00	    /* Or in the inhibit, write through bit */
+	ori	r0,r0,0x0c00		/* Or in the inhibit, write through bit */
 	tlbwe	r0,r1,0x0002		/* Save it out */
 	isync
 #endif
diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h
index 1038975..cbfe41d 100644
--- a/cpu/ppc4xx/vecnum.h
+++ b/cpu/ppc4xx/vecnum.h
@@ -31,7 +31,35 @@
 #ifndef _VECNUMS_H_
 #define _VECNUMS_H_
 
-#if defined(CONFIG_440)
+#if defined(CONFIG_440SP)
+
+/* UIC 0 */
+#define VECNUM_U0           0           /* UART0                        */
+#define VECNUM_U1           1           /* UART1                        */
+#define VECNUM_IIC0         2           /* IIC0                         */
+#define VECNUM_IIC1         3           /* IIC1                         */
+#define VECNUM_PIM          4           /* PCI inbound message          */
+#define VECNUM_PCRW         5           /* PCI command reg write        */
+#define VECNUM_PPM          6           /* PCI power management         */
+#define VECNUM_UIC1NC       30          /* UIC1 non-critical interrupt  */
+#define VECNUM_UIC1C        31          /* UIC1 critical interrupt      */
+
+/* UIC 1 */
+#define VECNUM_EIR0         (32 + 0)	/* External interrupt 0         */
+#define VECNUM_MS           (32 + 1)	/* MAL SERR                     */
+#define VECNUM_TXDE         (32 + 2)	/* MAL TXDE                     */
+#define VECNUM_RXDE         (32 + 3)	/* MAL RXDE                     */
+#define VECNUM_MTE          (32 + 6)	/* MAL Tx EOB                   */
+#define VECNUM_MRE          (32 + 7)	/* MAL Rx EOB                   */
+#define VECNUM_CT0          (32 + 12)	/* GPT compare timer 0          */
+#define VECNUM_CT1          (32 + 13)	/* GPT compare timer 1          */
+#define VECNUM_CT2          (32 + 14)	/* GPT compare timer 2          */
+#define VECNUM_CT3          (32 + 15)	/* GPT compare timer 3          */
+#define VECNUM_CT4          (32 + 16)	/* GPT compare timer 4          */
+#define VECNUM_ETH0         (32 + 28)	/* Ethernet interrupt status    */
+#define VECNUM_EWU0         (32 + 29)	/* Emac  wakeup                 */
+
+#elif defined(CONFIG_440)
 
 /* UIC 0 */
 #define VECNUM_U0           0           /* UART0                        */