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| author | Wolfgang Denk <wd@denx.de> | 2008-01-10 00:49:59 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-01-10 00:49:59 +0100 |
| commit | 694976afa5dcc5c4e7eaeaa0612eac35cd5bd8ec (patch) | |
| tree | 711b1a20a1bab99fc304b6fa55374daf35f4919c /cpu | |
| parent | 80adb2761627ec10eb8997bea6c1e52e34816c6b (diff) | |
| parent | 17a41e4492121ccf9fa2c10c2cb1a6d1c18d74f7 (diff) | |
| download | u-boot-imx-694976afa5dcc5c4e7eaeaa0612eac35cd5bd8ec.zip u-boot-imx-694976afa5dcc5c4e7eaeaa0612eac35cd5bd8ec.tar.gz u-boot-imx-694976afa5dcc5c4e7eaeaa0612eac35cd5bd8ec.tar.bz2 | |
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc85xx/fdt.c | 5 | ||||
| -rw-r--r-- | cpu/mpc85xx/spd_sdram.c | 23 | ||||
| -rw-r--r-- | cpu/mpc85xx/start.S | 9 |
3 files changed, 21 insertions, 16 deletions
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 737a6c4..0ce17e7 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -43,8 +43,11 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); #ifdef CONFIG_QE - do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + do_fixup_by_prop_u32(blob, "device_type", "qe", 4, "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "qe", 4, + "brg-frequency", bd->bi_busfreq / 2, 1); + fdt_fixup_qe_firmware(blob); #endif #ifdef CFG_NS16550 diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 553f736..adc9c4d 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1071,22 +1071,19 @@ setup_laws_and_tlbs(unsigned int memsize) ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize * 1024 * 1024) && ram_tlb_index < 16) { - mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0)); - mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size)); - mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), - 0, 0, 0, 0, 0, 0, 0, 0)); - mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), - 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); + mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0)); + mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size)); + mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0)); + mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))); asm volatile("isync;msync;tlbwe;isync"); - debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0)); - debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size)); - debug("DDR: MAS2=0x%08x\n", - TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), - 0, 0, 0, 0, 0, 0, 0, 0)); + debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0)); + debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size)); + debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0)); debug("DDR: MAS3=0x%08x\n", - TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), - 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); + FSL_BOOKE_MAS3(ram_tlb_address, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))); ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); ram_tlb_index++; diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index b769ef8..b489d2f 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -268,7 +268,10 @@ _start_e500: */ lis r3,CFG_INIT_RAM_ADDR@h ori r3,r3,CFG_INIT_RAM_ADDR@l - li r2,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE)) + mfspr r2, L1CFG0 + andi. r2, r2, 0x1ff + /* cache size * 1024 / (2 * L1 line size) */ + slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) mtctr r2 li r0,0 1: @@ -1061,7 +1064,9 @@ unlock_ram_in_cache: /* invalidate the INIT_RAM section */ lis r3,(CFG_INIT_RAM_ADDR & ~31)@h ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l - li r4,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE)) + mfspr r4,L1CFG0 + andi. r4,r4,0x1ff + slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 1: icbi r0,r3 dcbi r0,r3 |