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| author | Liu Ying <Ying.Liu@freescale.com> | 2012-09-11 16:09:21 +0800 |
|---|---|---|
| committer | Liu Ying <Ying.Liu@freescale.com> | 2012-09-27 11:10:31 +0800 |
| commit | b8c2285070dc6581d08488c738b46528e8f064df (patch) | |
| tree | 3e013fc0d7acd9f5acbce45ea11cf428d10c8c6d /cpu | |
| parent | 82d607a727228da0cb333adc7d072e9eb23c26db (diff) | |
| download | u-boot-imx-b8c2285070dc6581d08488c738b46528e8f064df.zip u-boot-imx-b8c2285070dc6581d08488c738b46528e8f064df.tar.gz u-boot-imx-b8c2285070dc6581d08488c738b46528e8f064df.tar.bz2 | |
ENGR00223797-1 MX6 SabreSD:Align IPU related clocks with kernel
This patch aligns IPU related clocks with imx_3.0.35(_android)
kernel setting to support smooth transition from uboot splash
screen to kernel stage.
The IPU related clock trees are:
1) MX6DQ SabreSD:
ipu1_clk --
osc_clk(24M)->pll2_528_bus_main_clk(528M)->periph_clk(528M)
->mmdc_ch0_axi_clk(528M)->ipu1_clk(264M)
ipu1_pixel_clk_x --
osc_clk(24M)->pll2_528_bus_main_clk(528M)->
pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)->
ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M)
2) MX6DL SabreSD:
ipu1_clk --
osc_clk(24M)->pll3_usb_otg_main_clk(480M)->
pll3_pfd_540M(540M)->ipu1_clk(270M)
ipu1_pixel_clk_x --
osc_clk(24M)->pll2_528_bus_main_clk(528M)->
pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)->
ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M)
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'cpu')
0 files changed, 0 insertions, 0 deletions