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authorHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2008-12-17 16:53:07 +0100
committerHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2008-12-17 16:53:07 +0100
commitcb5473205206c7f14cbb1e747f28ec75b48826e2 (patch)
tree8f4808d60917100b18a10b05230f7638a0a9bbcc /cpu
parentbaf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 (diff)
parent92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb (diff)
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Merge branch 'fixes' into cleanups
Conflicts: board/atmel/atngw100/atngw100.c board/atmel/atstk1000/atstk1000.c cpu/at32ap/at32ap700x/gpio.c include/asm-avr32/arch-at32ap700x/clk.h include/configs/atngw100.h include/configs/atstk1002.h include/configs/atstk1003.h include/configs/atstk1004.h include/configs/atstk1006.h include/configs/favr-32-ezkit.h include/configs/hammerhead.h include/configs/mimc200.h
Diffstat (limited to 'cpu')
-rw-r--r--cpu/74xx_7xx/cache.S14
-rw-r--r--cpu/74xx_7xx/cpu.c20
-rw-r--r--cpu/74xx_7xx/interrupts.c2
-rw-r--r--cpu/74xx_7xx/kgdb.S10
-rw-r--r--cpu/74xx_7xx/speed.c4
-rw-r--r--cpu/74xx_7xx/start.S183
-rw-r--r--cpu/arm1136/cpu.c2
-rw-r--r--cpu/arm1136/mx31/interrupts.c133
-rw-r--r--cpu/arm1136/mx31/serial.c12
-rw-r--r--cpu/arm1136/omap24xx/interrupts.c18
-rw-r--r--cpu/arm1136/start.S16
-rw-r--r--cpu/arm1176/s3c64xx/interrupts.c7
-rw-r--r--cpu/arm1176/start.S26
-rw-r--r--cpu/arm720t/config.mk1
-rw-r--r--cpu/arm720t/cpu.c2
-rw-r--r--cpu/arm720t/interrupts.c18
-rw-r--r--cpu/arm720t/lpc2292/flash.c4
-rw-r--r--cpu/arm720t/serial.c2
-rw-r--r--cpu/arm720t/serial_netarm.c2
-rw-r--r--cpu/arm720t/start.S12
-rw-r--r--cpu/arm920t/at91rm9200/i2c.c16
-rw-r--r--cpu/arm920t/at91rm9200/interrupts.c8
-rw-r--r--cpu/arm920t/at91rm9200/lowlevel_init.S2
-rw-r--r--cpu/arm920t/at91rm9200/spi.c4
-rw-r--r--cpu/arm920t/at91rm9200/usb.c4
-rw-r--r--cpu/arm920t/config.mk1
-rw-r--r--cpu/arm920t/cpu.c2
-rw-r--r--cpu/arm920t/imx/interrupts.c4
-rw-r--r--cpu/arm920t/imx/serial.c56
-rw-r--r--cpu/arm920t/interrupts.c2
-rw-r--r--cpu/arm920t/s3c24x0/i2c.c8
-rw-r--r--cpu/arm920t/s3c24x0/interrupts.c2
-rw-r--r--cpu/arm920t/s3c24x0/usb.c4
-rw-r--r--cpu/arm920t/s3c24x0/usb_ohci.c8
-rw-r--r--cpu/arm920t/start.S23
-rw-r--r--cpu/arm925t/config.mk1
-rw-r--r--cpu/arm925t/cpu.c2
-rw-r--r--cpu/arm925t/interrupts.c18
-rw-r--r--cpu/arm925t/start.S12
-rw-r--r--cpu/arm926ejs/Makefile2
-rw-r--r--cpu/arm926ejs/at91/Makefile1
-rw-r--r--cpu/arm926ejs/at91/config.mk1
-rw-r--r--cpu/arm926ejs/at91/ether.c35
-rw-r--r--cpu/arm926ejs/at91/spi.c8
-rw-r--r--cpu/arm926ejs/at91/timer.c2
-rw-r--r--cpu/arm926ejs/at91/u-boot.lds2
-rw-r--r--cpu/arm926ejs/at91/usb.c22
-rw-r--r--cpu/arm926ejs/config.mk3
-rw-r--r--cpu/arm926ejs/cpu.c2
-rw-r--r--cpu/arm926ejs/davinci/dp83848.c27
-rw-r--r--cpu/arm926ejs/davinci/i2c.c19
-rw-r--r--cpu/arm926ejs/davinci/nand.c105
-rw-r--r--cpu/arm926ejs/davinci/timer.c8
-rw-r--r--cpu/arm926ejs/omap/Makefile2
-rw-r--r--cpu/arm926ejs/omap/cpuinfo.c (renamed from cpu/arm926ejs/cpuinfo.c)0
-rw-r--r--cpu/arm926ejs/omap/timer.c18
-rw-r--r--cpu/arm926ejs/start.S12
-rwxr-xr-xcpu/arm926ejs/versatile/timer.c20
-rw-r--r--cpu/arm946es/config.mk8
-rw-r--r--cpu/arm946es/cpu.c2
-rw-r--r--cpu/arm946es/interrupts.c6
-rw-r--r--cpu/arm946es/start.S12
-rw-r--r--cpu/arm_intcm/config.mk8
-rw-r--r--cpu/arm_intcm/cpu.c2
-rw-r--r--cpu/arm_intcm/start.S12
-rw-r--r--cpu/at32ap/at32ap700x/clk.c24
-rw-r--r--cpu/at32ap/cache.c8
-rw-r--r--cpu/at32ap/cpu.c10
-rw-r--r--cpu/at32ap/hsdramc.c4
-rw-r--r--cpu/at32ap/interrupts.c4
-rw-r--r--cpu/at32ap/start.S2
-rw-r--r--cpu/blackfin/Makefile2
-rw-r--r--cpu/blackfin/cpu.c40
-rw-r--r--cpu/blackfin/flush.S230
-rw-r--r--cpu/blackfin/i2c.c16
-rw-r--r--cpu/blackfin/interrupts.c2
-rw-r--r--cpu/blackfin/serial.c72
-rw-r--r--cpu/blackfin/serial.h8
-rw-r--r--cpu/blackfin/start.S35
-rw-r--r--cpu/blackfin/traps.c58
-rw-r--r--cpu/i386/interrupts.c2
-rw-r--r--cpu/i386/sc520.c14
-rw-r--r--cpu/i386/sc520_asm.S12
-rw-r--r--cpu/i386/start.S24
-rw-r--r--cpu/i386/timer.c4
-rw-r--r--cpu/ixp/cpu.c15
-rw-r--r--cpu/ixp/interrupts.c4
-rw-r--r--cpu/ixp/npe/include/IxEthDB_p.h2
-rw-r--r--cpu/ixp/npe/include/npe.h6
-rw-r--r--cpu/ixp/npe/miiphy.c2
-rw-r--r--cpu/ixp/npe/npe.c12
-rw-r--r--cpu/ixp/serial.c12
-rw-r--r--cpu/ixp/start.S22
-rw-r--r--cpu/ixp/timer.c2
-rw-r--r--cpu/leon2/cpu.c3
-rw-r--r--cpu/leon2/interrupts.c8
-rw-r--r--cpu/leon2/prom.c50
-rw-r--r--cpu/leon2/serial.c2
-rw-r--r--cpu/leon2/start.S39
-rw-r--r--cpu/leon3/cpu.c2
-rw-r--r--cpu/leon3/cpu_init.c20
-rw-r--r--cpu/leon3/interrupts.c8
-rw-r--r--cpu/leon3/prom.c52
-rw-r--r--cpu/leon3/serial.c2
-rw-r--r--cpu/leon3/start.S37
-rw-r--r--cpu/leon3/usb_uhci.c2
-rw-r--r--cpu/lh7a40x/config.mk1
-rw-r--r--cpu/lh7a40x/cpu.c2
-rw-r--r--cpu/lh7a40x/interrupts.c10
-rw-r--r--cpu/lh7a40x/start.S12
-rw-r--r--cpu/mcf5227x/Makefile2
-rw-r--r--cpu/mcf5227x/cpu.c16
-rw-r--r--cpu/mcf5227x/cpu_init.c66
-rw-r--r--cpu/mcf5227x/dspi.c261
-rw-r--r--cpu/mcf5227x/interrupts.c8
-rw-r--r--cpu/mcf5227x/speed.c32
-rw-r--r--cpu/mcf5227x/start.S276
-rw-r--r--cpu/mcf523x/cpu.c13
-rw-r--r--cpu/mcf523x/cpu_init.c96
-rw-r--r--cpu/mcf523x/interrupts.c8
-rw-r--r--cpu/mcf523x/speed.c2
-rw-r--r--cpu/mcf523x/start.S43
-rw-r--r--cpu/mcf52x2/cpu.c18
-rw-r--r--cpu/mcf52x2/cpu_init.c493
-rw-r--r--cpu/mcf52x2/interrupts.c14
-rw-r--r--cpu/mcf52x2/speed.c12
-rw-r--r--cpu/mcf52x2/start.S79
-rw-r--r--cpu/mcf532x/cpu.c34
-rw-r--r--cpu/mcf532x/cpu_init.c265
-rw-r--r--cpu/mcf532x/interrupts.c8
-rw-r--r--cpu/mcf532x/speed.c123
-rw-r--r--cpu/mcf532x/start.S52
-rw-r--r--cpu/mcf5445x/cpu.c27
-rw-r--r--cpu/mcf5445x/cpu_init.c90
-rw-r--r--cpu/mcf5445x/dspi.c32
-rw-r--r--cpu/mcf5445x/interrupts.c8
-rw-r--r--cpu/mcf5445x/pci.c62
-rw-r--r--cpu/mcf5445x/speed.c14
-rw-r--r--cpu/mcf5445x/start.S83
-rw-r--r--cpu/mcf547x_8x/cpu.c14
-rw-r--r--cpu/mcf547x_8x/cpu_init.c79
-rw-r--r--cpu/mcf547x_8x/interrupts.c8
-rw-r--r--cpu/mcf547x_8x/pci.c38
-rw-r--r--cpu/mcf547x_8x/slicetimer.c18
-rw-r--r--cpu/mcf547x_8x/speed.c2
-rw-r--r--cpu/mcf547x_8x/start.S37
-rw-r--r--cpu/microblaze/exception.c2
-rw-r--r--cpu/microblaze/interrupts.c22
-rw-r--r--cpu/microblaze/start.S14
-rw-r--r--cpu/microblaze/timer.c12
-rw-r--r--cpu/mips/au1x00_eth.c4
-rw-r--r--cpu/mips/au1x00_serial.c2
-rw-r--r--cpu/mips/au1x00_usb_ohci.c9
-rw-r--r--cpu/mips/cache.S16
-rw-r--r--cpu/mips/cpu.c11
-rw-r--r--cpu/mips/incaip_clock.c4
-rw-r--r--cpu/mips/start.S44
-rw-r--r--cpu/mpc512x/cpu.c26
-rw-r--r--cpu/mpc512x/cpu_init.c10
-rw-r--r--cpu/mpc512x/i2c.c21
-rw-r--r--cpu/mpc512x/interrupts.c2
-rw-r--r--cpu/mpc512x/iopin.c2
-rw-r--r--cpu/mpc512x/serial.c18
-rw-r--r--cpu/mpc512x/speed.c16
-rw-r--r--cpu/mpc512x/start.S59
-rw-r--r--cpu/mpc5xx/cpu.c18
-rw-r--r--cpu/mpc5xx/cpu_init.c48
-rw-r--r--cpu/mpc5xx/interrupts.c12
-rw-r--r--cpu/mpc5xx/serial.c12
-rw-r--r--cpu/mpc5xx/speed.c4
-rw-r--r--cpu/mpc5xx/spi.c16
-rw-r--r--cpu/mpc5xx/start.S45
-rw-r--r--cpu/mpc5xx/u-boot.lds3
-rw-r--r--cpu/mpc5xxx/cpu.c15
-rw-r--r--cpu/mpc5xxx/cpu_init.c120
-rw-r--r--cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S8
-rw-r--r--cpu/mpc5xxx/i2c.c22
-rw-r--r--cpu/mpc5xxx/interrupts.c2
-rw-r--r--cpu/mpc5xxx/pci_mpc5200.c10
-rw-r--r--cpu/mpc5xxx/serial.c4
-rw-r--r--cpu/mpc5xxx/speed.c17
-rw-r--r--cpu/mpc5xxx/start.S65
-rw-r--r--cpu/mpc5xxx/u-boot-customlayout.lds3
-rw-r--r--cpu/mpc5xxx/u-boot.lds1
-rw-r--r--cpu/mpc5xxx/usb.c4
-rw-r--r--cpu/mpc5xxx/usb_ohci.c8
-rw-r--r--cpu/mpc8220/cpu.c15
-rw-r--r--cpu/mpc8220/cpu_init.c64
-rw-r--r--cpu/mpc8220/dramSetup.c14
-rw-r--r--cpu/mpc8220/i2c.c16
-rw-r--r--cpu/mpc8220/i2cCore.c2
-rw-r--r--cpu/mpc8220/interrupts.c2
-rw-r--r--cpu/mpc8220/pci.c4
-rw-r--r--cpu/mpc8220/speed.c26
-rw-r--r--cpu/mpc8220/start.S37
-rw-r--r--cpu/mpc8220/u-boot.lds1
-rw-r--r--cpu/mpc824x/cpu.c12
-rw-r--r--cpu/mpc824x/cpu_init.c234
-rw-r--r--cpu/mpc824x/drivers/epic/epic1.c4
-rw-r--r--cpu/mpc824x/drivers/i2c/i2c.c18
-rw-r--r--cpu/mpc824x/interrupts.c4
-rw-r--r--cpu/mpc824x/start.S93
-rw-r--r--cpu/mpc824x/u-boot.lds1
-rw-r--r--cpu/mpc8260/commproc.c18
-rw-r--r--cpu/mpc8260/cpu.c33
-rw-r--r--cpu/mpc8260/cpu_init.c106
-rw-r--r--cpu/mpc8260/ether_fcc.c24
-rw-r--r--cpu/mpc8260/ether_scc.c16
-rw-r--r--cpu/mpc8260/i2c.c79
-rw-r--r--cpu/mpc8260/interrupts.c12
-rw-r--r--cpu/mpc8260/kgdb.S8
-rw-r--r--cpu/mpc8260/pci.c100
-rw-r--r--cpu/mpc8260/serial_scc.c14
-rw-r--r--cpu/mpc8260/serial_smc.c14
-rw-r--r--cpu/mpc8260/speed.c4
-rw-r--r--cpu/mpc8260/spi.c20
-rw-r--r--cpu/mpc8260/start.S121
-rw-r--r--cpu/mpc8260/traps.c4
-rw-r--r--cpu/mpc8260/u-boot.lds1
-rw-r--r--cpu/mpc83xx/cpu.c66
-rw-r--r--cpu/mpc83xx/cpu_init.c338
-rw-r--r--cpu/mpc83xx/ecc.c4
-rw-r--r--cpu/mpc83xx/fdt.c9
-rw-r--r--cpu/mpc83xx/interrupts.c4
-rw-r--r--cpu/mpc83xx/nand_init.c40
-rw-r--r--cpu/mpc83xx/pci.c10
-rw-r--r--cpu/mpc83xx/qe_io.c2
-rw-r--r--cpu/mpc83xx/serdes.c4
-rw-r--r--cpu/mpc83xx/spd_sdram.c32
-rw-r--r--cpu/mpc83xx/speed.c44
-rw-r--r--cpu/mpc83xx/start.S318
-rw-r--r--cpu/mpc83xx/traps.c4
-rw-r--r--cpu/mpc83xx/u-boot.lds1
-rw-r--r--cpu/mpc85xx/commproc.c16
-rw-r--r--cpu/mpc85xx/cpu.c117
-rw-r--r--cpu/mpc85xx/cpu_init.c114
-rw-r--r--cpu/mpc85xx/ddr-gen1.c4
-rw-r--r--cpu/mpc85xx/ddr-gen2.c2
-rw-r--r--cpu/mpc85xx/ddr-gen3.c13
-rw-r--r--cpu/mpc85xx/ether_fcc.c26
-rw-r--r--cpu/mpc85xx/fdt.c20
-rw-r--r--cpu/mpc85xx/interrupts.c18
-rw-r--r--cpu/mpc85xx/mp.c10
-rw-r--r--cpu/mpc85xx/mpc8536_serdes.c4
-rw-r--r--cpu/mpc85xx/pci.c64
-rw-r--r--cpu/mpc85xx/qe_io.c2
-rw-r--r--cpu/mpc85xx/release.S13
-rw-r--r--cpu/mpc85xx/serial_scc.c8
-rw-r--r--cpu/mpc85xx/speed.c9
-rw-r--r--cpu/mpc85xx/start.S102
-rw-r--r--cpu/mpc85xx/tlb.c2
-rw-r--r--cpu/mpc85xx/traps.c2
-rw-r--r--cpu/mpc86xx/Makefile4
-rw-r--r--cpu/mpc86xx/cache.S14
-rw-r--r--cpu/mpc86xx/cpu.c56
-rw-r--r--cpu/mpc86xx/cpu_init.c100
-rw-r--r--cpu/mpc86xx/ddr-8641.c4
-rw-r--r--cpu/mpc86xx/fdt.c25
-rw-r--r--cpu/mpc86xx/interrupts.c133
-rw-r--r--cpu/mpc86xx/mp.c68
-rw-r--r--cpu/mpc86xx/mp.h7
-rw-r--r--cpu/mpc86xx/release.S169
-rw-r--r--cpu/mpc86xx/speed.c2
-rw-r--r--cpu/mpc86xx/start.S283
-rw-r--r--cpu/mpc8xx/commproc.c12
-rw-r--r--cpu/mpc8xx/cpu.c49
-rw-r--r--cpu/mpc8xx/cpu_init.c128
-rw-r--r--cpu/mpc8xx/fec.c42
-rw-r--r--cpu/mpc8xx/i2c.c65
-rw-r--r--cpu/mpc8xx/interrupts.c16
-rw-r--r--cpu/mpc8xx/kgdb.S8
-rw-r--r--cpu/mpc8xx/lcd.c50
-rw-r--r--cpu/mpc8xx/scc.c18
-rw-r--r--cpu/mpc8xx/serial.c52
-rw-r--r--cpu/mpc8xx/speed.c28
-rw-r--r--cpu/mpc8xx/spi.c40
-rw-r--r--cpu/mpc8xx/start.S25
-rw-r--r--cpu/mpc8xx/upatch.c22
-rw-r--r--cpu/mpc8xx/video.c14
-rw-r--r--cpu/mpc8xxx/ddr/ctrl_regs.c80
-rw-r--r--cpu/mpc8xxx/ddr/ddr.h17
-rw-r--r--cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h84
-rw-r--r--cpu/mpc8xxx/ddr/main.c84
-rw-r--r--cpu/mpc8xxx/ddr/options.c84
-rw-r--r--cpu/nios/asmi.c6
-rw-r--r--cpu/nios/interrupts.c20
-rw-r--r--cpu/nios/serial.c8
-rw-r--r--cpu/nios/spi.c24
-rw-r--r--cpu/nios/start.S19
-rw-r--r--cpu/nios2/cpu.c8
-rw-r--r--cpu/nios2/epcs.c4
-rw-r--r--cpu/nios2/interrupts.c22
-rw-r--r--cpu/nios2/serial.c8
-rw-r--r--cpu/nios2/start.S27
-rw-r--r--cpu/nios2/sysid.c6
-rw-r--r--cpu/ppc4xx/40x_spd_sdram.c10
-rw-r--r--cpu/ppc4xx/44x_spd_ddr.c22
-rw-r--r--cpu/ppc4xx/44x_spd_ddr2.c317
-rw-r--r--cpu/ppc4xx/4xx_enet.c1983
-rw-r--r--cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c1233
-rw-r--r--cpu/ppc4xx/4xx_pci.c46
-rw-r--r--cpu/ppc4xx/4xx_pcie.c144
-rw-r--r--cpu/ppc4xx/4xx_uart.c44
-rw-r--r--cpu/ppc4xx/Makefile4
-rw-r--r--cpu/ppc4xx/cache.S4
-rw-r--r--cpu/ppc4xx/commproc.c12
-rw-r--r--cpu/ppc4xx/cpu.c38
-rw-r--r--cpu/ppc4xx/cpu_init.c100
-rw-r--r--cpu/ppc4xx/denali_data_eye.c2
-rw-r--r--cpu/ppc4xx/denali_spd_ddr2.c22
-rw-r--r--cpu/ppc4xx/ecc.c4
-rw-r--r--cpu/ppc4xx/ecc.h6
-rw-r--r--cpu/ppc4xx/fdt.c45
-rw-r--r--cpu/ppc4xx/gpio.c8
-rw-r--r--cpu/ppc4xx/i2c.c47
-rw-r--r--cpu/ppc4xx/miiphy.c39
-rw-r--r--cpu/ppc4xx/ndfc.c10
-rw-r--r--cpu/ppc4xx/sdram.c60
-rw-r--r--cpu/ppc4xx/sdram.h20
-rw-r--r--cpu/ppc4xx/speed.c2
-rw-r--r--cpu/ppc4xx/start.S418
-rw-r--r--cpu/ppc4xx/usb.c4
-rw-r--r--cpu/ppc4xx/usb_ohci.c14
-rw-r--r--cpu/ppc4xx/usbdev.h44
-rw-r--r--cpu/pxa/config.mk1
-rw-r--r--cpu/pxa/cpu.c2
-rw-r--r--cpu/pxa/i2c.c23
-rw-r--r--cpu/pxa/interrupts.c6
-rw-r--r--cpu/pxa/mmc.c14
-rw-r--r--cpu/pxa/pxafb.c30
-rw-r--r--cpu/pxa/start.S40
-rw-r--r--cpu/pxa/usb.c4
-rw-r--r--cpu/s3c44b0/config.mk1
-rw-r--r--cpu/s3c44b0/cpu.c6
-rw-r--r--cpu/s3c44b0/interrupts.c6
-rw-r--r--cpu/s3c44b0/start.S4
-rw-r--r--cpu/sa1100/config.mk1
-rw-r--r--cpu/sa1100/cpu.c2
-rw-r--r--cpu/sa1100/interrupts.c6
-rw-r--r--cpu/sa1100/start.S14
-rw-r--r--cpu/sh2/Makefile2
-rw-r--r--cpu/sh2/start.S4
-rw-r--r--cpu/sh2/time.c111
-rw-r--r--cpu/sh3/Makefile2
-rw-r--r--cpu/sh3/start.S4
-rw-r--r--cpu/sh3/time.c103
-rw-r--r--cpu/sh4/Makefile2
-rw-r--r--cpu/sh4/start.S4
-rw-r--r--cpu/sh4/time.c98
-rw-r--r--cpu/sh4/watchdog.c53
350 files changed, 7620 insertions, 7169 deletions
diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S
index eac4544..66c7298 100644
--- a/cpu/74xx_7xx/cache.S
+++ b/cpu/74xx_7xx/cache.S
@@ -52,7 +52,7 @@ _GLOBAL(invalidate_l1_data_cache)
/*
* Flush data cache.
*/
-_GLOBAL(flush_data_cache)
+_GLOBAL(flush_dcache)
lis r3,0
lis r5,CACHE_LINE_SIZE
flush:
@@ -292,7 +292,7 @@ _GLOBAL(dcache_enable)
mtspr HID0, r5 /* enable + invalidate */
mtspr HID0, r3 /* enable */
sync
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
mflr r5
bl l2cache_enable /* uses r3 and r4 */
sync
@@ -303,12 +303,12 @@ _GLOBAL(dcache_enable)
/*
* Disable data cache(s) - L1 and optionally L2
- * Calls flush_data_cache and l2cache_disable_no_flush.
+ * Calls flush_dcache and l2cache_disable_no_flush.
* LR saved in r4
*/
_GLOBAL(dcache_disable)
mflr r4 /* save link register */
- bl flush_data_cache /* uses r3 and r5 */
+ bl flush_dcache /* uses r3 and r5 */
sync
mfspr r3, HID0
li r5, HID0_DCFI|HID0_DLOCK
@@ -318,7 +318,7 @@ _GLOBAL(dcache_disable)
andc r3, r3, r5 /* no enable, no invalidate */
mtspr HID0, r3
sync
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
bl l2cache_disable_no_flush /* uses r3 */
#endif
mtlr r4 /* restore link register */
@@ -389,11 +389,11 @@ _GLOBAL(l2cache_enable)
/*
* Disable L2 cache
- * Calls flush_data_cache. LR is saved in r4
+ * Calls flush_dcache. LR is saved in r4
*/
_GLOBAL(l2cache_disable)
mflr r4 /* save link register */
- bl flush_data_cache /* uses r3 and r5 */
+ bl flush_dcache /* uses r3 and r5 */
sync
mtlr r4 /* restore link register */
l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c
index c007abc..3c17277 100644
--- a/cpu/74xx_7xx/cpu.c
+++ b/cpu/74xx_7xx/cpu.c
@@ -256,16 +256,16 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
__asm__ __volatile__ ("isync");
__asm__ __volatile__ ("sync");
-#ifdef CFG_RESET_ADDRESS
- addr = CFG_RESET_ADDRESS;
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
- * note: when CFG_MONITOR_BASE points to a RAM address,
- * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
+ * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
+ * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
* address. Better pick an address known to be invalid on your
- * system and assign it to CFG_RESET_ADDRESS.
+ * system and assign it to CONFIG_SYS_RESET_ADDRESS.
*/
- addr = CFG_MONITOR_BASE - sizeof (ulong);
+ addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
soft_restart(addr);
while(1); /* not reached */
@@ -277,18 +277,18 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/*
* For the 7400 the TB clock runs at 1/4 the cpu bus speed.
*/
-#if defined(CONFIG_AMIGAONEG3SE) || defined(CFG_CONFIG_BUS_CLK)
+#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SYS_CONFIG_BUS_CLK)
unsigned long get_tbclk(void)
{
return (gd->bus_clk / 4);
}
-#else /* ! CONFIG_AMIGAONEG3SE and !CFG_CONFIG_BUS_CLK*/
+#else /* ! CONFIG_AMIGAONEG3SE and !CONFIG_SYS_CONFIG_BUS_CLK*/
unsigned long get_tbclk (void)
{
- return CFG_BUS_HZ / 4;
+ return CONFIG_SYS_BUS_HZ / 4;
}
-#endif /* CONFIG_AMIGAONEG3SE or CFG_CONFIG_BUS_CLK*/
+#endif /* CONFIG_AMIGAONEG3SE or CONFIG_SYS_CONFIG_BUS_CLK*/
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_WATCHDOG)
#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
diff --git a/cpu/74xx_7xx/interrupts.c b/cpu/74xx_7xx/interrupts.c
index f0ea485..0ea1aec 100644
--- a/cpu/74xx_7xx/interrupts.c
+++ b/cpu/74xx_7xx/interrupts.c
@@ -48,7 +48,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
GTREGREAD(ETHERNET2_INTERRUPT_MASK_REGISTER));
puts("interrupt_init: setting decrementer_count\n");
#endif
- *decrementer_count = get_tbclk() / CFG_HZ;
+ *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
return (0);
}
diff --git a/cpu/74xx_7xx/kgdb.S b/cpu/74xx_7xx/kgdb.S
index 4f23122..ad487cd 100644
--- a/cpu/74xx_7xx/kgdb.S
+++ b/cpu/74xx_7xx/kgdb.S
@@ -43,7 +43,7 @@ kgdb_flush_cache_all:
addis r4,r0,0x0040
kgdb_flush_loop:
lwz r5,0(r3)
- addi r3,r3,CFG_CACHELINE_SIZE
+ addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
cmp 0,0,r3,r4
bne kgdb_flush_loop
SYNC
@@ -55,21 +55,21 @@ kgdb_flush_loop:
.globl kgdb_flush_cache_range
kgdb_flush_cache_range:
- li r5,CFG_CACHELINE_SIZE-1
+ li r5,CONFIG_SYS_CACHELINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
- srwi. r4,r4,CFG_CACHELINE_SHIFT
+ srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
beqlr
mtctr r4
mr r6,r3
1: dcbst 0,r3
- addi r3,r3,CFG_CACHELINE_SIZE
+ addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
sync /* wait for dcbst's to get to ram */
mtctr r4
2: icbi 0,r6
- addi r6,r6,CFG_CACHELINE_SIZE
+ addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
bdnz 2b
SYNC
blr
diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c
index d8c40ce..bc33a67 100644
--- a/cpu/74xx_7xx/speed.c
+++ b/cpu/74xx_7xx/speed.c
@@ -127,8 +127,8 @@ int get_clocks (void)
{
ulong clock = 0;
-#ifdef CFG_BUS_CLK
- gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */
+#ifdef CONFIG_SYS_BUS_CLK
+ gd->bus_clk = CONFIG_SYS_BUS_CLK; /* bus clock is a fixed frequency */
#else
gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */
#endif
diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S
index 42b0f72..792cd30 100644
--- a/cpu/74xx_7xx/start.S
+++ b/cpu/74xx_7xx/start.S
@@ -34,6 +34,7 @@
*/
#include <config.h>
#include <74xx_7xx.h>
+#include <timestamp.h>
#include <version.h>
#include <ppc_asm.tmpl>
@@ -87,7 +88,7 @@
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
. = EXC_OFF_SYS_RESET
@@ -209,7 +210,7 @@ boot_warm:
bl invalidate_bats
sync
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
/* init the L2 cache */
addis r3, r0, L2_INIT@h
ori r3, r3, L2_INIT@l
@@ -225,12 +226,12 @@ boot_warm:
*/
#endif
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
/* invalidate the L2 cache */
bl l2cache_invalidate
sync
#endif
-#ifdef CFG_BOARD_ASM_INIT
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
/* do early init */
bl board_asm_init
#endif
@@ -238,8 +239,8 @@ boot_warm:
/*
* Calculate absolute address in FLASH and jump there
*------------------------------------------------------*/
- lis r3, CFG_MONITOR_BASE@h
- ori r3, r3, CFG_MONITOR_BASE@l
+ lis r3, CONFIG_SYS_MONITOR_BASE@h
+ ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
@@ -280,15 +281,15 @@ in_flash:
bl l1dcache_enable
sync
#endif
-#ifdef CFG_INIT_RAM_LOCK
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
bl lock_ram_in_cache
sync
#endif
/* set up the stack pointer in our newly created
* cache-ram (r1) */
- lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
- ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+ lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
+ ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
@@ -343,146 +344,146 @@ setup_bats:
addis r0, r0, 0x0000
/* IBAT 0 */
- addis r4, r0, CFG_IBAT0L@h
- ori r4, r4, CFG_IBAT0L@l
- addis r3, r0, CFG_IBAT0U@h
- ori r3, r3, CFG_IBAT0U@l
+ addis r4, r0, CONFIG_SYS_IBAT0L@h
+ ori r4, r4, CONFIG_SYS_IBAT0L@l
+ addis r3, r0, CONFIG_SYS_IBAT0U@h
+ ori r3, r3, CONFIG_SYS_IBAT0U@l
mtspr IBAT0L, r4
mtspr IBAT0U, r3
isync
/* DBAT 0 */
- addis r4, r0, CFG_DBAT0L@h
- ori r4, r4, CFG_DBAT0L@l
- addis r3, r0, CFG_DBAT0U@h
- ori r3, r3, CFG_DBAT0U@l
+ addis r4, r0, CONFIG_SYS_DBAT0L@h
+ ori r4, r4, CONFIG_SYS_DBAT0L@l
+ addis r3, r0, CONFIG_SYS_DBAT0U@h
+ ori r3, r3, CONFIG_SYS_DBAT0U@l
mtspr DBAT0L, r4
mtspr DBAT0U, r3
isync
/* IBAT 1 */
- addis r4, r0, CFG_IBAT1L@h
- ori r4, r4, CFG_IBAT1L@l
- addis r3, r0, CFG_IBAT1U@h
- ori r3, r3, CFG_IBAT1U@l
+ addis r4, r0, CONFIG_SYS_IBAT1L@h
+ ori r4, r4, CONFIG_SYS_IBAT1L@l
+ addis r3, r0, CONFIG_SYS_IBAT1U@h
+ ori r3, r3, CONFIG_SYS_IBAT1U@l
mtspr IBAT1L, r4
mtspr IBAT1U, r3
isync
/* DBAT 1 */
- addis r4, r0, CFG_DBAT1L@h
- ori r4, r4, CFG_DBAT1L@l
- addis r3, r0, CFG_DBAT1U@h
- ori r3, r3, CFG_DBAT1U@l
+ addis r4, r0, CONFIG_SYS_DBAT1L@h
+ ori r4, r4, CONFIG_SYS_DBAT1L@l
+ addis r3, r0, CONFIG_SYS_DBAT1U@h
+ ori r3, r3, CONFIG_SYS_DBAT1U@l
mtspr DBAT1L, r4
mtspr DBAT1U, r3
isync
/* IBAT 2 */
- addis r4, r0, CFG_IBAT2L@h
- ori r4, r4, CFG_IBAT2L@l
- addis r3, r0, CFG_IBAT2U@h
- ori r3, r3, CFG_IBAT2U@l
+ addis r4, r0, CONFIG_SYS_IBAT2L@h
+ ori r4, r4, CONFIG_SYS_IBAT2L@l
+ addis r3, r0, CONFIG_SYS_IBAT2U@h
+ ori r3, r3, CONFIG_SYS_IBAT2U@l
mtspr IBAT2L, r4
mtspr IBAT2U, r3
isync
/* DBAT 2 */
- addis r4, r0, CFG_DBAT2L@h
- ori r4, r4, CFG_DBAT2L@l
- addis r3, r0, CFG_DBAT2U@h
- ori r3, r3, CFG_DBAT2U@l
+ addis r4, r0, CONFIG_SYS_DBAT2L@h
+ ori r4, r4, CONFIG_SYS_DBAT2L@l
+ addis r3, r0, CONFIG_SYS_DBAT2U@h
+ ori r3, r3, CONFIG_SYS_DBAT2U@l
mtspr DBAT2L, r4
mtspr DBAT2U, r3
isync
/* IBAT 3 */
- addis r4, r0, CFG_IBAT3L@h
- ori r4, r4, CFG_IBAT3L@l
- addis r3, r0, CFG_IBAT3U@h
- ori r3, r3, CFG_IBAT3U@l
+ addis r4, r0, CONFIG_SYS_IBAT3L@h
+ ori r4, r4, CONFIG_SYS_IBAT3L@l
+ addis r3, r0, CONFIG_SYS_IBAT3U@h
+ ori r3, r3, CONFIG_SYS_IBAT3U@l
mtspr IBAT3L, r4
mtspr IBAT3U, r3
isync
/* DBAT 3 */
- addis r4, r0, CFG_DBAT3L@h
- ori r4, r4, CFG_DBAT3L@l
- addis r3, r0, CFG_DBAT3U@h
- ori r3, r3, CFG_DBAT3U@l
+ addis r4, r0, CONFIG_SYS_DBAT3L@h
+ ori r4, r4, CONFIG_SYS_DBAT3L@l
+ addis r3, r0, CONFIG_SYS_DBAT3U@h
+ ori r3, r3, CONFIG_SYS_DBAT3U@l
mtspr DBAT3L, r4
mtspr DBAT3U, r3
isync
#ifdef CONFIG_HIGH_BATS
/* IBAT 4 */
- addis r4, r0, CFG_IBAT4L@h
- ori r4, r4, CFG_IBAT4L@l
- addis r3, r0, CFG_IBAT4U@h
- ori r3, r3, CFG_IBAT4U@l
+ addis r4, r0, CONFIG_SYS_IBAT4L@h
+ ori r4, r4, CONFIG_SYS_IBAT4L@l
+ addis r3, r0, CONFIG_SYS_IBAT4U@h
+ ori r3, r3, CONFIG_SYS_IBAT4U@l
mtspr IBAT4L, r4
mtspr IBAT4U, r3
isync
/* DBAT 4 */
- addis r4, r0, CFG_DBAT4L@h
- ori r4, r4, CFG_DBAT4L@l
- addis r3, r0, CFG_DBAT4U@h
- ori r3, r3, CFG_DBAT4U@l
+ addis r4, r0, CONFIG_SYS_DBAT4L@h
+ ori r4, r4, CONFIG_SYS_DBAT4L@l
+ addis r3, r0, CONFIG_SYS_DBAT4U@h
+ ori r3, r3, CONFIG_SYS_DBAT4U@l
mtspr DBAT4L, r4
mtspr DBAT4U, r3
isync
/* IBAT 5 */
- addis r4, r0, CFG_IBAT5L@h
- ori r4, r4, CFG_IBAT5L@l
- addis r3, r0, CFG_IBAT5U@h
- ori r3, r3, CFG_IBAT5U@l
+ addis r4, r0, CONFIG_SYS_IBAT5L@h
+ ori r4, r4, CONFIG_SYS_IBAT5L@l
+ addis r3, r0, CONFIG_SYS_IBAT5U@h
+ ori r3, r3, CONFIG_SYS_IBAT5U@l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
isync
/* DBAT 5 */
- addis r4, r0, CFG_DBAT5L@h
- ori r4, r4, CFG_DBAT5L@l
- addis r3, r0, CFG_DBAT5U@h
- ori r3, r3, CFG_DBAT5U@l
+ addis r4, r0, CONFIG_SYS_DBAT5L@h
+ ori r4, r4, CONFIG_SYS_DBAT5L@l
+ addis r3, r0, CONFIG_SYS_DBAT5U@h
+ ori r3, r3, CONFIG_SYS_DBAT5U@l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
isync
/* IBAT 6 */
- addis r4, r0, CFG_IBAT6L@h
- ori r4, r4, CFG_IBAT6L@l
- addis r3, r0, CFG_IBAT6U@h
- ori r3, r3, CFG_IBAT6U@l
+ addis r4, r0, CONFIG_SYS_IBAT6L@h
+ ori r4, r4, CONFIG_SYS_IBAT6L@l
+ addis r3, r0, CONFIG_SYS_IBAT6U@h
+ ori r3, r3, CONFIG_SYS_IBAT6U@l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
isync
/* DBAT 6 */
- addis r4, r0, CFG_DBAT6L@h
- ori r4, r4, CFG_DBAT6L@l
- addis r3, r0, CFG_DBAT6U@h
- ori r3, r3, CFG_DBAT6U@l
+ addis r4, r0, CONFIG_SYS_DBAT6L@h
+ ori r4, r4, CONFIG_SYS_DBAT6L@l
+ addis r3, r0, CONFIG_SYS_DBAT6U@h
+ ori r3, r3, CONFIG_SYS_DBAT6U@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
isync
/* IBAT 7 */
- addis r4, r0, CFG_IBAT7L@h
- ori r4, r4, CFG_IBAT7L@l
- addis r3, r0, CFG_IBAT7U@h
- ori r3, r3, CFG_IBAT7U@l
+ addis r4, r0, CONFIG_SYS_IBAT7L@h
+ ori r4, r4, CONFIG_SYS_IBAT7L@l
+ addis r3, r0, CONFIG_SYS_IBAT7U@h
+ ori r3, r3, CONFIG_SYS_IBAT7U@l
mtspr IBAT7L, r4
mtspr IBAT7U, r3
isync
/* DBAT 7 */
- addis r4, r0, CFG_DBAT7L@h
- ori r4, r4, CFG_DBAT7L@l
- addis r3, r0, CFG_DBAT7U@h
- ori r3, r3, CFG_DBAT7U@l
+ addis r4, r0, CONFIG_SYS_DBAT7L@h
+ ori r4, r4, CONFIG_SYS_DBAT7L@l
+ addis r3, r0, CONFIG_SYS_DBAT7U@h
+ ori r3, r3, CONFIG_SYS_DBAT7U@l
mtspr DBAT7L, r4
mtspr DBAT7U, r3
isync
@@ -612,16 +613,16 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
@@ -639,11 +640,11 @@ relocate_code:
bl board_relocate_rom
sync
mr r3, r10 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
#else
cmplw cr1,r3,r4
addi r0,r5,3
@@ -851,15 +852,15 @@ trap_reloc:
blr
-#ifdef CFG_INIT_RAM_LOCK
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
lock_ram_in_cache:
/* Allocate Initial RAM in data cache.
*/
- lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
- li r2, ((CFG_INIT_RAM_END & ~31) + \
- (CFG_INIT_RAM_ADDR & 31) + 31) / 32
- mtctr r2
+ lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+ li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r4
1:
dcbz r0, r3
addi r3, r3, 32
@@ -876,11 +877,11 @@ lock_ram_in_cache:
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
- lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
- li r2, ((CFG_INIT_RAM_END & ~31) + \
- (CFG_INIT_RAM_ADDR & 31) + 31) / 32
- mtctr r2
+ lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+ li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r4
1: icbi r0, r3
addi r3, r3, 32
bdnz 1b
diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
index c27f8cd..0486163 100644
--- a/cpu/arm1136/cpu.c
+++ b/cpu/arm1136/cpu.c
@@ -89,7 +89,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;
diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c
index 21b77a5..ab7202f 100644
--- a/cpu/arm1136/mx31/interrupts.c
+++ b/cpu/arm1136/mx31/interrupts.c
@@ -23,45 +23,123 @@
#include <common.h>
#include <asm/arch/mx31-regs.h>
+#include <div64.h>
#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
/* General purpose timers registers */
-#define GPTCR __REG(TIMER_BASE) /* Control register */
-#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
-#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
-#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
+#define GPTCR __REG(TIMER_BASE) /* Control register */
+#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
+#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
+#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
/* General purpose timers bitfields */
-#define GPTCR_SWR (1<<15) /* Software reset */
-#define GPTCR_FRR (1<<9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
-#define GPTCR_TEN (1) /* Timer enable */
+#define GPTCR_SWR (1 << 15) /* Software reset */
+#define GPTCR_FRR (1 << 9) /* Freerun / restart */
+#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
+#define GPTCR_TEN 1 /* Timer enable */
+
+static ulong timestamp;
+static ulong lastinc;
+
+/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
+#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, CONFIG_MX31_CLK32);
+ return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+ time *= CONFIG_MX31_CLK32;
+ do_div(time, CONFIG_SYS_HZ);
+ return time;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+ us = us * CONFIG_MX31_CLK32 + 999999;
+ do_div(us, 1000000);
+ return us;
+}
+#else
+/* ~2% error */
+#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ do_div(tick, TICK_PER_TIME);
+ return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+ return time * TICK_PER_TIME;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+ us += US_PER_TICK - 1;
+ do_div(us, US_PER_TICK);
+ return us;
+}
+#endif
/* nothing really to do with interrupts, just starts up a counter. */
+/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int interrupt_init (void)
{
int i;
/* setup GP Timer 1 */
GPTCR = GPTCR_SWR;
- for ( i=0; i<100; i++) GPTCR = 0; /* We have no udelay by now */
+ for (i = 0; i < 100; i++)
+ GPTCR = 0; /* We have no udelay by now */
GPTPR = 0; /* 32Khz */
- GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */
+ /* Freerun Mode, PERCLK1 input */
+ GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
return 0;
}
void reset_timer_masked (void)
{
- GPTCR = 0;
- GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */
+ /* reset time */
+ lastinc = GPTCNT; /* capture current incrementer value time */
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+unsigned long long get_ticks (void)
+{
+ ulong now = GPTCNT; /* current tick value */
+
+ if (now >= lastinc) /* normal mode (non roll) */
+ /* move stamp forward with absolut diff ticks */
+ timestamp += (now - lastinc);
+ else /* we have rollover of incrementer */
+ timestamp += (0xFFFFFFFF - lastinc) + now;
+ lastinc = now;
+ return timestamp;
}
ulong get_timer_masked (void)
{
- ulong val = GPTCNT;
- return val;
+ /*
+ * get_ticks() returns a long long (64 bit), it wraps in
+ * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+ * 5 * 10^6 days - long enough.
+ */
+ return tick_to_time(get_ticks());
}
ulong get_timer (ulong base)
@@ -71,29 +149,20 @@ ulong get_timer (ulong base)
void set_timer (ulong t)
{
+ timestamp = time_to_tick(t);
}
/* delay x useconds AND perserve advance timstamp value */
void udelay (unsigned long usec)
{
- ulong tmo, tmp;
-
- if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- } else { /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
- tmo /= (1000*1000);
- }
-
- tmp = get_timer (0); /* get current timestamp */
- if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
- reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */
- else
- tmo += tmp; /* else, set advancing stamp wake up time */
- while (get_timer_masked () < tmo)/* loop till event */
- /*NOP*/;
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = us_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
}
void reset_cpu (ulong addr)
diff --git a/cpu/arm1136/mx31/serial.c b/cpu/arm1136/mx31/serial.c
index f498599..e025e94 100644
--- a/cpu/arm1136/mx31/serial.c
+++ b/cpu/arm1136/mx31/serial.c
@@ -25,18 +25,18 @@
#define __REG(x) (*((volatile u32 *)(x)))
-#ifdef CFG_MX31_UART1
+#ifdef CONFIG_SYS_MX31_UART1
#define UART_PHYS 0x43f90000
-#elif defined(CFG_MX31_UART2)
+#elif defined(CONFIG_SYS_MX31_UART2)
#define UART_PHYS 0x43f94000
-#elif defined(CFG_MX31_UART3)
+#elif defined(CONFIG_SYS_MX31_UART3)
#define UART_PHYS 0x5000c000
-#elif defined(CFG_MX31_UART4)
+#elif defined(CONFIG_SYS_MX31_UART4)
#define UART_PHYS 0x43fb0000
-#elif defined(CFG_MX31_UART5)
+#elif defined(CONFIG_SYS_MX31_UART5)
#define UART_PHYS 0x43fb4000
#else
-#error "define CFG_MX31_UARTx to use the mx31 UART driver"
+#error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver"
#endif
/* Register definitions */
diff --git a/cpu/arm1136/omap24xx/interrupts.c b/cpu/arm1136/omap24xx/interrupts.c
index b9a8b93..fb02a49 100644
--- a/cpu/arm1136/omap24xx/interrupts.c
+++ b/cpu/arm1136/omap24xx/interrupts.c
@@ -37,7 +37,7 @@
#define TIMER_LOAD_VAL 0
/* macro to read the 32 bit timer */
-#define READ_TIMER (*((volatile ulong *)(CFG_TIMERBASE+TCRR)))
+#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR)))
static ulong timestamp;
static ulong lastinc;
@@ -48,9 +48,9 @@ int interrupt_init (void)
int32_t val;
/* Start the counter ticking up */
- *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/
- val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/
- *((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */
+ *((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/
+ val = (CONFIG_SYS_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/
+ *((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */
reset_timer_masked(); /* init the timestamp and lastinc value */
@@ -81,10 +81,10 @@ void udelay (unsigned long usec)
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -125,10 +125,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
endtime = get_timer_masked () + tmo;
@@ -154,6 +154,6 @@ unsigned long long get_ticks(void)
ulong get_tbclk (void)
{
ulong tbclk;
- tbclk = CFG_HZ;
+ tbclk = CONFIG_SYS_HZ;
return tbclk;
}
diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S
index 51b664d..e622338 100644
--- a/cpu/arm1136/start.S
+++ b/cpu/arm1136/start.S
@@ -178,8 +178,8 @@ stack_setup:
#ifdef CONFIG_ONENAND_IPL
sub sp, r0, #128 /* leave 32 words for abort-stack */
#else
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -290,8 +290,8 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, _armboot_start
- sub r2, r2, #(CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@@ -323,8 +323,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
- sub r13, r13, #(CFG_MALLOC_LEN) @ move past malloc pool
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
+ sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
@@ -341,8 +341,8 @@ cpu_init_crit:
sub r13, r13, #4 @ space on current stack for scratch reg.
str r0, [r13] @ save R0's value.
ldr r0, _armboot_start @ get data regions start
- sub r0, r0, #(CFG_MALLOC_LEN) @ move past malloc pool
- sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack
+ sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
+ sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack
str lr, [r0] @ save caller lr in position 0 of saved stack
mrs r0, spsr @ get the spsr
str lr, [r0, #4] @ save spsr in position 1 of saved stack
diff --git a/cpu/arm1176/s3c64xx/interrupts.c b/cpu/arm1176/s3c64xx/interrupts.c
index 8356ae4..83f3806 100644
--- a/cpu/arm1176/s3c64xx/interrupts.c
+++ b/cpu/arm1176/s3c64xx/interrupts.c
@@ -41,6 +41,7 @@
#include <common.h>
#include <asm/proc-armv/ptrace.h>
#include <s3c6400.h>
+#include <div64.h>
static ulong timer_load_val;
@@ -148,7 +149,9 @@ void reset_timer(void)
ulong get_timer_masked(void)
{
- return get_ticks() / (timer_load_val / (100 * CFG_HZ));
+ unsigned long long res = get_ticks();
+ do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
+ return res;
}
ulong get_timer(ulong base)
@@ -158,7 +161,7 @@ ulong get_timer(ulong base)
void set_timer(ulong t)
{
- timestamp = t * (timer_load_val / (100 * CFG_HZ));
+ timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ));
}
void udelay(unsigned long usec)
diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S
index 991277f..cb891df 100644
--- a/cpu/arm1176/start.S
+++ b/cpu/arm1176/start.S
@@ -37,8 +37,8 @@
#endif
#include <s3c6400.h>
-#if !defined(CONFIG_ENABLE_MMU) && !defined(CFG_PHY_UBOOT_BASE)
-#define CFG_PHY_UBOOT_BASE CFG_UBOOT_BASE
+#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
+#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#endif
/*
@@ -105,7 +105,7 @@ _TEXT_BASE:
* by scsuh.
*/
_TEXT_PHY_BASE:
- .word CFG_PHY_UBOOT_BASE
+ .word CONFIG_SYS_PHY_UBOOT_BASE
.globl _armboot_start
_armboot_start:
@@ -209,7 +209,7 @@ enable_mmu:
/* Set the TTB register */
ldr r0, _mmu_table_base
- ldr r1, =CFG_PHY_UBOOT_BASE
+ ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
ldr r2, =0xfff00000
bic r0, r0, r2
orr r1, r0, r1
@@ -242,11 +242,11 @@ skip_hw_init:
/* Set up the stack */
stack_setup:
#ifdef CONFIG_MEMORY_UPPER_CODE
- ldr sp, =(CFG_UBOOT_BASE + CFG_UBOOT_SIZE - 0xc)
+ ldr sp, =(CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE - 0xc)
#else
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
sub sp, r0, #12 /* leave 3 words for abort-stack */
#endif
@@ -357,9 +357,9 @@ phy_last_jump:
stmia sp, {r0 - r12}
ldr r2, _armboot_start
- sub r2, r2, #(CFG_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
/* set base 2 words into abort stack */
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
/* get values for "aborted" pc and cpsr (into parm regs) */
ldmia r2, {r2 - r3}
/* grab pointer to old stack */
@@ -377,9 +377,9 @@ phy_last_jump:
/* setup our mode stack (enter in banked mode) */
ldr r13, _armboot_start
/* move past malloc pool */
- sub r13, r13, #(CFG_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
/* move to reserved a couple spots for abort stack */
- sub r13, r13, #(CFG_GBL_DATA_SIZE + 8)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
/* save caller lr in position 0 of saved stack */
str lr, [r13]
@@ -407,9 +407,9 @@ phy_last_jump:
/* get data regions start */
ldr r0, _armboot_start
/* move past malloc pool */
- sub r0, r0, #(CFG_MALLOC_LEN)
+ sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)
/* move past gbl and a couple spots for abort stack */
- sub r0, r0, #(CFG_GBL_DATA_SIZE + 8)
+ sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
/* save caller lr in position 0 of saved stack */
str lr, [r0]
/* get the spsr */
diff --git a/cpu/arm720t/config.mk b/cpu/arm720t/config.mk
index 641b91c..3cae1dc 100644
--- a/cpu/arm720t/config.mk
+++ b/cpu/arm720t/config.mk
@@ -32,4 +32,5 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
#
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c
index 60c1aa9..5ac8f59 100644
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -41,7 +41,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;
diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c
index 9854016..39ed345 100644
--- a/cpu/arm720t/interrupts.c
+++ b/cpu/arm720t/interrupts.c
@@ -95,7 +95,7 @@ static void timer_isr( void *data) {
unsigned int *pTime = (unsigned int *)data;
(*pTime)++;
- if ( !(*pTime % (CFG_HZ/4))) {
+ if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
/* toggle LED 0 */
PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
}
@@ -118,7 +118,7 @@ int interrupt_init (void)
IRQEN = 0;
/* operate timer 2 in non-prescale mode */
- TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) |
+ TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
NETARM_GEN_TCTL_ENABLE |
NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
@@ -166,9 +166,9 @@ int interrupt_init (void)
/*
* Load Timer data register with count down value.
- * count_down_val = CFG_SYS_CLK_FREQ/CFG_HZ
+ * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
*/
- PUT_REG( REG_TDATA0, (CFG_SYS_CLK_FREQ / CFG_HZ));
+ PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
/*
* Enable global interrupt
@@ -181,7 +181,7 @@ int interrupt_init (void)
#elif defined(CONFIG_LPC2292)
PUT32(T0IR, 0); /* disable all timer0 interrupts */
PUT32(T0TCR, 0); /* disable timer0 */
- PUT32(T0PR, CFG_SYS_CLK_FREQ / CFG_HZ);
+ PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
PUT32(T0MCR, 0);
PUT32(T0TC, 0);
PUT32(T0TCR, 1); /* enable timer0 */
@@ -223,7 +223,7 @@ void udelay (unsigned long usec)
ulong tmo;
tmo = usec / 1000;
- tmo *= CFG_HZ;
+ tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
tmo += get_timer (0);
@@ -268,10 +268,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) {
tmo = usec / 1000;
- tmo *= CFG_HZ;
+ tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
} else {
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -294,7 +294,7 @@ void udelay (unsigned long usec)
{
u32 ticks;
- ticks = (usec * CFG_HZ) / 1000000;
+ ticks = (usec * CONFIG_SYS_HZ) / 1000000;
ticks += get_timer (0);
diff --git a/cpu/arm720t/lpc2292/flash.c b/cpu/arm720t/lpc2292/flash.c
index e5c8697..3d2dc32 100644
--- a/cpu/arm720t/lpc2292/flash.c
+++ b/cpu/arm720t/lpc2292/flash.c
@@ -85,7 +85,7 @@ int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
command[1] = flash_addr;
command[2] = COPY_BUFFER_LOCATION;
command[3] = 512;
- command[4] = CFG_SYS_CLK_FREQ >> 10;
+ command[4] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP copy failed\n");
@@ -132,7 +132,7 @@ int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last)
command[0] = IAP_CMD_ERASE;
command[1] = s_first;
command[2] = s_last;
- command[3] = CFG_SYS_CLK_FREQ >> 10;
+ command[3] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP erase failed\n");
diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c
index 1b0e147..54a9b31 100644
--- a/cpu/arm720t/serial.c
+++ b/cpu/arm720t/serial.c
@@ -85,7 +85,7 @@ void serial_putc (const char c)
if (c == '\n')
serial_putc ('\r');
- tmo = get_timer (0) + 1 * CFG_HZ;
+ tmo = get_timer (0) + 1 * CONFIG_SYS_HZ;
while (IO_SYSFLG1 & SYSFLG1_UTXFF)
if (get_timer (0) > tmo)
break;
diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c
index a593cbc..1a1b2db 100644
--- a/cpu/arm720t/serial_netarm.c
+++ b/cpu/arm720t/serial_netarm.c
@@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* wait until transmitter is ready for another character */
#define TXWAITRDY(registers) \
{ \
- ulong tmo = get_timer(0) + 1 * CFG_HZ; \
+ ulong tmo = get_timer(0) + 1 * CONFIG_SYS_HZ; \
while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \
if (get_timer(0) > tmo) \
break; \
diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S
index 8423e4f..022b873 100644
--- a/cpu/arm720t/start.S
+++ b/cpu/arm720t/start.S
@@ -166,8 +166,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -444,8 +444,8 @@ lock_loop:
add r8, sp, #S_PC
ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@@ -477,8 +477,8 @@ lock_loop:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
diff --git a/cpu/arm920t/at91rm9200/i2c.c b/cpu/arm920t/at91rm9200/i2c.c
index 826cea8..9fd72d3 100644
--- a/cpu/arm920t/at91rm9200/i2c.c
+++ b/cpu/arm920t/at91rm9200/i2c.c
@@ -120,7 +120,7 @@ int
i2c_read (unsigned char chip, unsigned int addr, int alen,
unsigned char *buffer, int len)
{
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/* we only allow one address byte */
if (alen > 1)
return 1;
@@ -139,7 +139,7 @@ int
i2c_write(unsigned char chip, unsigned int addr, int alen,
unsigned char *buffer, int len)
{
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
int i;
unsigned char *buf;
@@ -189,18 +189,14 @@ i2c_init(int speed, int slaveaddr)
return;
}
-uchar i2c_reg_read(uchar i2c_addr, uchar reg)
+int i2c_set_bus_speed(unsigned int speed)
{
- unsigned char buf;
-
- i2c_read(i2c_addr, reg, 1, &buf, 1);
-
- return(buf);
+ return -1;
}
-void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
+unsigned int i2c_get_bus_speed(void)
{
- i2c_write(i2c_addr, reg, 1, &val, 1);
+ return CONFIG_SYS_I2C_SPEED;
}
#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/arm920t/at91rm9200/interrupts.c b/cpu/arm920t/at91rm9200/interrupts.c
index 1054602..5f0703c 100644
--- a/cpu/arm920t/at91rm9200/interrupts.c
+++ b/cpu/arm920t/at91rm9200/interrupts.c
@@ -35,8 +35,8 @@
#include <asm/arch/hardware.h>
/*#include <asm/proc/ptrace.h>*/
-/* the number of clocks per CFG_HZ */
-#define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ)
+/* the number of clocks per CONFIG_SYS_HZ */
+#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
/* macro to read the 16 bit timer */
#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
@@ -126,7 +126,7 @@ void udelay_masked (unsigned long usec)
ulong endtime;
signed long diff;
- tmo = CFG_HZ_CLOCK / 1000;
+ tmo = CONFIG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= 1000;
@@ -155,7 +155,7 @@ ulong get_tbclk (void)
{
ulong tbclk;
- tbclk = CFG_HZ;
+ tbclk = CONFIG_SYS_HZ;
return tbclk;
}
diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S
index 98363eb..66b07da 100644
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
@@ -79,7 +79,7 @@ lowlevel_init:
/* Get the CKGR Base Address */
ldr r1, =AT91C_BASE_CKGR
/* Main oscillator Enable register */
-#ifdef CFG_USE_MAIN_OSCILLATOR
+#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */
#else
ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */
diff --git a/cpu/arm920t/at91rm9200/spi.c b/cpu/arm920t/at91rm9200/spi.c
index 265d185..f3cb5d8 100644
--- a/cpu/arm920t/at91rm9200/spi.c
+++ b/cpu/arm920t/at91rm9200/spi.c
@@ -137,11 +137,11 @@ unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) &&
- ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
+ ((timeout = get_timer_masked() ) < CONFIG_SYS_SPI_WRITE_TOUT));
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
pDesc->state = IDLE;
- if (timeout >= CFG_SPI_WRITE_TOUT){
+ if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT){
printf("Error Timeout\n\r");
return DATAFLASH_ERROR;
}
diff --git a/cpu/arm920t/at91rm9200/usb.c b/cpu/arm920t/at91rm9200/usb.c
index c121de6..72355dc 100644
--- a/cpu/arm920t/at91rm9200/usb.c
+++ b/cpu/arm920t/at91rm9200/usb.c
@@ -23,7 +23,7 @@
#include <common.h>
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
# ifdef CONFIG_AT91RM9200
#include <asm/arch/hardware.h>
@@ -50,4 +50,4 @@ int usb_cpu_init_fail(void)
}
# endif /* CONFIG_AT91RM9200 */
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/cpu/arm920t/config.mk b/cpu/arm920t/config.mk
index 8db4adb..38718a3 100644
--- a/cpu/arm920t/config.mk
+++ b/cpu/arm920t/config.mk
@@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv4
#
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c
index f93bf57..1b9cde6 100644
--- a/cpu/arm920t/cpu.c
+++ b/cpu/arm920t/cpu.c
@@ -95,7 +95,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;
diff --git a/cpu/arm920t/imx/interrupts.c b/cpu/arm920t/imx/interrupts.c
index 03ce06d..ddcfb34 100644
--- a/cpu/arm920t/imx/interrupts.c
+++ b/cpu/arm920t/imx/interrupts.c
@@ -60,7 +60,7 @@ void reset_timer (void)
ulong get_timer (ulong base)
{
- return get_timer_masked ();
+ return get_timer_masked() - base;
}
void set_timer (ulong t)
@@ -112,7 +112,7 @@ ulong get_tbclk (void)
{
ulong tbclk;
- tbclk = CFG_HZ;
+ tbclk = CONFIG_SYS_HZ;
return tbclk;
}
diff --git a/cpu/arm920t/imx/serial.c b/cpu/arm920t/imx/serial.c
index 6c56acb..85f1167 100644
--- a/cpu/arm920t/imx/serial.c
+++ b/cpu/arm920t/imx/serial.c
@@ -52,6 +52,8 @@ struct imx_serial {
volatile uint32_t uts;
};
+DECLARE_GLOBAL_DATA_PTR;
+
void serial_setbrg (void)
{
serial_init();
@@ -67,6 +69,9 @@ extern void imx_gpio_mode(int gpio_mode);
int serial_init (void)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
+ unsigned int ufcr_rfdiv;
+ unsigned int refclk;
+
#ifdef CONFIG_IMX_SERIAL1
imx_gpio_mode(PC11_PF_UART1_TXD);
imx_gpio_mode(PC12_PF_UART1_RXD);
@@ -95,11 +100,33 @@ int serial_init (void)
/* Configure FIFOs */
base->ufcr = 0xa81;
+ /* set the baud rate.
+ *
+ * baud * 16 x
+ * --------- = -
+ * refclk y
+ *
+ * x - 1 = UBIR
+ * y - 1 = UBMR
+ *
+ * each register is 16 bits wide. refclk max is 96 MHz
+ *
+ */
+
+ ufcr_rfdiv = ((base->ufcr) & UFCR_RFDIV) >> 7;
+ if (ufcr_rfdiv == 6)
+ ufcr_rfdiv = 7;
+ else
+ ufcr_rfdiv = 6 - ufcr_rfdiv;
+
+ refclk = get_PERCLK1();
+ refclk /= ufcr_rfdiv;
+
/* Set the numerator value minus one of the BRM ratio */
- base->ubir = (CONFIG_BAUDRATE / 100) - 1;
+ base->ubir = (gd->baudrate / 100) - 1;
/* Set the denominator value minus one of the BRM ratio */
- base->ubmr = 10000 - 1;
+ base->ubmr = (refclk/(16 * 100)) - 1;
/* Set to 8N1 */
base->ucr2 &= ~UCR2_PREN;
@@ -117,22 +144,21 @@ int serial_init (void)
/* Clear status flags */
base->usr2 |= USR2_ADET |
- USR2_DTRF |
- USR2_IDLE |
- USR2_IRINT |
- USR2_WAKE |
- USR2_RTSF |
- USR2_BRCD |
- USR2_ORE |
- USR2_RDR;
+ USR2_DTRF |
+ USR2_IDLE |
+ USR2_IRINT |
+ USR2_WAKE |
+ USR2_RTSF |
+ USR2_BRCD |
+ USR2_ORE;
/* Clear status flags */
base->usr1 |= USR1_PARITYERR |
- USR1_RTSD |
- USR1_ESCF |
- USR1_FRAMERR |
- USR1_AIRINT |
- USR1_AWAKE;
+ USR1_RTSD |
+ USR1_ESCF |
+ USR1_FRAMERR |
+ USR1_AIRINT |
+ USR1_AWAKE;
return (0);
}
diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c
index c9cd066..09c54db 100644
--- a/cpu/arm920t/interrupts.c
+++ b/cpu/arm920t/interrupts.c
@@ -42,7 +42,7 @@ void do_irq (struct pt_regs *pt_regs)
/* ASSUMED to be a timer interrupt */
/* Just clear it - count handled in */
/* integratorap.c */
- *(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0;
+ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0;
#else
#error do_irq() not defined for this cpu type
#endif
diff --git a/cpu/arm920t/s3c24x0/i2c.c b/cpu/arm920t/s3c24x0/i2c.c
index 374b683..fba5cd1 100644
--- a/cpu/arm920t/s3c24x0/i2c.c
+++ b/cpu/arm920t/s3c24x0/i2c.c
@@ -384,7 +384,7 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
xaddr[3] = addr & 0xFF;
}
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -397,7 +397,7 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
* hidden in the chip address.
*/
if (alen > 0)
- chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
if ((ret =
i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen,
@@ -423,7 +423,7 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
}
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -436,7 +436,7 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
* hidden in the chip address.
*/
if (alen > 0)
- chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
return (i2c_transfer
(I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c
index 7ad9fcb..11e6804 100644
--- a/cpu/arm920t/s3c24x0/interrupts.c
+++ b/cpu/arm920t/s3c24x0/interrupts.c
@@ -179,7 +179,7 @@ ulong get_tbclk (void)
#elif defined(CONFIG_SBC2410X) || \
defined(CONFIG_SMDK2410) || \
defined(CONFIG_VCMA9)
- tbclk = CFG_HZ;
+ tbclk = CONFIG_SYS_HZ;
#else
# error "tbclk not configured"
#endif
diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c
index 421ebb4..9ccf575 100644
--- a/cpu/arm920t/s3c24x0/usb.c
+++ b/cpu/arm920t/s3c24x0/usb.c
@@ -23,7 +23,7 @@
#include <common.h>
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
#if defined(CONFIG_S3C2400)
@@ -69,4 +69,4 @@ int usb_cpu_init_fail (void)
}
# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
-#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c
index b57c2d8..641f270 100644
--- a/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/cpu/arm920t/s3c24x0/usb_ohci.c
@@ -654,7 +654,7 @@ static void td_fill (ohci_t *ohci, unsigned int info,
td->index = index;
td->data = (__u32)data;
#ifdef OHCI_FILL_TRACE
- if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
+ if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
for (i = 0; i < len; i++)
printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
printf("\n");
@@ -756,7 +756,7 @@ static void dl_transfer_length(td_t * td)
tdCBP = m32_swap (td->hwCBP);
- if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
+ if (!(usb_pipecontrol(lurb_priv->pipe) &&
((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
if (tdBE != 0) {
if (td->hwCBP == 0)
@@ -1025,7 +1025,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
#else
wait_ms(1);
#endif
- if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+ if (usb_pipeint(pipe)) {
info("Root-Hub submit IRQ: NOT implemented");
return 0;
}
@@ -1259,7 +1259,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
/* allow more time for a BULK device to react - some are slow */
#define BULK_TO 5000 /* timeout in milliseconds */
- if (usb_pipetype (pipe) == PIPE_BULK)
+ if (usb_pipebulk(pipe))
timeout = BULK_TO;
else
timeout = 100;
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 62231f8..fbcfe6d 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -24,7 +24,6 @@
* MA 02111-1307 USA
*/
-
#include <config.h>
#include <version.h>
#include <status_led.h>
@@ -119,7 +118,7 @@ start_code:
bl coloured_LED_init
bl red_LED_on
-#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
+#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
/*
* relocate exception table
*/
@@ -178,8 +177,6 @@ copyex:
bl cpu_init_crit
#endif
-#ifndef CONFIG_AT91RM9200
-
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
@@ -198,12 +195,12 @@ copy_loop:
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-#endif
+
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -261,7 +258,7 @@ cpu_init_crit:
* find a lowlevel_init.S in your board directory.
*/
mov ip, lr
-#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
+#if defined(CONFIG_AT91RM9200EK)
#else
bl lowlevel_init
@@ -315,8 +312,9 @@ cpu_init_crit:
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CONFIG_STACKSIZE)
+ sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@@ -348,8 +346,9 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ sub r13, r13, #(CONFIG_STACKSIZE)
+ sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
diff --git a/cpu/arm925t/config.mk b/cpu/arm925t/config.mk
index 8db4adb..38718a3 100644
--- a/cpu/arm925t/config.mk
+++ b/cpu/arm925t/config.mk
@@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv4
#
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c
index d85b7fa..b9f0931 100644
--- a/cpu/arm925t/cpu.c
+++ b/cpu/arm925t/cpu.c
@@ -95,7 +95,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;
diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/interrupts.c
index 208a25bd..3ef4554 100644
--- a/cpu/arm925t/interrupts.c
+++ b/cpu/arm925t/interrupts.c
@@ -39,7 +39,7 @@
#define TIMER_LOAD_VAL 0xffffffff
/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
+#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
static ulong timestamp;
static ulong lastdec;
@@ -50,9 +50,9 @@ int interrupt_init (void)
int32_t val;
/* Start the decrementer ticking down from 0xffffffff */
- *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
- val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
- *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
+ *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
+ val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT);
+ *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
/* init the timestamp and lastdec value */
reset_timer_masked();
@@ -86,10 +86,10 @@ void udelay (unsigned long usec)
if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
}else{ /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -145,10 +145,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -178,6 +178,6 @@ ulong get_tbclk (void)
{
ulong tbclk;
- tbclk = CFG_HZ;
+ tbclk = CONFIG_SYS_HZ;
return tbclk;
}
diff --git a/cpu/arm925t/start.S b/cpu/arm925t/start.S
index 5ddda54..c48014d 100644
--- a/cpu/arm925t/start.S
+++ b/cpu/arm925t/start.S
@@ -190,8 +190,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -295,8 +295,8 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@@ -328,8 +328,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
diff --git a/cpu/arm926ejs/Makefile b/cpu/arm926ejs/Makefile
index 0facce4..d5ac7d3 100644
--- a/cpu/arm926ejs/Makefile
+++ b/cpu/arm926ejs/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
-COBJS = interrupts.o cpu.o cpuinfo.o
+COBJS = interrupts.o cpu.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile
index 44cde1a..2d2a888 100644
--- a/cpu/arm926ejs/at91/Makefile
+++ b/cpu/arm926ejs/at91/Makefile
@@ -25,7 +25,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
-COBJS-y += ether.o
COBJS-y += timer.o
COBJS-$(CONFIG_HAS_DATAFLASH) +=spi.o
COBJS-y += usb.o
diff --git a/cpu/arm926ejs/at91/config.mk b/cpu/arm926ejs/at91/config.mk
index 31491a8..06177e6 100644
--- a/cpu/arm926ejs/at91/config.mk
+++ b/cpu/arm926ejs/at91/config.mk
@@ -1,3 +1,2 @@
-PLATFORM_CPPFLAGS += -march=armv5te
PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
LDSCRIPT := $(SRCTREE)/cpu/arm926ejs/at91/u-boot.lds
diff --git a/cpu/arm926ejs/at91/ether.c b/cpu/arm926ejs/at91/ether.c
deleted file mode 100644
index 7e11fe4..0000000
--- a/cpu/arm926ejs/at91/ether.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
-
-#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
-void at91sam9_eth_initialize(bd_t *bi)
-{
- macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
-}
-#endif
diff --git a/cpu/arm926ejs/at91/spi.c b/cpu/arm926ejs/at91/spi.c
index c9fe6d8..3eb252c 100644
--- a/cpu/arm926ejs/at91/spi.c
+++ b/cpu/arm926ejs/at91/spi.c
@@ -48,7 +48,7 @@ void AT91F_SpiInit(void)
((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
AT91_BASE_SPI + AT91_SPI_CSR(0));
-#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS1
+#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
/* Configure CS1 */
writel(AT91_SPI_NCPHA |
(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
@@ -57,7 +57,7 @@ void AT91F_SpiInit(void)
AT91_BASE_SPI + AT91_SPI_CSR(1));
#endif
-#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS3
+#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
/* Configure CS3 */
writel(AT91_SPI_NCPHA |
(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
@@ -144,11 +144,11 @@ unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
- ((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT));
+ ((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT));
writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
pDesc->state = IDLE;
- if (timeout >= CFG_SPI_WRITE_TOUT) {
+ if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
printf("Error Timeout\n\r");
return DATAFLASH_ERROR;
}
diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c
index c79ec7e..fec545b 100644
--- a/cpu/arm926ejs/at91/timer.c
+++ b/cpu/arm926ejs/at91/timer.c
@@ -130,7 +130,7 @@ ulong get_tbclk(void)
{
ulong tbclk;
- tbclk = CFG_HZ;
+ tbclk = CONFIG_SYS_HZ;
return tbclk;
}
diff --git a/cpu/arm926ejs/at91/u-boot.lds b/cpu/arm926ejs/at91/u-boot.lds
index 996f401..4778d1e 100644
--- a/cpu/arm926ejs/at91/u-boot.lds
+++ b/cpu/arm926ejs/at91/u-boot.lds
@@ -52,6 +52,6 @@ SECTIONS
. = ALIGN(4);
__bss_start = .;
- .bss : { *(.bss) }
+ .bss : { *(.bss) . = ALIGN(4); }
_end = .;
}
diff --git a/cpu/arm926ejs/at91/usb.c b/cpu/arm926ejs/at91/usb.c
index 2a92f73..a15ab16 100644
--- a/cpu/arm926ejs/at91/usb.c
+++ b/cpu/arm926ejs/at91/usb.c
@@ -23,7 +23,7 @@
#include <common.h>
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
@@ -31,6 +31,15 @@
int usb_cpu_init(void)
{
+
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
+ defined(CONFIG_AT91SAM9263)
+ /* Enable PLLB */
+ at91_sys_write(AT91_CKGR_PLLBR, CONFIG_SYS_AT91_PLLB);
+ while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
+ ;
+#endif
+
/* Enable USB host clock. */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP);
#ifdef CONFIG_AT91SAM9261
@@ -51,6 +60,15 @@ int usb_cpu_stop(void)
#else
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP);
#endif
+
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
+ defined(CONFIG_AT91SAM9263)
+ /* Disable PLLB */
+ at91_sys_write(AT91_CKGR_PLLBR, 0);
+ while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != 0)
+ ;
+#endif
+
return 0;
}
@@ -59,4 +77,4 @@ int usb_cpu_init_fail(void)
return usb_cpu_stop();
}
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/cpu/arm926ejs/config.mk b/cpu/arm926ejs/config.mk
index 8db4adb..a57d03a 100644
--- a/cpu/arm926ejs/config.mk
+++ b/cpu/arm926ejs/config.mk
@@ -24,11 +24,12 @@
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
-msoft-float
-PLATFORM_CPPFLAGS += -march=armv4
+PLATFORM_CPPFLAGS += -march=armv5te
# =========================================================================
#
# Supply options according to compiler version
#
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index 56c6289..48a2c0b 100644
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -95,7 +95,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;
diff --git a/cpu/arm926ejs/davinci/dp83848.c b/cpu/arm926ejs/davinci/dp83848.c
index 59f039b..c71c685 100644
--- a/cpu/arm926ejs/davinci/dp83848.c
+++ b/cpu/arm926ejs/davinci/dp83848.c
@@ -64,29 +64,16 @@ int dp83848_get_link_speed(int phy_addr)
return(0);
/* Speed doesn't matter, there is no setting for it in EMAC... */
- if (tmp & DP83848_SPEED) {
- if (tmp & DP83848_DUPLEX) {
- /* set DM644x EMAC for Full Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
+ if (tmp & DP83848_DUPLEX) {
+ /* set DM644x EMAC for Full Duplex */
+ emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
+ EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
} else {
- if (tmp & DP83848_DUPLEX) {
- /* set DM644x EMAC for Full Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
+ /*set DM644x EMAC for Half Duplex */
+ emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
}
- return(0);
+ return(1);
}
diff --git a/cpu/arm926ejs/davinci/i2c.c b/cpu/arm926ejs/davinci/i2c.c
index af9dc03..3ba20ef 100644
--- a/cpu/arm926ejs/davinci/i2c.c
+++ b/cpu/arm926ejs/davinci/i2c.c
@@ -104,7 +104,7 @@ void i2c_init(int speed, int slaveadd)
}
psc = 2;
- div = (CFG_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
+ div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */
REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */
REG(I2C_SCLH) = div - REG(I2C_SCLL);
@@ -331,21 +331,4 @@ int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
return(0);
}
-
-u_int8_t i2c_reg_read(u_int8_t chip, u_int8_t reg)
-{
- u_int8_t tmp;
-
- i2c_read(chip, reg, 1, &tmp, 1);
- return(tmp);
-}
-
-
-void i2c_reg_write(u_int8_t chip, u_int8_t reg, u_int8_t val)
-{
- u_int8_t tmp;
-
- i2c_write(chip, reg, 1, &tmp, 1);
-}
-
#endif /* CONFIG_DRIVER_DAVINCI_I2C */
diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c
index 5a1da63..014e2b0 100644
--- a/cpu/arm926ejs/davinci/nand.c
+++ b/cpu/arm926ejs/davinci/nand.c
@@ -44,14 +44,14 @@
#include <common.h>
#include <asm/io.h>
-#ifdef CFG_USE_NAND
+#ifdef CONFIG_SYS_USE_NAND
#if !defined(CONFIG_NAND_LEGACY)
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/emif_defs.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
@@ -87,8 +87,11 @@ static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
#endif
}
-#ifdef CFG_NAND_HW_ECC
-#ifdef CFG_NAND_LARGEPAGE
+#ifdef CONFIG_SYS_NAND_HW_ECC
+#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
+/* Linux-compatible ECC uses MTD defaults. */
+/* These layouts are not compatible with Linux or RBL/UBL. */
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout davinci_nand_ecclayout = {
.eccbytes = 12,
.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
@@ -100,7 +103,7 @@ static struct nand_ecclayout davinci_nand_ecclayout = {
{.offset = 60, .length = 4}
}
};
-#elif defined(CFG_NAND_SMALLPAGE)
+#elif defined(CONFIG_SYS_NAND_SMALLPAGE)
static struct nand_ecclayout davinci_nand_ecclayout = {
.eccbytes = 3,
.eccpos = {0, 1, 2},
@@ -110,8 +113,9 @@ static struct nand_ecclayout davinci_nand_ecclayout = {
}
};
#else
-#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
+#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
#endif
+#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
@@ -150,6 +154,15 @@ static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
{
u_int32_t tmp;
+#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
+ /*
+ * This is not how you should read ECCs on large page Davinci devices.
+ * The region parameter gets you ECCs for flash chips on different chip
+ * selects, not the 4x512 byte pages in a 2048 byte page.
+ *
+ * Preserved for backwards compatibility though.
+ */
+
int region, n;
struct nand_chip *this = mtd->priv;
@@ -163,9 +176,26 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
*ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0);
region++;
}
+#else
+ const int region = 1;
+
+ tmp = nand_davinci_readecc(mtd, region);
+
+ /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
+ * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
+ tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
+
+ /* Invert so that erased block ECC is correct */
+ tmp = ~tmp;
+
+ *ecc_code++ = tmp;
+ *ecc_code++ = tmp >> 8;
+ *ecc_code++ = tmp >> 16;
+#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
return(0);
}
+#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf)
{
u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8);
@@ -282,13 +312,14 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in
return(-1);
}
}
+#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
{
- struct nand_chip *this;
+ struct nand_chip *this = mtd->priv;
+#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
int block_count = 0, i, rc;
- this = mtd->priv;
block_count = (this->ecc.size/512);
for (i = 0; i < block_count; i++) {
if (memcmp(read_ecc, calc_ecc, 3) != 0) {
@@ -301,9 +332,44 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *
calc_ecc += 3;
dat += 512;
}
+#else
+ u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
+ (read_ecc[2] << 16);
+ u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
+ (calc_ecc[2] << 16);
+ u_int32_t diff = ecc_calc ^ ecc_nand;
+
+ if (diff) {
+ if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
+ /* Correctable error */
+ if ((diff >> (12 + 3)) < this->ecc.size) {
+ uint8_t find_bit = 1 << ((diff >> 12) & 7);
+ uint32_t find_byte = diff >> (12 + 3);
+
+ dat[find_byte] ^= find_bit;
+ MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
+ "bit ECC error at offset: %d, bit: "
+ "%d\n", find_byte, find_bit);
+ return 1;
+ } else {
+ return -1;
+ }
+ } else if (!(diff & (diff - 1))) {
+ /* Single bit ECC error in the ECC itself,
+ nothing to fix */
+ MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
+ "ECC.\n");
+ return 1;
+ } else {
+ /* Uncorrectable error */
+ MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
+ return -1;
+ }
+ }
+#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
return(0);
}
-#endif
+#endif /* CONFIG_SYS_NAND_HW_ECC */
static int nand_davinci_dev_ready(struct mtd_info *mtd)
{
@@ -365,27 +431,32 @@ int board_nand_init(struct nand_chip *nand)
nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA;
nand->chip_delay = 0;
nand->select_chip = nand_davinci_select_chip;
-#ifdef CFG_NAND_USE_FLASH_BBT
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
nand->options = NAND_USE_FLASH_BBT;
#endif
-#ifdef CFG_NAND_HW_ECC
+#ifdef CONFIG_SYS_NAND_HW_ECC
nand->ecc.mode = NAND_ECC_HW;
-#ifdef CFG_NAND_LARGEPAGE
+#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
+ nand->ecc.layout = &davinci_nand_ecclayout;
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
nand->ecc.size = 2048;
nand->ecc.bytes = 12;
-#elif defined(CFG_NAND_SMALLPAGE)
+#elif defined(CONFIG_SYS_NAND_SMALLPAGE)
nand->ecc.size = 512;
nand->ecc.bytes = 3;
#else
-#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
+#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
#endif
- nand->ecc.layout = &davinci_nand_ecclayout;
+#else
+ nand->ecc.size = 512;
+ nand->ecc.bytes = 3;
+#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
nand->ecc.calculate = nand_davinci_calculate_ecc;
nand->ecc.correct = nand_davinci_correct_data;
nand->ecc.hwctl = nand_davinci_enable_hwecc;
#else
nand->ecc.mode = NAND_ECC_SOFT;
-#endif
+#endif /* CONFIG_SYS_NAND_HW_ECC */
/* Set address of hardware control function */
nand->cmd_ctrl = nand_davinci_hwcontrol;
@@ -401,4 +472,4 @@ int board_nand_init(struct nand_chip *nand)
#else
#error "U-Boot legacy NAND support not available for DaVinci chips"
#endif
-#endif /* CFG_USE_NAND */
+#endif /* CONFIG_SYS_USE_NAND */
diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c
index 6c670f0..773735a 100644
--- a/cpu/arm926ejs/davinci/timer.c
+++ b/cpu/arm926ejs/davinci/timer.c
@@ -54,9 +54,9 @@ typedef volatile struct {
u_int32_t wdtcr;
} davinci_timer;
-davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE;
+davinci_timer *timer = (davinci_timer *)CONFIG_SYS_TIMERBASE;
-#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ)
+#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
#define TIM_CLK_DIV 16
static ulong timestamp;
@@ -117,7 +117,7 @@ void udelay(unsigned long usec)
ulong endtime;
signed long diff;
- tmo = CFG_HZ_CLOCK / 1000;
+ tmo = CONFIG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= (1000 * TIM_CLK_DIV);
@@ -144,5 +144,5 @@ unsigned long long get_ticks(void)
*/
ulong get_tbclk(void)
{
- return CFG_HZ;
+ return CONFIG_SYS_HZ;
}
diff --git a/cpu/arm926ejs/omap/Makefile b/cpu/arm926ejs/omap/Makefile
index c335d5c..74aea74 100644
--- a/cpu/arm926ejs/omap/Makefile
+++ b/cpu/arm926ejs/omap/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
-COBJS = timer.o
+COBJS = timer.o cpuinfo.o
SOBJS = reset.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/arm926ejs/cpuinfo.c b/cpu/arm926ejs/omap/cpuinfo.c
index 35ba7db..35ba7db 100644
--- a/cpu/arm926ejs/cpuinfo.c
+++ b/cpu/arm926ejs/omap/cpuinfo.c
diff --git a/cpu/arm926ejs/omap/timer.c b/cpu/arm926ejs/omap/timer.c
index a2a9133..49e74ab 100644
--- a/cpu/arm926ejs/omap/timer.c
+++ b/cpu/arm926ejs/omap/timer.c
@@ -41,7 +41,7 @@
#define TIMER_LOAD_VAL 0xffffffff
/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
+#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
static ulong timestamp;
static ulong lastdec;
@@ -51,9 +51,9 @@ int timer_init (void)
int32_t val;
/* Start the decrementer ticking down from 0xffffffff */
- *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
- val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
- *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
+ *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
+ val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT);
+ *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
/* init the timestamp and lastdec value */
reset_timer_masked();
@@ -87,10 +87,10 @@ void udelay (unsigned long usec)
if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
}else{ /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -140,10 +140,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -172,6 +172,6 @@ ulong get_tbclk (void)
{
ulong tbclk;
- tbclk = CFG_HZ;
+ tbclk = CONFIG_SYS_HZ;
return tbclk;
}
diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S
index a61fa18..ed4932a 100644
--- a/cpu/arm926ejs/start.S
+++ b/cpu/arm926ejs/start.S
@@ -165,8 +165,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -276,8 +276,8 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@@ -310,8 +310,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
diff --git a/cpu/arm926ejs/versatile/timer.c b/cpu/arm926ejs/versatile/timer.c
index f01f318..9ac867e 100755
--- a/cpu/arm926ejs/versatile/timer.c
+++ b/cpu/arm926ejs/versatile/timer.c
@@ -41,7 +41,7 @@
#define TIMER_LOAD_VAL 0xffffffff
/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
+#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
static ulong timestamp;
static ulong lastdec;
@@ -62,9 +62,9 @@ int timer_init (void)
ulong tmr_ctrl_val;
/* 1st disable the Timer */
- tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8);
+ tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
tmr_ctrl_val &= ~TIMER_ENABLE;
- *(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val;
+ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
/*
* The Timer Control Register has one Undefined/Shouldn't Use Bit
@@ -78,11 +78,11 @@ int timer_init (void)
* Tmr Siz : 16 Bit Counter
* Tmr in Wrapping Mode
*/
- tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8);
+ tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
- *(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val;
+ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
/* init the timestamp and lastdec value */
reset_timer_masked();
@@ -116,10 +116,10 @@ void udelay (unsigned long usec)
if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
}else{ /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -169,10 +169,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -201,6 +201,6 @@ ulong get_tbclk (void)
{
ulong tbclk;
- tbclk = CFG_HZ;
+ tbclk = CONFIG_SYS_HZ;
return tbclk;
}
diff --git a/cpu/arm946es/config.mk b/cpu/arm946es/config.mk
index 81ca288..6190e16 100644
--- a/cpu/arm946es/config.mk
+++ b/cpu/arm946es/config.mk
@@ -25,3 +25,11 @@ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
-msoft-float
PLATFORM_CPPFLAGS += -march=armv4
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c
index 4c63a8d..44c589a 100644
--- a/cpu/arm946es/cpu.c
+++ b/cpu/arm946es/cpu.c
@@ -95,7 +95,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;
diff --git a/cpu/arm946es/interrupts.c b/cpu/arm946es/interrupts.c
index a2c3646..c13d309 100644
--- a/cpu/arm946es/interrupts.c
+++ b/cpu/arm946es/interrupts.c
@@ -121,10 +121,10 @@ void udelay_masked (unsigned long usec)
if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ_CLOCK; /* find number of "ticks" to wait to achieve target */
+ tmo *= CONFIG_SYS_HZ_CLOCK; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
}else{ /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ_CLOCK;
+ tmo = usec * CONFIG_SYS_HZ_CLOCK;
tmo /= (1000*1000);
}
@@ -151,7 +151,7 @@ ulong get_tbclk (void)
{
ulong tbclk;
- tbclk = CFG_HZ;
+ tbclk = CONFIG_SYS_HZ;
return tbclk;
}
diff --git a/cpu/arm946es/start.S b/cpu/arm946es/start.S
index 9e97f53..7972b00 100644
--- a/cpu/arm946es/start.S
+++ b/cpu/arm946es/start.S
@@ -157,8 +157,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -264,8 +264,8 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@@ -298,8 +298,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
diff --git a/cpu/arm_intcm/config.mk b/cpu/arm_intcm/config.mk
index 81ca288..6190e16 100644
--- a/cpu/arm_intcm/config.mk
+++ b/cpu/arm_intcm/config.mk
@@ -25,3 +25,11 @@ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
-msoft-float
PLATFORM_CPPFLAGS += -march=armv4
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c
index e2309f8..ccf7fd5 100644
--- a/cpu/arm_intcm/cpu.c
+++ b/cpu/arm_intcm/cpu.c
@@ -43,7 +43,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;
diff --git a/cpu/arm_intcm/start.S b/cpu/arm_intcm/start.S
index d5778a0..ee0804a 100644
--- a/cpu/arm_intcm/start.S
+++ b/cpu/arm_intcm/start.S
@@ -155,8 +155,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -240,8 +240,8 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@@ -274,8 +274,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
diff --git a/cpu/at32ap/at32ap700x/clk.c b/cpu/at32ap/at32ap700x/clk.c
index a6a6c88..2c2e19c 100644
--- a/cpu/at32ap/at32ap700x/clk.c
+++ b/cpu/at32ap/at32ap700x/clk.c
@@ -39,10 +39,10 @@ void clk_init(void)
#ifdef CONFIG_PLL
/* Initialize the PLL */
- sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
- | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
- | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
- | SM_BF(PLLOPT, CFG_PLL0_OPT)
+ sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CONFIG_SYS_PLL0_SUPPRESS_CYCLES)
+ | SM_BF(PLLMUL, CONFIG_SYS_PLL0_MUL - 1)
+ | SM_BF(PLLDIV, CONFIG_SYS_PLL0_DIV - 1)
+ | SM_BF(PLLOPT, CONFIG_SYS_PLL0_OPT)
| SM_BF(PLLOSC, 0)
| SM_BIT(PLLEN)));
@@ -52,14 +52,14 @@ void clk_init(void)
/* Set up clocks for the CPU and all peripheral buses */
cksel = 0;
- if (CFG_CLKDIV_CPU)
- cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
- if (CFG_CLKDIV_HSB)
- cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
- if (CFG_CLKDIV_PBA)
- cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
- if (CFG_CLKDIV_PBB)
- cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
+ if (CONFIG_SYS_CLKDIV_CPU)
+ cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CONFIG_SYS_CLKDIV_CPU - 1);
+ if (CONFIG_SYS_CLKDIV_HSB)
+ cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CONFIG_SYS_CLKDIV_HSB - 1);
+ if (CONFIG_SYS_CLKDIV_PBA)
+ cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CONFIG_SYS_CLKDIV_PBA - 1);
+ if (CONFIG_SYS_CLKDIV_PBB)
+ cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CONFIG_SYS_CLKDIV_PBB - 1);
sm_writel(PM_CKSEL, cksel);
#ifdef CONFIG_PLL
diff --git a/cpu/at32ap/cache.c b/cpu/at32ap/cache.c
index 41fb5aa..16a0565 100644
--- a/cpu/at32ap/cache.c
+++ b/cpu/at32ap/cache.c
@@ -28,7 +28,7 @@ void dcache_clean_range(volatile void *start, size_t size)
{
unsigned long v, begin, end, linesz;
- linesz = CFG_DCACHE_LINESZ;
+ linesz = CONFIG_SYS_DCACHE_LINESZ;
/* You asked for it, you got it */
begin = (unsigned long)start & ~(linesz - 1);
@@ -44,7 +44,7 @@ void dcache_invalidate_range(volatile void *start, size_t size)
{
unsigned long v, begin, end, linesz;
- linesz = CFG_DCACHE_LINESZ;
+ linesz = CONFIG_SYS_DCACHE_LINESZ;
/* You asked for it, you got it */
begin = (unsigned long)start & ~(linesz - 1);
@@ -58,7 +58,7 @@ void dcache_flush_range(volatile void *start, size_t size)
{
unsigned long v, begin, end, linesz;
- linesz = CFG_DCACHE_LINESZ;
+ linesz = CONFIG_SYS_DCACHE_LINESZ;
/* You asked for it, you got it */
begin = (unsigned long)start & ~(linesz - 1);
@@ -74,7 +74,7 @@ void icache_invalidate_range(volatile void *start, size_t size)
{
unsigned long v, begin, end, linesz;
- linesz = CFG_ICACHE_LINESZ;
+ linesz = CONFIG_SYS_ICACHE_LINESZ;
/* You asked for it, you got it */
begin = (unsigned long)start & ~(linesz - 1);
diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c
index 0ba8361..904bfb2 100644
--- a/cpu/at32ap/cpu.c
+++ b/cpu/at32ap/cpu.c
@@ -32,12 +32,12 @@
#include "hsmc3.h"
/* Sanity checks */
-#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
- || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \
- || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
+#if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB) \
+ || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA) \
+ || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB)
# error Constraint fCPU >= fHSB >= fPB{A,B} violated
#endif
-#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
+#if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) || (CONFIG_SYS_PLL0_DIV < 1))
# error Invalid PLL multiplier and/or divider
#endif
@@ -47,7 +47,7 @@ int cpu_init(void)
{
extern void _evba(void);
- gd->cpu_hz = CFG_OSC0_HZ;
+ gd->cpu_hz = CONFIG_SYS_OSC0_HZ;
/* TODO: Move somewhere else, but needs to be run before we
* increase the clock frequency. */
diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c
index 992612b..f74121c 100644
--- a/cpu/at32ap/hsdramc.c
+++ b/cpu/at32ap/hsdramc.c
@@ -21,7 +21,7 @@
*/
#include <common.h>
-#ifdef CFG_HSDRAMC
+#ifdef CONFIG_SYS_HSDRAMC
#include <asm/io.h>
#include <asm/sdram.h>
@@ -117,4 +117,4 @@ unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
return sdram_size;
}
-#endif /* CFG_HSDRAMC */
+#endif /* CONFIG_SYS_HSDRAMC */
diff --git a/cpu/at32ap/interrupts.c b/cpu/at32ap/interrupts.c
index 160838e..75cc39e 100644
--- a/cpu/at32ap/interrupts.c
+++ b/cpu/at32ap/interrupts.c
@@ -82,7 +82,7 @@ void set_timer(unsigned long t)
unsigned long long ticks = t;
unsigned long lo, hi, hi_new;
- ticks = (ticks * get_tbclk()) / CFG_HZ;
+ ticks = (ticks * get_tbclk()) / CONFIG_SYS_HZ;
hi = ticks >> 32;
lo = ticks & 0xffffffffUL;
@@ -137,7 +137,7 @@ void timer_init(void)
sysreg_write(COUNT, 0);
- tmp = (u64)CFG_HZ << 32;
+ tmp = (u64)CONFIG_SYS_HZ << 32;
tmp += gd->cpu_hz / 2;
do_div(tmp, gd->cpu_hz);
tb_factor = (u32)tmp;
diff --git a/cpu/at32ap/start.S b/cpu/at32ap/start.S
index 907e9b1..d37a46e 100644
--- a/cpu/at32ap/start.S
+++ b/cpu/at32ap/start.S
@@ -188,7 +188,7 @@ at32ap_low_level_init:
.align 2
.type sp_init,@object
sp_init:
- .long CFG_INIT_SP_ADDR
+ .long CONFIG_SYS_INIT_SP_ADDR
got_init:
.long 3b - _GLOBAL_OFFSET_TABLE_
diff --git a/cpu/blackfin/Makefile b/cpu/blackfin/Makefile
index f194a38..8fed4b4 100644
--- a/cpu/blackfin/Makefile
+++ b/cpu/blackfin/Makefile
@@ -16,7 +16,7 @@ LIB = $(obj)lib$(CPU).a
EXTRA :=
CEXTRA := initcode.o
SEXTRA := start.o
-SOBJS := interrupt.o cache.o flush.o
+SOBJS := interrupt.o cache.o
COBJS := cpu.o traps.o interrupts.o reset.o serial.o i2c.o watchdog.o
ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
diff --git a/cpu/blackfin/cpu.c b/cpu/blackfin/cpu.c
index 53de5ab..9efd88e 100644
--- a/cpu/blackfin/cpu.c
+++ b/cpu/blackfin/cpu.c
@@ -14,46 +14,11 @@
#include <asm/blackfin.h>
#include <asm/cplb.h>
#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
#include <asm/mach-common/bits/trace.h>
#include "cpu.h"
#include "serial.h"
-void icache_enable(void)
-{
- bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() | (IMC | ENICPLB));
- SSYNC();
-}
-
-void icache_disable(void)
-{
- bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() & ~(IMC | ENICPLB));
- SSYNC();
-}
-
-int icache_status(void)
-{
- return bfin_read_IMEM_CONTROL() & ENICPLB;
-}
-
-void dcache_enable(void)
-{
- bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() | (ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
- SSYNC();
-}
-
-void dcache_disable(void)
-{
- bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
- SSYNC();
-}
-
-int dcache_status(void)
-{
- return bfin_read_DMEM_CONTROL() & ENDCPLB;
-}
-
__attribute__ ((__noreturn__))
void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
{
@@ -133,9 +98,8 @@ int irq_init(void)
bfin_write_EVT15(evt_default);
bfin_write_ILAT(0);
CSYNC();
- /* enable all interrupts except for core timer */
- irq_flags = 0xffffffbf;
+ /* enable hardware error irq */
+ irq_flags = 0x3f;
local_irq_enable();
- CSYNC();
return 0;
}
diff --git a/cpu/blackfin/flush.S b/cpu/blackfin/flush.S
deleted file mode 100644
index 417f798..0000000
--- a/cpu/blackfin/flush.S
+++ /dev/null
@@ -1,230 +0,0 @@
-/* flush.S - low level cache flushing routines
- * Copyright (C) 2003-2007 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <asm/mach-common/bits/mpu.h>
-
-.text
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the data cache.
- */
-
-ENTRY(_flush_data_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = HI(DCPLB_ADDR0);
- P5.L = LO(DCPLB_ADDR0);
- P4.H = HI(DCPLB_DATA0);
- P4.L = LO(DCPLB_DATA0);
- R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
- R6 = 16;
-.Lnext: R0 = [P5++];
- R1 = [P4++];
- CC = BITTST(R1, 14); /* Is it write-through?*/
- IF CC JUMP .Lskip; /* If so, ignore it.*/
- R2 = R1 & R7; /* Is it a dirty, cached page?*/
- CC = R2;
- IF !CC JUMP .Lskip; /* If not, ignore it.*/
- [--SP] = RETS;
- CALL _dcplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-.Lskip: R6 += -1;
- CC = R6;
- IF CC JUMP .Lnext;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-ENDPROC(_flush_data_cache)
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular DCPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_dcplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP .Ldflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* The page could be mapped into Bank A or Bank B, depending
- * on (a) whether both banks are configured as cache, and
- * (b) on whether address bit A[x] is set. x is determined
- * by DCBS in DMEM_CONTROL
- */
-
- R2 = 0; /* Default to Bank A (Bank B would be 1)*/
-
- P0.L = LO(DMEM_CONTROL);
- P0.H = HI(DMEM_CONTROL);
-
- R3 = [P0]; /* If Bank B is not enabled as cache*/
- CC = BITTST(R3, 2); /* then Bank A is our only option.*/
- IF CC JUMP .Lbank_chosen;
-
- R4 = 1<<14; /* If DCBS==0, use A[14].*/
- R5 = R4 << 7; /* If DCBS==1, use A[23];*/
- CC = BITTST(R3, 4);
- IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
- R5 = R0 & R4; /* Use it to test the Page address*/
- CC = R5; /* and if that bit is set, we use Bank B,*/
- R2 = CC; /* else we use Bank A.*/
- R2 <<= 23; /* The Bank selection's at posn 23.*/
-
-.Lbank_chosen:
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /*Anamoly 05000209*/
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
- /* Save in extraction pattern for later deposit.*/
- R3.H = R4.L << 0;
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R2 = Bank select mask
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = LO(DTEST_COMMAND);
- P5.H = HI(DTEST_COMMAND);
- P4.L = LO(DTEST_DATA0);
- P4.H = HI(DTEST_DATA0);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 2;
- LSETUP (.Lfs1, .Lfe1) LC1 = P2;
-.Lfs1: P0 = 64; /* iterate over all sets*/
- LSETUP (.Lfs0, .Lfe0) LC0 = P0;
-.Lfs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
- BITSET(R6,14);
- [P5] = R6; /* Issue Command*/
- SSYNC;
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP .Lfskip; /* and skip if not.*/
- CC = BITTST(R7, 1); /* Check if dirty*/
- IF !CC JUMP .Lfskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP .Lfskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- SSYNC;
- FLUSHINV [P3]; /* And flush the entry*/
-.Lfskip:
-.Lfe0: R5 += 1; /* Advance to next Set*/
-.Lfe1: BITSET(R2, 26); /* Go to next Way.*/
-
-.Ldfinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-.Ldflush_whole_page:
-
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (.Leall, .Leall) LC0 = P1;
-.Leall: FLUSHINV [P0++];
- SSYNC;
- JUMP .Ldfinished;
-ENDPROC(_dcplb_flush)
-
-.align 4;
-page_prefix_table:
-.byte4 0xFFFFFC00; /* 1K */
-.byte4 0xFFFFF000; /* 4K */
-.byte4 0xFFF00000; /* 1M */
-.byte4 0xFFC00000; /* 4M */
-.page_prefix_table.end:
diff --git a/cpu/blackfin/i2c.c b/cpu/blackfin/i2c.c
index 60f03d4..2a3e223 100644
--- a/cpu/blackfin/i2c.c
+++ b/cpu/blackfin/i2c.c
@@ -425,20 +425,4 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
}
-uchar i2c_reg_read(uchar chip, uchar reg)
-{
- uchar buf;
-
- PRINTD("i2c_reg_read: chip=0x%02x, reg=0x%02x\n", chip, reg);
- i2c_read(chip, reg, 0, &buf, 1);
- return (buf);
-}
-
-void i2c_reg_write(uchar chip, uchar reg, uchar val)
-{
- PRINTD("i2c_reg_write: chip=0x%02x, reg=0x%02x, val=0x%02x\n", chip,
- reg, val);
- i2c_write(chip, reg, 0, &val, 1);
-}
-
#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/blackfin/interrupts.c b/cpu/blackfin/interrupts.c
index 80c5505..d4dd636 100644
--- a/cpu/blackfin/interrupts.c
+++ b/cpu/blackfin/interrupts.c
@@ -48,7 +48,7 @@ ulong get_tbclk(void)
{
ulong tbclk;
- tbclk = CFG_HZ;
+ tbclk = CONFIG_SYS_HZ;
return tbclk;
}
diff --git a/cpu/blackfin/serial.c b/cpu/blackfin/serial.c
index 406d9d0..0d6f377 100644
--- a/cpu/blackfin/serial.c
+++ b/cpu/blackfin/serial.c
@@ -35,6 +35,32 @@
#include "serial.h"
+#ifdef CONFIG_DEBUG_SERIAL
+uint16_t cached_lsr[256];
+uint16_t cached_rbr[256];
+size_t cache_count;
+
+/* The LSR is read-to-clear on some parts, so we have to make sure status
+ * bits aren't inadvertently lost when doing various tests.
+ */
+static uint16_t uart_lsr_save;
+static uint16_t uart_lsr_read(void)
+{
+ uint16_t lsr = *pUART_LSR;
+ uart_lsr_save |= (lsr & (OE|PE|FE|BI));
+ return lsr | uart_lsr_save;
+}
+/* Just do the clear for everyone since it can't hurt. */
+static void uart_lsr_clear(void)
+{
+ uart_lsr_save = 0;
+ *pUART_LSR |= -1;
+}
+#else
+static inline uint16_t uart_lsr_read(void) { return *pUART_LSR; }
+static inline void uart_lsr_clear(void) { *pUART_LSR = -1; }
+#endif
+
/* Symbol for our assembly to call. */
void serial_set_baud(uint32_t baud)
{
@@ -61,6 +87,12 @@ int serial_init(void)
{
serial_initialize();
serial_setbrg();
+ uart_lsr_clear();
+#ifdef CONFIG_DEBUG_SERIAL
+ cache_count = 0;
+ memset(cached_lsr, 0x00, sizeof(cached_lsr));
+ memset(cached_rbr, 0x00, sizeof(cached_rbr));
+#endif
return 0;
}
@@ -73,7 +105,7 @@ void serial_putc(const char c)
WATCHDOG_RESET();
/* wait for the hardware fifo to clear up */
- while (!(*pUART_LSR & THRE))
+ while (!(uart_lsr_read() & THRE))
continue;
/* queue the character for transmission */
@@ -83,38 +115,54 @@ void serial_putc(const char c)
WATCHDOG_RESET();
/* wait for the byte to be shifted over the line */
- while (!(*pUART_LSR & TEMT))
+ while (!(uart_lsr_read() & TEMT))
continue;
}
int serial_tstc(void)
{
WATCHDOG_RESET();
- return (*pUART_LSR & DR) ? 1 : 0;
+ return (uart_lsr_read() & DR) ? 1 : 0;
}
int serial_getc(void)
{
- uint16_t uart_lsr_val, uart_rbr_val;
+ uint16_t uart_rbr_val;
/* wait for data ! */
while (!serial_tstc())
continue;
- /* clear the status and grab the new byte */
- uart_lsr_val = *pUART_LSR;
+ /* grab the new byte */
uart_rbr_val = *pUART_RBR;
+#ifdef CONFIG_DEBUG_SERIAL
+ /* grab & clear the LSR */
+ uint16_t uart_lsr_val = uart_lsr_read();
+
+ cached_lsr[cache_count] = uart_lsr_val;
+ cached_rbr[cache_count] = uart_rbr_val;
+ cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
+
if (uart_lsr_val & (OE|PE|FE|BI)) {
- /* Some parts are read-to-clear while others are
- * write-to-clear. Just do the write for everyone
- * since it cant hurt (other than code size).
- */
- *pUART_LSR = (OE|PE|FE|BI);
+ uint16_t dll, dlh;
+ printf("\n[SERIAL ERROR]\n");
+ ACCESS_LATCH();
+ dll = *pUART_DLL;
+ dlh = *pUART_DLH;
+ ACCESS_PORT_IER();
+ printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh);
+ do {
+ --cache_count;
+ printf("\t%3i: RBR=0x%02x LSR=0x%02x\n", cache_count,
+ cached_rbr[cache_count], cached_lsr[cache_count]);
+ } while (cache_count > 0);
return -1;
}
+#endif
+ uart_lsr_clear();
- return uart_rbr_val & 0xFF;
+ return uart_rbr_val;
}
void serial_puts(const char *s)
diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h
index 1f0f4b4..ec40c26 100644
--- a/cpu/blackfin/serial.h
+++ b/cpu/blackfin/serial.h
@@ -175,11 +175,11 @@ static inline uint32_t serial_early_get_baud(void)
__attribute__((always_inline))
static inline void serial_early_set_baud(uint32_t baud)
{
- /* Translate from baud into divisor in terms of SCLK.
- * The +1 is to make sure we over sample just a little
- * rather than under sample the incoming signals.
+ /* Translate from baud into divisor in terms of SCLK. The
+ * weird multiplication is to make sure we over sample just
+ * a little rather than under sample the incoming signals.
*/
- uint16_t divisor = (get_sclk() / (baud * 16)) + 1;
+ uint16_t divisor = (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230;
/* Set DLAB in LCR to Access DLL and DLH */
ACCESS_LATCH();
diff --git a/cpu/blackfin/start.S b/cpu/blackfin/start.S
index 30212e9..9975a0c 100644
--- a/cpu/blackfin/start.S
+++ b/cpu/blackfin/start.S
@@ -1,7 +1,7 @@
/*
* U-boot - start.S Startup file for Blackfin u-boot
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* This file is based on head.S
* Copyright (c) 2003 Metrowerks/Motorola
@@ -49,8 +49,8 @@
ENTRY(_start)
/* Set our initial stack to L1 scratch space */
- sp.l = LO(L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE);
- sp.h = HI(L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE);
+ sp.l = LO(L1_SRAM_SCRATCH_END - 20);
+ sp.h = HI(L1_SRAM_SCRATCH_END - 20);
#ifdef CONFIG_HW_WATCHDOG
# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START
@@ -75,7 +75,7 @@ ENTRY(_start)
serial_early_puts("Init Registers");
- /* Disable nested interrupts and enable CYCLES for udelay() */
+ /* Disable self-nested interrupts and enable CYCLES for udelay() */
R0 = CCEN | 0x30;
SYSCFG = R0;
@@ -145,12 +145,12 @@ ENTRY(_start)
r6 = 0 (x);
p1 = r0;
- p2.l = LO(CFG_MONITOR_BASE);
- p2.h = HI(CFG_MONITOR_BASE);
+ p2.l = LO(CONFIG_SYS_MONITOR_BASE);
+ p2.h = HI(CONFIG_SYS_MONITOR_BASE);
p3 = 0x04;
- p4.l = LO(CFG_MONITOR_BASE + CFG_MONITOR_LEN);
- p4.h = HI(CFG_MONITOR_BASE + CFG_MONITOR_LEN);
+ p4.l = LO(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN);
+ p4.h = HI(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN);
.Lloop1:
r1 = [p1 ++ p3];
[p2 ++ p3] = r1;
@@ -180,7 +180,7 @@ ENTRY(_start)
/* Now lower ourselves from the highest interrupt level to
* the lowest. We do this by masking all interrupts but 15,
- * setting the 15 handler to "board_init_f", raising the 15
+ * setting the 15 handler to ".Lenable_nested", raising the 15
* interrupt, and then returning from the highest interrupt
* level to the dummy "jump" until the interrupt controller
* services the pending 15 interrupt.
@@ -190,20 +190,23 @@ ENTRY(_start)
r1 = r6;
p0.l = LO(EVT15);
p0.h = HI(EVT15);
- p1.l = _cpu_init_f;
- p1.h = _cpu_init_f;
+ p1.l = .Lenable_nested;
+ p1.h = .Lenable_nested;
[p0] = p1;
- p2.l = LO(IMASK);
- p2.h = HI(IMASK);
- p3.l = LO(EVT_IVG15);
- p3.h = HI(EVT_IVG15);
- [p2] = p3;
+ r7 = EVT_IVG15 (z);
+ sti r7;
raise 15;
p4.l = .LWAIT_HERE;
p4.h = .LWAIT_HERE;
reti = p4;
rti;
+ /* Enable nested interrupts before continuing with cpu init */
+.Lenable_nested:
+ cli r7;
+ [--sp] = reti;
+ jump.l _cpu_init_f;
+
.LWAIT_HERE:
jump .LWAIT_HERE;
ENDPROC(_start)
diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c
index 4474fe5..d17c0a1 100644
--- a/cpu/blackfin/traps.c
+++ b/cpu/blackfin/traps.c
@@ -229,26 +229,67 @@ static void decode_address(char *buf, unsigned long address)
if (!address)
sprintf(buf, "<0x%p> /* Maybe null pointer? */", address);
- else if (address >= CFG_MONITOR_BASE &&
- address < CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+ else if (address >= CONFIG_SYS_MONITOR_BASE &&
+ address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
sprintf(buf, "<0x%p> /* somewhere in u-boot */", address);
else
sprintf(buf, "<0x%p> /* unknown address */", address);
}
+static char *strhwerrcause(uint16_t hwerrcause)
+{
+ switch (hwerrcause) {
+ case 0x02: return "system mmr error";
+ case 0x03: return "external memory addressing error";
+ case 0x12: return "performance monitor overflow";
+ case 0x18: return "raise 5 instruction";
+ default: return "undef";
+ }
+}
+
+static char *strexcause(uint16_t excause)
+{
+ switch (excause) {
+ case 0x00 ... 0xf: return "custom exception";
+ case 0x10: return "single step";
+ case 0x11: return "trace buffer full";
+ case 0x21: return "undef inst";
+ case 0x22: return "illegal inst";
+ case 0x23: return "dcplb prot violation";
+ case 0x24: return "misaligned data";
+ case 0x25: return "unrecoverable event";
+ case 0x26: return "dcplb miss";
+ case 0x27: return "multiple dcplb hit";
+ case 0x28: return "emulation watchpoint";
+ case 0x2a: return "misaligned inst";
+ case 0x2b: return "icplb prot violation";
+ case 0x2c: return "icplb miss";
+ case 0x2d: return "multiple icplb hit";
+ case 0x2e: return "illegal use of supervisor resource";
+ default: return "undef";
+ }
+}
+
void dump(struct pt_regs *fp)
{
char buf[150];
size_t i;
+ uint16_t hwerrcause, excause;
if (!ENABLE_DUMP)
return;
+ /* fp->ipend is garbage, so load it ourself */
+ fp->ipend = bfin_read_IPEND();
+
+ hwerrcause = (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P;
+ excause = (fp->seqstat & EXCAUSE) >> EXCAUSE_P;
+
printf("SEQUENCER STATUS:\n");
printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
fp->seqstat, fp->ipend, fp->syscfg);
- printf(" HWERRCAUSE: 0x%lx\n", (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P);
- printf(" EXCAUSE : 0x%lx\n", (fp->seqstat & EXCAUSE) >> EXCAUSE_P);
+ printf(" HWERRCAUSE: 0x%lx: %s\n", hwerrcause, strhwerrcause(hwerrcause));
+ printf(" EXCAUSE : 0x%lx: %s\n", excause, strexcause(excause));
for (i = 6; i <= 15; ++i) {
if (fp->ipend & (1 << i)) {
decode_address(buf, bfin_read32(EVT0 + 4*i));
@@ -263,8 +304,9 @@ void dump(struct pt_regs *fp)
printf(" RETX: %s\n", buf);
decode_address(buf, fp->rets);
printf(" RETS: %s\n", buf);
+ /* we lie and store RETI in "pc" */
decode_address(buf, fp->pc);
- printf(" PC : %s\n", buf);
+ printf(" RETI: %s\n", buf);
if (fp->seqstat & EXCAUSE) {
decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
@@ -344,10 +386,6 @@ void bfin_panic(struct pt_regs *regs)
);
dump(regs);
dump_bfin_trace_buffer();
- printf(
- "\n"
- "Please reset the board\n"
- "\n"
- );
+ puts("\n");
bfin_reset_or_hang();
}
diff --git a/cpu/i386/interrupts.c b/cpu/i386/interrupts.c
index f340119..f6dbcca 100644
--- a/cpu/i386/interrupts.c
+++ b/cpu/i386/interrupts.c
@@ -509,7 +509,7 @@ int disable_interrupts(void)
}
-#ifdef CFG_RESET_GENERIC
+#ifdef CONFIG_SYS_RESET_GENERIC
void __attribute__ ((regparm(0))) generate_gpf(void);
asm(".globl generate_gpf\n"
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 640b255..cb6bc03 100644
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -32,7 +32,7 @@
#include <config.h>
#include <pci.h>
#ifdef CONFIG_SC520_SSI
-#include <ssi.h>
+#include <asm/ic/ssi.h>
#endif
#include <asm/io.h>
#include <asm/pci.h>
@@ -113,7 +113,7 @@ void init_sc520(void)
write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */
- if (CFG_SC520_HIGH_SPEED) {
+ if (CONFIG_SYS_SC520_HIGH_SPEED) {
write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */
gd->cpu_clk = 133000000;
printf("## CPU Speed set to 133MHz\n");
@@ -145,7 +145,7 @@ unsigned long init_sc520_dram(void)
u32 dram_present=0;
u32 dram_ctrl;
-#ifdef CFG_SDRAM_DRCTMCTL
+#ifdef CONFIG_SYS_SDRAM_DRCTMCTL
/* these memory control registers are set up in the assember part,
* in sc520_asm.S, during 'mem_init'. If we muck with them here,
* after we are running a stack in RAM, we have troubles. Besides,
@@ -156,9 +156,9 @@ unsigned long init_sc520_dram(void)
#else
int val;
- int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
- int refresh_rate = CFG_SDRAM_REFRESH_RATE;
- int ras_cas_delay = CFG_SDRAM_RAS_CAS_DELAY;
+ int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
+ int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE;
+ int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY;
/* set SDRAM speed here */
@@ -393,7 +393,7 @@ void pci_sc520_init(struct pci_controller *hose)
#endif
-#ifdef CFG_TIMER_SC520
+#ifdef CONFIG_SYS_TIMER_SC520
void reset_timer(void)
diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S
index 34322ea..59ed2b8 100644
--- a/cpu/i386/sc520_asm.S
+++ b/cpu/i386/sc520_asm.S
@@ -460,21 +460,21 @@ emptybank:
incl %edi
loop cleanuplp
-#if defined CFG_SDRAM_DRCTMCTL
+#if defined CONFIG_SYS_SDRAM_DRCTMCTL
/* just have your hardware desinger _GIVE_ you what you need here! */
movl $DRCTMCTL, %edi
- movb $CFG_SDRAM_DRCTMCTL,%al
+ movb $CONFIG_SYS_SDRAM_DRCTMCTL,%al
movb (%edi), %al
#else
-#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T)
+#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
/* set the CAS latency now since it is hard to do
* when we run from the RAM */
movl $DRCTMCTL, %edi /* DRAM timing register */
movb (%edi), %al
-#ifdef CFG_SDRAM_CAS_LATENCY_2T
+#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
andb $0xef, %al
#endif
-#ifdef CFG_SDRAM_CAS_LATENCY_3T
+#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
orb $0x10, %al
#endif
movb %al, (%edi)
@@ -540,7 +540,7 @@ bank0: movl (%edi), %eax
done:
movl %ebx, %eax
-#if CFG_SDRAM_ECC_ENABLE
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
/* A nominal memory test: just a byte at each address line */
movl %eax, %ecx
shrl $0x1, %ecx
diff --git a/cpu/i386/start.S b/cpu/i386/start.S
index 264ac09..b6175b1 100644
--- a/cpu/i386/start.S
+++ b/cpu/i386/start.S
@@ -55,7 +55,7 @@ early_board_init_ret:
/* so we try to indicate progress */
movw $0x01, %ax
movl $.progress0, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress0:
/* size memory */
@@ -67,14 +67,14 @@ mem_init_ret:
* (we need atleast bss start+bss size+stack size) */
movl $_i386boot_bss_start, %ecx /* BSS start */
addl $_i386boot_bss_size, %ecx /* BSS size */
- addl $CFG_STACK_SIZE, %ecx
+ addl $CONFIG_SYS_STACK_SIZE, %ecx
cmpl %ecx, %eax
jae mem_ok
/* indicate (lack of) progress */
movw $0x81, %ax
movl $.progress0a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress0a:
jmp die
mem_ok:
@@ -82,13 +82,13 @@ mem_ok:
/* indicate progress */
movw $0x02, %ax
movl $.progress1, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress1:
/* create a stack after the bss */
movl $_i386boot_bss_start, %eax
addl $_i386boot_bss_size, %eax
- addl $CFG_STACK_SIZE, %eax
+ addl $CONFIG_SYS_STACK_SIZE, %eax
movl %eax, %esp
pushl $0
@@ -104,7 +104,7 @@ no_stack:
/* indicate (lack of) progress */
movw $0x82, %ax
movl $.progress1a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress1a:
jmp die
@@ -113,7 +113,7 @@ stack_ok:
/* indicate progress */
movw $0x03, %ax
movl $.progress2, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress2:
/* copy data section to ram, size must be 4-byte aligned */
@@ -136,7 +136,7 @@ data_fail:
/* indicate (lack of) progress */
movw $0x83, %ax
movl $.progress2a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress2a:
jmp die
@@ -145,7 +145,7 @@ data_ok:
/* indicate progress */
movw $0x04, %ax
movl $.progress3, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress3:
/* clear bss section in ram, size must be 4-byte aligned */
@@ -168,7 +168,7 @@ bss_fail:
/* indicate (lack of) progress */
movw $0x84, %ax
movl $.progress3a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress3a:
jmp die
@@ -180,7 +180,7 @@ bss_ok:
/* indicate progress */
movw $0x05, %ax
movl $.progress4, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress4:
call start_i386boot /* Enter, U-boot! */
@@ -188,7 +188,7 @@ bss_ok:
/* indicate (lack of) progress */
movw $0x85, %ax
movl $.progress4a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress4a:
die: hlt
diff --git a/cpu/i386/timer.c b/cpu/i386/timer.c
index 486d927..46db23f 100644
--- a/cpu/i386/timer.c
+++ b/cpu/i386/timer.c
@@ -72,9 +72,9 @@ int timer_init(void)
}
-#ifdef CFG_TIMER_GENERIC
+#ifdef CONFIG_SYS_TIMER_GENERIC
-/* the unit for these is CFG_HZ */
+/* the unit for these is CONFIG_SYS_HZ */
/* FixMe: implement these */
void reset_timer (void)
diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c
index 2c7d5a0..27872fb 100644
--- a/cpu/ixp/cpu.c
+++ b/cpu/ixp/cpu.c
@@ -32,6 +32,7 @@
#include <common.h>
#include <command.h>
+#include <netdev.h>
#include <asm/arch/ixp425.h>
ulong loops_per_jiffy;
@@ -81,7 +82,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
@@ -198,7 +199,7 @@ void pci_init(void)
void bootcount_store (ulong a)
{
- volatile ulong *save_addr = (volatile ulong *)(CFG_BOOTCOUNT_ADDR);
+ volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR);
save_addr[0] = a;
save_addr[1] = BOOTCOUNT_MAGIC;
@@ -206,7 +207,7 @@ void bootcount_store (ulong a)
ulong bootcount_load (void)
{
- volatile ulong *save_addr = (volatile ulong *)(CFG_BOOTCOUNT_ADDR);
+ volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR);
if (save_addr[1] != BOOTCOUNT_MAGIC)
return 0;
@@ -215,3 +216,11 @@ ulong bootcount_load (void)
}
#endif /* CONFIG_BOOTCOUNT_LIMIT */
+
+int cpu_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_IXP4XX_NPE
+ npe_initialize(bis);
+#endif
+ return 0;
+}
diff --git a/cpu/ixp/interrupts.c b/cpu/ixp/interrupts.c
index 84fe937..621f31b 100644
--- a/cpu/ixp/interrupts.c
+++ b/cpu/ixp/interrupts.c
@@ -40,8 +40,8 @@
*/
#define FREQ 66666666
-#define CLOCK_TICK_RATE (((FREQ / CFG_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CFG_HZ)
-#define LATCH ((CLOCK_TICK_RATE + CFG_HZ/2) / CFG_HZ) /* For divider */
+#define CLOCK_TICK_RATE (((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ)
+#define LATCH ((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ) /* For divider */
struct _irq_handler {
void *m_data;
diff --git a/cpu/ixp/npe/include/IxEthDB_p.h b/cpu/ixp/npe/include/IxEthDB_p.h
index e7c67ae..ccec7ea 100644
--- a/cpu/ixp/npe/include/IxEthDB_p.h
+++ b/cpu/ixp/npe/include/IxEthDB_p.h
@@ -193,8 +193,6 @@ extern int overflowEvent;
#define LEFT (-1)
/* macros */
-#define MIN(a, b) ((a) < (b) ? (a) : (b))
-
#define IX_ETH_DB_CHECK_PORT_EXISTS(portID) \
{ \
if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
diff --git a/cpu/ixp/npe/include/npe.h b/cpu/ixp/npe/include/npe.h
index e53458d..3d6f727 100644
--- a/cpu/ixp/npe/include/npe.h
+++ b/cpu/ixp/npe/include/npe.h
@@ -27,10 +27,10 @@
/*
* defines...
*/
-#define CFG_NPE_NUMS 1
+#define CONFIG_SYS_NPE_NUMS 1
#ifdef CONFIG_HAS_ETH1
-#undef CFG_NPE_NUMS
-#define CFG_NPE_NUMS 2
+#undef CONFIG_SYS_NPE_NUMS
+#define CONFIG_SYS_NPE_NUMS 2
#endif
#define NPE_NUM_PORTS 3
diff --git a/cpu/ixp/npe/miiphy.c b/cpu/ixp/npe/miiphy.c
index c63c54e..20fee2d 100644
--- a/cpu/ixp/npe/miiphy.c
+++ b/cpu/ixp/npe/miiphy.c
@@ -32,7 +32,7 @@
| Date Description of Change BY
| --------- --------------------- ---
| 05-May-99 Created MKW
- | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
+ | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to
| better match OPB speed. Also modified delay times. JWB
| 29-Jul-99 Added Full duplex support MKW
| 24-Aug-99 Removed printf from dp83843_duplex() JWB
diff --git a/cpu/ixp/npe/npe.c b/cpu/ixp/npe/npe.c
index 892096b..bd77fed 100644
--- a/cpu/ixp/npe/npe.c
+++ b/cpu/ixp/npe/npe.c
@@ -51,7 +51,7 @@ static int npe_exists[NPE_NUM_PORTS];
static int npe_used[NPE_NUM_PORTS];
/* A little extra so we can align to cacheline. */
-static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CFG_CACHELINE_SIZE - 1];
+static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CONFIG_SYS_CACHELINE_SIZE - 1];
static u8 *npe_alloc_end;
static u8 *npe_alloc_free;
@@ -60,7 +60,7 @@ static void *npe_alloc(int size)
static int count = 0;
void *p = NULL;
- size = (size + (CFG_CACHELINE_SIZE-1)) & ~(CFG_CACHELINE_SIZE-1);
+ size = (size + (CONFIG_SYS_CACHELINE_SIZE-1)) & ~(CONFIG_SYS_CACHELINE_SIZE-1);
count++;
if ((npe_alloc_free + size) < npe_alloc_end) {
@@ -399,7 +399,7 @@ static int npe_init(struct eth_device *dev, bd_t * bis)
npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
- CFG_CACHELINE_SIZE - 1) & ~(CFG_CACHELINE_SIZE - 1));
+ CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
/* initialize mbuf pool */
init_rx_mbufs(p_npe);
@@ -568,7 +568,7 @@ int npe_initialize(bd_t * bis)
int eth_num = 0;
struct npe *p_npe = NULL;
- for (eth_num = 0; eth_num < CFG_NPE_NUMS; eth_num++) {
+ for (eth_num = 0; eth_num < CONFIG_SYS_NPE_NUMS; eth_num++) {
/* See if we can actually bring up the interface, otherwise, skip it */
switch (eth_num) {
@@ -673,8 +673,8 @@ int npe_initialize(bd_t * bis)
npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
- CFG_CACHELINE_SIZE - 1)
- & ~(CFG_CACHELINE_SIZE - 1));
+ CONFIG_SYS_CACHELINE_SIZE - 1)
+ & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
if (!npe_csr_load())
return 0;
diff --git a/cpu/ixp/serial.c b/cpu/ixp/serial.c
index 4549631..dd26af4 100644
--- a/cpu/ixp/serial.c
+++ b/cpu/ixp/serial.c
@@ -43,7 +43,7 @@ DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg (void)
{
unsigned int quot = 0;
- int uart = CFG_IXP425_CONSOLE;
+ int uart = CONFIG_SYS_IXP425_CONSOLE;
if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0))
quot = SERIAL_CLOCK / gd->baudrate;
@@ -85,9 +85,9 @@ int serial_init (void)
void serial_putc (const char c)
{
/* wait for room in the tx FIFO on UART */
- while ((LSR(CFG_IXP425_CONSOLE) & LSR_TEMT) == 0);
+ while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0);
- THR(CFG_IXP425_CONSOLE) = c;
+ THR(CONFIG_SYS_IXP425_CONSOLE) = c;
/* If \n, also do \r */
if (c == '\n')
@@ -101,7 +101,7 @@ void serial_putc (const char c)
*/
int serial_tstc (void)
{
- return LSR(CFG_IXP425_CONSOLE) & LSR_DR;
+ return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR;
}
/*
@@ -111,9 +111,9 @@ int serial_tstc (void)
*/
int serial_getc (void)
{
- while (!(LSR(CFG_IXP425_CONSOLE) & LSR_DR));
+ while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR));
- return (char) RBR(CFG_IXP425_CONSOLE) & 0xff;
+ return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff;
}
void
diff --git a/cpu/ixp/start.S b/cpu/ixp/start.S
index d4c8e33..196ba5d 100644
--- a/cpu/ixp/start.S
+++ b/cpu/ixp/start.S
@@ -154,7 +154,7 @@ reset:
CPWAIT r0
/* set EXP CS0 to the optimum timing */
- ldr r1, =CFG_EXP_CS0
+ ldr r1, =CONFIG_SYS_EXP_CS0
ldr r2, =IXP425_EXP_CS0
str r1, [r2]
@@ -165,7 +165,7 @@ reset:
orr r1, r1, #0x80000000
str r1, [r2]
#endif
- mov r1, #CFG_SDR_CONFIG
+ mov r1, #CONFIG_SYS_SDR_CONFIG
ldr r2, =IXP425_SDR_CONFIG
str r1, [r2]
@@ -181,7 +181,7 @@ reset:
DELAY_FOR 0x4000, r0
/* set SDRAM internal refresh val */
- ldr r1, =CFG_SDRAM_REFRESH_CNT
+ ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
str r1, [r3]
DELAY_FOR 0x4000, r0
@@ -199,7 +199,7 @@ reset:
bne 111b
/* set mode register in sdram */
- mov r1, #CFG_SDR_MODE_CONFIG
+ mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
str r1, [r4]
DELAY_FOR 0x4000, r0
@@ -211,7 +211,7 @@ reset:
/* copy */
mov r0, #0
mov r4, r0
- add r2, r0, #CFG_MONITOR_LEN
+ add r2, r0, #CONFIG_SYS_MONITOR_LEN
mov r1, #0x10000000
mov r5, r1
@@ -283,8 +283,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -345,8 +345,8 @@ _start_armboot: .word start_armboot
add r8, sp, #S_PC
ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
@@ -382,8 +382,8 @@ _start_armboot: .word start_armboot
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
diff --git a/cpu/ixp/timer.c b/cpu/ixp/timer.c
index 920f34e..09d8ad5 100644
--- a/cpu/ixp/timer.c
+++ b/cpu/ixp/timer.c
@@ -44,7 +44,7 @@ void ixp425_udelay(unsigned long usec)
* This function has a max usec, but since it is called from udelay
* we should not have to worry... be happy
*/
- unsigned long usecs = CFG_HZ/1000000L & ~IXP425_OST_RELOAD_MASK;
+ unsigned long usecs = CONFIG_SYS_HZ/1000000L & ~IXP425_OST_RELOAD_MASK;
*IXP425_OSST = IXP425_OSST_TIMER_1_PEND;
usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE;
diff --git a/cpu/leon2/cpu.c b/cpu/leon2/cpu.c
index 5de1c52..d6e23b1 100644
--- a/cpu/leon2/cpu.c
+++ b/cpu/leon2/cpu.c
@@ -25,6 +25,7 @@
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -57,8 +58,6 @@ int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
/* ------------------------------------------------------------------------- */
-extern int greth_initialize(bd_t *bis);
-
#ifdef CONFIG_GRETH
int cpu_eth_init(bd_t *bis)
{
diff --git a/cpu/leon2/interrupts.c b/cpu/leon2/interrupts.c
index 35b375c..9b0da96 100644
--- a/cpu/leon2/interrupts.c
+++ b/cpu/leon2/interrupts.c
@@ -98,8 +98,8 @@ static void leon2_ic_enable(unsigned int irq)
void handler_irq(int irq, struct pt_regs *regs)
{
if (irq_handlers[irq].handler) {
- if (((unsigned int)irq_handlers[irq].handler > CFG_RAM_END) ||
- ((unsigned int)irq_handlers[irq].handler < CFG_RAM_BASE)
+ if (((unsigned int)irq_handlers[irq].handler > CONFIG_SYS_RAM_END) ||
+ ((unsigned int)irq_handlers[irq].handler < CONFIG_SYS_RAM_BASE)
) {
printf("handler_irq: bad handler: %x, irq number %d\n",
(unsigned int)irq_handlers[irq].handler, irq);
@@ -163,8 +163,8 @@ void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
(ulong) handler, (ulong) irq_handlers[irq].handler);
- if (((unsigned int)handler > CFG_RAM_END) ||
- ((unsigned int)handler < CFG_RAM_BASE)
+ if (((unsigned int)handler > CONFIG_SYS_RAM_END) ||
+ ((unsigned int)handler < CONFIG_SYS_RAM_BASE)
) {
printf("irq_install_handler: bad handler: %x, irq number %d\n",
(unsigned int)handler, irq);
diff --git a/cpu/leon2/prom.c b/cpu/leon2/prom.c
index b031995..1a6c7f7 100644
--- a/cpu/leon2/prom.c
+++ b/cpu/leon2/prom.c
@@ -45,14 +45,14 @@ extern struct linux_romvec *kernel_arg_promvec;
/* for __va */
extern int __prom_start;
#define PAGE_OFFSET 0xf0000000
-#define phys_base CFG_SDRAM_BASE
+#define phys_base CONFIG_SYS_SDRAM_BASE
#define PROM_OFFS 8192
#define PROM_SIZE_MASK (PROM_OFFS-1)
#define __va(x) ( \
(void *)( ((unsigned long)(x))-PROM_OFFS+ \
- (CFG_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \
+ (CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \
)
-#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CFG_PROM_OFFSET-TEXT_BASE))
+#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-TEXT_BASE))
struct property {
char *name;
@@ -540,13 +540,13 @@ static struct leon_prom_info PROM_DATA spi = {
__va(&spi.totphys),
{
NULL,
- (char *)CFG_SDRAM_BASE,
+ (char *)CONFIG_SYS_SDRAM_BASE,
0,
},
__va(&spi.avail),
{
NULL,
- (char *)CFG_SDRAM_BASE,
+ (char *)CONFIG_SYS_SDRAM_BASE,
0,
},
NULL, /* prommap_p */
@@ -654,7 +654,7 @@ static void PROM_TEXT leon_reboot(char *bcommand)
/* get physical address */
struct leon_prom_info *pspi =
- (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
unsigned int *srmmu_ctx_table;
@@ -707,7 +707,7 @@ static void PROM_TEXT leon_reboot_physical(char *bcommand)
srmmu_set_mmureg(0);
/* Hardcoded start address */
- reset = CFG_MONITOR_BASE;
+ reset = CONFIG_SYS_MONITOR_BASE;
/* flush data cache */
sparc_dcache_flush_all();
@@ -762,7 +762,7 @@ static int PROM_TEXT no_nextnode(int node)
{
/* get physical address */
struct leon_prom_info *pspi =
- (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -777,7 +777,7 @@ static int PROM_TEXT no_child(int node)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -792,7 +792,7 @@ static struct property PROM_TEXT *find_property(int node, char *name)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -811,7 +811,7 @@ static int PROM_TEXT no_proplen(int node, char *name)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -827,7 +827,7 @@ static int PROM_TEXT no_getprop(int node, char *name, char *value)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -850,7 +850,7 @@ static char PROM_TEXT *no_nextprop(int node, char *name)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
struct property *prop;
/* convert into virtual address */
@@ -906,7 +906,7 @@ void leon_prom_init(struct leon_prom_info *pspi)
pspi->freq_khz = CONFIG_SYS_CLK_FREQ / 1000;
/* Set Available main memory size */
- pspi->totphys.num_bytes = CFG_PROM_OFFSET - CFG_SDRAM_BASE;
+ pspi->totphys.num_bytes = CONFIG_SYS_PROM_OFFSET - CONFIG_SYS_SDRAM_BASE;
pspi->avail.num_bytes = pspi->totphys.num_bytes;
#undef nodes
@@ -951,7 +951,7 @@ extern unsigned short bss_start, bss_end;
int prom_init(void)
{
struct leon_prom_info *pspi = (void *)
- ((((unsigned int)&spi) & PROM_SIZE_MASK) + CFG_PROM_OFFSET);
+ ((((unsigned int)&spi) & PROM_SIZE_MASK) + CONFIG_SYS_PROM_OFFSET);
/* disable mmu */
srmmu_set_mmureg(0x00000000);
@@ -977,7 +977,7 @@ void prepare_bootargs(char *bootargs)
/* if no bootargs set, skip copying ==> default bootline */
if (bootargs && (*bootargs != '\0')) {
pspi = (void *)((((unsigned int)&spi) & PROM_SIZE_MASK) +
- CFG_PROM_OFFSET);
+ CONFIG_SYS_PROM_OFFSET);
src = bootargs;
dst = &pspi->arg[0];
left = 255; /* max len */
@@ -994,7 +994,7 @@ void srmmu_init_cpu(unsigned int entry)
{
sparc_srmmu_setup *psrmmu_tables = (void *)
((((unsigned int)&srmmu_tables) & PROM_SIZE_MASK) +
- CFG_PROM_OFFSET);
+ CONFIG_SYS_PROM_OFFSET);
/* Make context 0 (kernel's context) point
* to our prepared memory mapping
@@ -1010,21 +1010,21 @@ void srmmu_init_cpu(unsigned int entry)
#define PTE 2
#define ACC_SU_ALL 0x1c
psrmmu_tables->pgd_table[0xf0] =
- (CFG_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE;
+ (CONFIG_SYS_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf1] =
- ((CFG_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf2] =
- ((CFG_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf3] =
- ((CFG_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf4] =
- ((CFG_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf5] =
- ((CFG_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf6] =
- ((CFG_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf7] =
- ((CFG_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE;
/* convert rom vec pointer to virtual address */
kernel_arg_promvec = (struct linux_romvec *)
diff --git a/cpu/leon2/serial.c b/cpu/leon2/serial.c
index ce9457f..4f41b8e 100644
--- a/cpu/leon2/serial.c
+++ b/cpu/leon2/serial.c
@@ -57,7 +57,7 @@ int serial_init(void)
regs = (LEON2_Uart_regs *) & leon2->UART_Channel_2;
#endif
- regs->UART_Scaler = CFG_LEON2_UART1_SCALER;
+ regs->UART_Scaler = CONFIG_SYS_LEON2_UART1_SCALER;
/* Let bit 11 be unchanged (debug bit for GRMON) */
tmp = READ_WORD(regs->UART_Control);
diff --git a/cpu/leon2/start.S b/cpu/leon2/start.S
index f23f499..b1f1eb5 100644
--- a/cpu/leon2/start.S
+++ b/cpu/leon2/start.S
@@ -27,6 +27,7 @@
#include <asm/psr.h>
#include <asm/stack.h>
#include <asm/leon.h>
+#include <timestamp.h>
#include <version.h>
/* Entry for traps which jump to a programmer-specified trap handler. */
@@ -68,7 +69,7 @@ ARGPUSH = (WINDOWSIZE + 4)
MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
/* Number of register windows */
-#ifndef CFG_SPARC_NWINDOWS
+#ifndef CONFIG_SYS_SPARC_NWINDOWS
#error Must define number of SPARC register windows, default is 8
#endif
@@ -199,7 +200,7 @@ _trap_table:
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
.section ".text"
@@ -280,16 +281,16 @@ leon2_init_ioport:
leon2_init_mctrl:
/* memory config register 1 */
- set CFG_GRLIB_MEMCFG1, %g2
+ set CONFIG_SYS_GRLIB_MEMCFG1, %g2
ld [%g1], %g3 !
and %g3, 0x300, %g3
or %g2, %g3, %g2
st %g2, [%g1 + LEON2_MCFG1]
- set CFG_GRLIB_MEMCFG2, %g2 ! Load memory config register 2
+ set CONFIG_SYS_GRLIB_MEMCFG2, %g2 ! Load memory config register 2
#if !( defined(TSIM) || !defined(BZIMAGE))
st %g2, [%g1 + LEON2_MCFG2] ! only for prom version, else done by "dumon -i"
#endif
- set CFG_GRLIB_MEMCFG3, %g2 ! Init FT register
+ set CONFIG_SYS_GRLIB_MEMCFG3, %g2 ! Init FT register
st %g2, [%g1 + LEON2_ECTRL]
ld [%g1 + LEON2_ECTRL], %g2
srl %g2, 30, %g2
@@ -310,7 +311,7 @@ leon2_init_psr:
nop
leon2_init_stackp:
- set CFG_INIT_SP_OFFSET, %fp
+ set CONFIG_SYS_INIT_SP_OFFSET, %fp
andn %fp, 0x0f, %fp
sub %fp, 64, %sp
@@ -327,7 +328,7 @@ cpu_init_unreloc:
reloc:
set TEXT_START,%g2
set DATA_END,%g3
- set CFG_RELOC_MONITOR_BASE,%g4
+ set CONFIG_SYS_RELOC_MONITOR_BASE,%g4
reloc_loop:
ldd [%g2],%l0
ldd [%g2+8],%l2
@@ -373,10 +374,10 @@ fixup_got:
set __got_end,%g3
/*
* new got offset = (old GOT-PTR (read with ld) -
- * CFG_RELOC_MONITOR_BASE(from define) ) +
+ * CONFIG_SYS_RELOC_MONITOR_BASE(from define) ) +
* Destination Address (from define)
*/
- set CFG_RELOC_MONITOR_BASE,%g2
+ set CONFIG_SYS_RELOC_MONITOR_BASE,%g2
set TEXT_START, %g1
add %g4,%g2,%g4
sub %g4,%g1,%g4
@@ -397,7 +398,7 @@ got_loop:
prom_relocate:
set __prom_start, %g2
set __prom_end, %g3
- set CFG_PROM_OFFSET, %g4
+ set CONFIG_SYS_PROM_OFFSET, %g4
prom_relocate_loop:
ldd [%g2],%l0
@@ -413,7 +414,7 @@ prom_relocate_loop:
* the new trap table address
*/
- set CFG_RELOC_MONITOR_BASE, %g2
+ set CONFIG_SYS_RELOC_MONITOR_BASE, %g2
wr %g0, %g2, %tbr
/* call relocate*/
@@ -421,14 +422,14 @@ prom_relocate_loop:
/* Call relocated init functions */
jump:
set cpu_init_f2,%o1
- set CFG_RELOC_MONITOR_BASE,%o2
+ set CONFIG_SYS_RELOC_MONITOR_BASE,%o2
add %o1,%o2,%o1
sub %o1,%g1,%o1
call %o1
clr %o0
set board_init_f,%o1
- set CFG_RELOC_MONITOR_BASE,%o2
+ set CONFIG_SYS_RELOC_MONITOR_BASE,%o2
add %o1,%o2,%o1
sub %o1,%g1,%o1
call %o1
@@ -454,7 +455,7 @@ _irq_entry:
WRITE_PAUSE
mov %l7, %o0 ! irq level
set handler_irq, %o1
- set (CFG_RELOC_MONITOR_BASE-TEXT_BASE), %o2
+ set (CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE), %o2
add %o1, %o2, %o1
call %o1
add %sp, SF_REGS_SZ, %o1 ! pt_regs ptr
@@ -472,7 +473,7 @@ _window_overflow:
mov %wim, %l3 ! Calculate next WIM
mov %g1, %l7
srl %l3, 1, %g1
- sll %l3, (CFG_SPARC_NWINDOWS-1) , %l4
+ sll %l3, (CONFIG_SYS_SPARC_NWINDOWS-1) , %l4
or %l4, %g1, %g1
save ! Get into window to be saved.
@@ -509,7 +510,7 @@ _window_underflow:
mov %wim, %l3 ! Calculate next WIM
sll %l3, 1, %l4
- srl %l3, (CFG_SPARC_NWINDOWS-1), %l5
+ srl %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l5
or %l5, %l4, %l5
mov %l5, %wim
nop; nop; nop
@@ -578,7 +579,7 @@ trap_setup:
*/
srl %t_wim, 0x1, %g2 ! begin computation of new %wim
- set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
+ set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
sll %t_wim, %g3, %t_wim ! NWINDOWS-1
or %t_wim, %g2, %g2
@@ -612,7 +613,7 @@ ret_trap_entry:
mov 2, %g1
sll %g1, %t_psr, %g1
- set CFG_SPARC_NWINDOWS, %g2 !NWINDOWS
+ set CONFIG_SYS_SPARC_NWINDOWS, %g2 !NWINDOWS
srl %g1, %g2, %g2
or %g1, %g2, %g1
@@ -622,7 +623,7 @@ ret_trap_entry:
sll %g2, 0x1, %g1
/* We have to grab a window before returning. */
- set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
+ set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
srl %g2, %g3, %g2
or %g1, %g2, %g1
diff --git a/cpu/leon3/cpu.c b/cpu/leon3/cpu.c
index 1725fdb..976f311 100644
--- a/cpu/leon3/cpu.c
+++ b/cpu/leon3/cpu.c
@@ -25,6 +25,7 @@
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
@@ -65,7 +66,6 @@ u64 flash_read64(void *addr)
}
/* ------------------------------------------------------------------------- */
-extern int greth_initialize(bd_t *bis);
#ifdef CONFIG_GRETH
int cpu_eth_init(bd_t *bis)
diff --git a/cpu/leon3/cpu_init.c b/cpu/leon3/cpu_init.c
index 4fe7d4b..be22ec2 100644
--- a/cpu/leon3/cpu_init.c
+++ b/cpu/leon3/cpu_init.c
@@ -159,9 +159,9 @@ int init_memory_ctrl()
mctrl = (ambapp_dev_mctrl *) base;
/* config MCTRL memory controller */
- mctrl->mcfg1 = CFG_GRLIB_MEMCFG1 | (mctrl->mcfg1 & 0x300);
- mctrl->mcfg2 = CFG_GRLIB_MEMCFG2;
- mctrl->mcfg3 = CFG_GRLIB_MEMCFG3;
+ mctrl->mcfg1 = CONFIG_SYS_GRLIB_MEMCFG1 | (mctrl->mcfg1 & 0x300);
+ mctrl->mcfg2 = CONFIG_SYS_GRLIB_MEMCFG2;
+ mctrl->mcfg3 = CONFIG_SYS_GRLIB_MEMCFG3;
not_found_mctrl = 0;
}
@@ -171,9 +171,9 @@ int init_memory_ctrl()
mctrl = (ambapp_dev_mctrl *) base;
/* config MCTRL memory controller */
- mctrl->mcfg1 = CFG_GRLIB_FT_MEMCFG1 | (mctrl->mcfg1 & 0x300);
- mctrl->mcfg2 = CFG_GRLIB_FT_MEMCFG2;
- mctrl->mcfg3 = CFG_GRLIB_FT_MEMCFG3;
+ mctrl->mcfg1 = CONFIG_SYS_GRLIB_FT_MEMCFG1 | (mctrl->mcfg1 & 0x300);
+ mctrl->mcfg2 = CONFIG_SYS_GRLIB_FT_MEMCFG2;
+ mctrl->mcfg3 = CONFIG_SYS_GRLIB_FT_MEMCFG3;
not_found_mctrl = 0;
}
@@ -183,7 +183,7 @@ int init_memory_ctrl()
sdctrl = (ambapp_dev_sdctrl *) base;
/* config memory controller */
- sdctrl->sdcfg = CFG_GRLIB_SDRAM;
+ sdctrl->sdcfg = CONFIG_SYS_GRLIB_SDRAM;
not_found_mctrl = 0;
}
@@ -192,8 +192,8 @@ int init_memory_ctrl()
ddr2spa = (ambapp_dev_ddr2spa *) ambapp_ahb_get_info(ahb, 1);
/* Config DDR2 memory controller */
- ddr2spa->cfg1 = CFG_GRLIB_DDR2_CFG1;
- ddr2spa->cfg3 = CFG_GRLIB_DDR2_CFG3;
+ ddr2spa->cfg1 = CONFIG_SYS_GRLIB_DDR2_CFG1;
+ ddr2spa->cfg3 = CONFIG_SYS_GRLIB_DDR2_CFG3;
not_found_mctrl = 0;
}
@@ -202,7 +202,7 @@ int init_memory_ctrl()
ddrspa = (ambapp_dev_ddrspa *) ambapp_ahb_get_info(ahb, 1);
/* Config DDR memory controller */
- ddrspa->ctrl = CFG_GRLIB_DDR_CFG;
+ ddrspa->ctrl = CONFIG_SYS_GRLIB_DDR_CFG;
not_found_mctrl = 0;
}
diff --git a/cpu/leon3/interrupts.c b/cpu/leon3/interrupts.c
index 2692632..ac6aca5 100644
--- a/cpu/leon3/interrupts.c
+++ b/cpu/leon3/interrupts.c
@@ -104,8 +104,8 @@ static void leon3_ic_enable(unsigned int irq)
void handler_irq(int irq, struct pt_regs *regs)
{
if (irq_handlers[irq].handler) {
- if (((unsigned int)irq_handlers[irq].handler > CFG_RAM_END) ||
- ((unsigned int)irq_handlers[irq].handler < CFG_RAM_BASE)
+ if (((unsigned int)irq_handlers[irq].handler > CONFIG_SYS_RAM_END) ||
+ ((unsigned int)irq_handlers[irq].handler < CONFIG_SYS_RAM_BASE)
) {
printf("handler_irq: bad handler: %x, irq number %d\n",
(unsigned int)irq_handlers[irq].handler, irq);
@@ -165,8 +165,8 @@ void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
(ulong) handler, (ulong) irq_handlers[irq].handler);
- if (((unsigned int)handler > CFG_RAM_END) ||
- ((unsigned int)handler < CFG_RAM_BASE)
+ if (((unsigned int)handler > CONFIG_SYS_RAM_END) ||
+ ((unsigned int)handler < CONFIG_SYS_RAM_BASE)
) {
printf("irq_install_handler: bad handler: %x, irq number %d\n",
(unsigned int)handler, irq);
diff --git a/cpu/leon3/prom.c b/cpu/leon3/prom.c
index 9fa2d04..18d2fb2 100644
--- a/cpu/leon3/prom.c
+++ b/cpu/leon3/prom.c
@@ -49,14 +49,14 @@ ambapp_dev_gptimer *gptimer;
/* for __va */
extern int __prom_start;
#define PAGE_OFFSET 0xf0000000
-#define phys_base CFG_SDRAM_BASE
+#define phys_base CONFIG_SYS_SDRAM_BASE
#define PROM_OFFS 8192
#define PROM_SIZE_MASK (PROM_OFFS-1)
#define __va(x) ( \
(void *)( ((unsigned long)(x))-PROM_OFFS+ \
- (CFG_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \
+ (CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \
)
-#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CFG_PROM_OFFSET-TEXT_BASE))
+#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-TEXT_BASE))
struct property {
char *name;
@@ -545,13 +545,13 @@ static struct leon_prom_info PROM_DATA spi = {
__va(&spi.totphys),
{
NULL,
- (char *)CFG_SDRAM_BASE,
+ (char *)CONFIG_SYS_SDRAM_BASE,
0,
},
__va(&spi.avail),
{
NULL,
- (char *)CFG_SDRAM_BASE,
+ (char *)CONFIG_SYS_SDRAM_BASE,
0,
},
NULL, /* prommap_p */
@@ -659,7 +659,7 @@ static void PROM_TEXT leon_reboot(char *bcommand)
/* get physical address */
struct leon_prom_info *pspi =
- (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
unsigned int *srmmu_ctx_table;
@@ -712,7 +712,7 @@ static void PROM_TEXT leon_reboot_physical(char *bcommand)
srmmu_set_mmureg(0);
/* Hardcoded start address */
- reset = CFG_MONITOR_BASE;
+ reset = CONFIG_SYS_MONITOR_BASE;
/* flush data cache */
sparc_dcache_flush_all();
@@ -742,7 +742,7 @@ static int PROM_TEXT leon_nbputchar(int c)
/* get physical address */
struct leon_prom_info *pspi =
- (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
uart = (ambapp_dev_apbuart *)
SPARC_BYPASS_READ(&pspi->reloc_funcs.leon3_apbuart);
@@ -778,7 +778,7 @@ static int PROM_TEXT no_nextnode(int node)
{
/* get physical address */
struct leon_prom_info *pspi =
- (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -793,7 +793,7 @@ static int PROM_TEXT no_child(int node)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -808,7 +808,7 @@ static struct property PROM_TEXT *find_property(int node, char *name)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -827,7 +827,7 @@ static int PROM_TEXT no_proplen(int node, char *name)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -843,7 +843,7 @@ static int PROM_TEXT no_getprop(int node, char *name, char *value)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -866,7 +866,7 @@ static char PROM_TEXT *no_nextprop(int node, char *name)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CFG_PROM_OFFSET + sizeof(srmmu_tables));
+ (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
struct property *prop;
/* convert into virtual address */
@@ -922,7 +922,7 @@ void leon_prom_init(struct leon_prom_info *pspi)
pspi->freq_khz = CONFIG_SYS_CLK_FREQ / 1000;
/* Set Available main memory size */
- pspi->totphys.num_bytes = CFG_PROM_OFFSET - CFG_SDRAM_BASE;
+ pspi->totphys.num_bytes = CONFIG_SYS_PROM_OFFSET - CONFIG_SYS_SDRAM_BASE;
pspi->avail.num_bytes = pspi->totphys.num_bytes;
/* Set the pointer to the Console UART in romvec */
@@ -982,7 +982,7 @@ extern unsigned short bss_start, bss_end;
int prom_init(void)
{
struct leon_prom_info *pspi = (void *)
- ((((unsigned int)&spi) & PROM_SIZE_MASK) + CFG_PROM_OFFSET);
+ ((((unsigned int)&spi) & PROM_SIZE_MASK) + CONFIG_SYS_PROM_OFFSET);
/* disable mmu */
srmmu_set_mmureg(0x00000000);
@@ -1008,7 +1008,7 @@ void prepare_bootargs(char *bootargs)
/* if no bootargs set, skip copying ==> default bootline */
if (bootargs && (*bootargs != '\0')) {
pspi = (void *)((((unsigned int)&spi) & PROM_SIZE_MASK) +
- CFG_PROM_OFFSET);
+ CONFIG_SYS_PROM_OFFSET);
src = bootargs;
dst = &pspi->arg[0];
left = 255; /* max len */
@@ -1025,7 +1025,7 @@ void srmmu_init_cpu(unsigned int entry)
{
sparc_srmmu_setup *psrmmu_tables = (void *)
((((unsigned int)&srmmu_tables) & PROM_SIZE_MASK) +
- CFG_PROM_OFFSET);
+ CONFIG_SYS_PROM_OFFSET);
/* Make context 0 (kernel's context) point
* to our prepared memory mapping
@@ -1041,21 +1041,21 @@ void srmmu_init_cpu(unsigned int entry)
#define PTE 2
#define ACC_SU_ALL 0x1c
psrmmu_tables->pgd_table[0xf0] =
- (CFG_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE;
+ (CONFIG_SYS_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf1] =
- ((CFG_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf2] =
- ((CFG_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf3] =
- ((CFG_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf4] =
- ((CFG_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf5] =
- ((CFG_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf6] =
- ((CFG_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf7] =
- ((CFG_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE;
+ ((CONFIG_SYS_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE;
/* convert rom vec pointer to virtual address */
kernel_arg_promvec = (struct linux_romvec *)
diff --git a/cpu/leon3/serial.c b/cpu/leon3/serial.c
index 27d5cd3..4b2fcb8 100644
--- a/cpu/leon3/serial.c
+++ b/cpu/leon3/serial.c
@@ -58,7 +58,7 @@ int serial_init(void)
*
* Receiver & transmitter enable
*/
- leon3_apbuart->scaler = CFG_GRLIB_APBUART_SCALER;
+ leon3_apbuart->scaler = CONFIG_SYS_GRLIB_APBUART_SCALER;
/* Let bit 11 be unchanged (debug bit for GRMON) */
tmp = READ_WORD(leon3_apbuart->ctrl);
diff --git a/cpu/leon3/start.S b/cpu/leon3/start.S
index d421898..bd634bd 100644
--- a/cpu/leon3/start.S
+++ b/cpu/leon3/start.S
@@ -27,6 +27,7 @@
#include <asm/psr.h>
#include <asm/stack.h>
#include <asm/leon.h>
+#include <timestamp.h>
#include <version.h>
/* Entry for traps which jump to a programmer-specified trap handler. */
@@ -68,7 +69,7 @@ ARGPUSH = (WINDOWSIZE + 4)
MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
/* Number of register windows */
-#ifndef CFG_SPARC_NWINDOWS
+#ifndef CONFIG_SYS_SPARC_NWINDOWS
#error Must define number of SPARC register windows, default is 8
#endif
@@ -200,7 +201,7 @@ _trap_table:
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
.section ".text"
@@ -251,7 +252,7 @@ wininit:
mov %g3, %wim
stackp:
- set CFG_INIT_SP_OFFSET, %fp
+ set CONFIG_SYS_INIT_SP_OFFSET, %fp
andn %fp, 0x0f, %fp
sub %fp, 64, %sp
@@ -268,7 +269,7 @@ cpu_init_unreloc:
reloc:
set TEXT_START,%g2
set DATA_END,%g3
- set CFG_RELOC_MONITOR_BASE,%g4
+ set CONFIG_SYS_RELOC_MONITOR_BASE,%g4
reloc_loop:
ldd [%g2],%l0
ldd [%g2+8],%l2
@@ -314,10 +315,10 @@ fixup_got:
set __got_end,%g3
/*
* new got offset = (old GOT-PTR (read with ld) -
- * CFG_RELOC_MONITOR_BASE(from define) ) +
+ * CONFIG_SYS_RELOC_MONITOR_BASE(from define) ) +
* Destination Address (from define)
*/
- set CFG_RELOC_MONITOR_BASE,%g2
+ set CONFIG_SYS_RELOC_MONITOR_BASE,%g2
set TEXT_START, %g1
add %g4,%g2,%g4
sub %g4,%g1,%g4
@@ -338,7 +339,7 @@ got_loop:
prom_relocate:
set __prom_start, %g2
set __prom_end, %g3
- set CFG_PROM_OFFSET, %g4
+ set CONFIG_SYS_PROM_OFFSET, %g4
prom_relocate_loop:
ldd [%g2],%l0
@@ -354,7 +355,7 @@ prom_relocate_loop:
* the new trap table address
*/
- set CFG_RELOC_MONITOR_BASE, %g2
+ set CONFIG_SYS_RELOC_MONITOR_BASE, %g2
wr %g0, %g2, %tbr
nop
nop
@@ -368,22 +369,22 @@ snoop_detect:
sethi %hi(0x00800000), %o0
lda [%g0] 2, %o1
and %o0, %o1, %o0
- sethi %hi(leon3_snooping_avail+CFG_RELOC_MONITOR_BASE-TEXT_BASE), %o1
- st %o0, [%lo(leon3_snooping_avail+CFG_RELOC_MONITOR_BASE-TEXT_BASE)+%o1]
+ sethi %hi(leon3_snooping_avail+CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE), %o1
+ st %o0, [%lo(leon3_snooping_avail+CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE)+%o1]
/* call relocate*/
nop
/* Call relocated init functions */
jump:
set cpu_init_f2,%o1
- set CFG_RELOC_MONITOR_BASE,%o2
+ set CONFIG_SYS_RELOC_MONITOR_BASE,%o2
add %o1,%o2,%o1
sub %o1,%g1,%o1
call %o1
clr %o0
set board_init_f,%o1
- set CFG_RELOC_MONITOR_BASE,%o2
+ set CONFIG_SYS_RELOC_MONITOR_BASE,%o2
add %o1,%o2,%o1
sub %o1,%g1,%o1
call %o1
@@ -409,7 +410,7 @@ _irq_entry:
WRITE_PAUSE
mov %l7, %o0 ! irq level
set handler_irq, %o1
- set (CFG_RELOC_MONITOR_BASE-TEXT_BASE), %o2
+ set (CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE), %o2
add %o1, %o2, %o1
call %o1
add %sp, SF_REGS_SZ, %o1 ! pt_regs ptr
@@ -427,7 +428,7 @@ _window_overflow:
mov %wim, %l3 ! Calculate next WIM
mov %g1, %l7
srl %l3, 1, %g1
- sll %l3, (CFG_SPARC_NWINDOWS-1) , %l4
+ sll %l3, (CONFIG_SYS_SPARC_NWINDOWS-1) , %l4
or %l4, %g1, %g1
save ! Get into window to be saved.
@@ -464,7 +465,7 @@ _window_underflow:
mov %wim, %l3 ! Calculate next WIM
sll %l3, 1, %l4
- srl %l3, (CFG_SPARC_NWINDOWS-1), %l5
+ srl %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l5
or %l5, %l4, %l5
mov %l5, %wim
nop; nop; nop
@@ -533,7 +534,7 @@ trap_setup:
*/
srl %t_wim, 0x1, %g2 ! begin computation of new %wim
- set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
+ set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
sll %t_wim, %g3, %t_wim ! NWINDOWS-1
or %t_wim, %g2, %g2
@@ -567,7 +568,7 @@ ret_trap_entry:
mov 2, %g1
sll %g1, %t_psr, %g1
- set CFG_SPARC_NWINDOWS, %g2 !NWINDOWS
+ set CONFIG_SYS_SPARC_NWINDOWS, %g2 !NWINDOWS
srl %g1, %g2, %g2
or %g1, %g2, %g1
@@ -577,7 +578,7 @@ ret_trap_entry:
sll %g2, 0x1, %g1
/* We have to grab a window before returning. */
- set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
+ set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
srl %g2, %g3, %g2
or %g1, %g2, %g1
diff --git a/cpu/leon3/usb_uhci.c b/cpu/leon3/usb_uhci.c
index 7910beb..8f99e1d 100644
--- a/cpu/leon3/usb_uhci.c
+++ b/cpu/leon3/usb_uhci.c
@@ -901,7 +901,7 @@ int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
unsigned short wIndex;
unsigned short wLength;
- if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+ if (usb_pipeint(pipe)) {
printf("Root-Hub submit IRQ: NOT implemented\n");
return 0;
}
diff --git a/cpu/lh7a40x/config.mk b/cpu/lh7a40x/config.mk
index 10e755b..32fd1d1 100644
--- a/cpu/lh7a40x/config.mk
+++ b/cpu/lh7a40x/config.mk
@@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv4
#
# ========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c
index 578eb73..8ff3a36 100644
--- a/cpu/lh7a40x/cpu.c
+++ b/cpu/lh7a40x/cpu.c
@@ -94,7 +94,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;
diff --git a/cpu/lh7a40x/interrupts.c b/cpu/lh7a40x/interrupts.c
index d01787f..5acfe1a 100644
--- a/cpu/lh7a40x/interrupts.c
+++ b/cpu/lh7a40x/interrupts.c
@@ -59,7 +59,7 @@ int interrupt_init (void)
/*
* 10ms period with 508.469kHz clock = 5084
*/
- timer_load_val = CFG_HZ/100;
+ timer_load_val = CONFIG_SYS_HZ/100;
}
/* load value for 10 ms timeout */
@@ -98,12 +98,12 @@ void udelay (unsigned long usec)
/* normalize */
if (usec >= 1000) {
tmo = usec / 1000;
- tmo *= CFG_HZ;
+ tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
}
else {
if (usec > 1) {
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
else
@@ -152,11 +152,11 @@ void udelay_masked (unsigned long usec)
/* normalize */
if (usec >= 1000) {
tmo = usec / 1000;
- tmo *= CFG_HZ;
+ tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
} else {
if (usec > 1) {
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
} else {
tmo = 1;
diff --git a/cpu/lh7a40x/start.S b/cpu/lh7a40x/start.S
index e4655d6..11252ce 100644
--- a/cpu/lh7a40x/start.S
+++ b/cpu/lh7a40x/start.S
@@ -172,8 +172,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -285,8 +285,8 @@ cpu_init_crit:
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@@ -318,8 +318,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
diff --git a/cpu/mcf5227x/Makefile b/cpu/mcf5227x/Makefile
index d0e9b45..44f9385 100644
--- a/cpu/mcf5227x/Makefile
+++ b/cpu/mcf5227x/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
-COBJS = cpu.o speed.o cpu_init.o interrupts.o
+COBJS = cpu.o speed.o cpu_init.o interrupts.o dspi.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mcf5227x/cpu.c b/cpu/mcf5227x/cpu.c
index 5792a1c..d9f5f43 100644
--- a/cpu/mcf5227x/cpu.c
+++ b/cpu/mcf5227x/cpu.c
@@ -60,15 +60,17 @@ int checkcpu(void)
}
if (id) {
+ char buf1[32], buf2[32], buf3[32];
+
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
ver);
- printf(" CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n",
- (int)(gd->cpu_clk / 1000000),
- (int)(gd->bus_clk / 1000000),
- (int)(gd->flb_clk / 1000000));
- printf(" INP CLK %d Mhz VCO CLK %d Mhz\n",
- (int)(gd->inp_clk / 1000000),
- (int)(gd->vco_clk / 1000000));
+ printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
+ strmhz(buf1, gd->cpu_clk),
+ strmhz(buf2, gd->bus_clk),
+ strmhz(buf3, gd->flb_clk));
+ printf(" INP CLK %s MHz VCO CLK %s MHz\n",
+ strmhz(buf1, gd->inp_clk),
+ strmhz(buf2, gd->vco_clk));
}
return 0;
diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c
index cf29559..8945ef3 100644
--- a/cpu/mcf5227x/cpu_init.c
+++ b/cpu/mcf5227x/cpu_init.c
@@ -45,6 +45,7 @@ void cpu_init_f(void)
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+#if !defined(CONFIG_CF_SBF)
/* Workaround, must place before fbcs */
pll->psr = 0x12;
@@ -58,40 +59,47 @@ void cpu_init_f(void)
scm1->pacrg = 0;
scm1->pacri = 0;
-#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
- fbcs->csar0 = CFG_CS0_BASE;
- fbcs->cscr0 = CFG_CS0_CTRL;
- fbcs->csmr0 = CFG_CS0_MASK;
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+ && defined(CONFIG_SYS_CS0_CTRL))
+ fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+ fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+ fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
+#endif /* CONFIG_CF_SBF */
-#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
- fbcs->csar1 = CFG_CS1_BASE;
- fbcs->cscr1 = CFG_CS1_CTRL;
- fbcs->csmr1 = CFG_CS1_MASK;
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+ && defined(CONFIG_SYS_CS1_CTRL))
+ fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+ fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+ fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
-#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
- fbcs->csar2 = CFG_CS2_BASE;
- fbcs->cscr2 = CFG_CS2_CTRL;
- fbcs->csmr2 = CFG_CS2_MASK;
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+ && defined(CONFIG_SYS_CS2_CTRL))
+ fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+ fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+ fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
-#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
- fbcs->csar3 = CFG_CS3_BASE;
- fbcs->cscr3 = CFG_CS3_CTRL;
- fbcs->csmr3 = CFG_CS3_MASK;
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+ && defined(CONFIG_SYS_CS3_CTRL))
+ fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+ fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+ fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
-#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
- fbcs->csar4 = CFG_CS4_BASE;
- fbcs->cscr4 = CFG_CS4_CTRL;
- fbcs->csmr4 = CFG_CS4_MASK;
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+ && defined(CONFIG_SYS_CS4_CTRL))
+ fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+ fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+ fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
-#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
- fbcs->csar5 = CFG_CS5_BASE;
- fbcs->cscr5 = CFG_CS5_CTRL;
- fbcs->csmr5 = CFG_CS5_MASK;
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+ && defined(CONFIG_SYS_CS5_CTRL))
+ fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+ fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+ fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
#ifdef CONFIG_FSL_I2C
@@ -107,12 +115,12 @@ void cpu_init_f(void)
int cpu_init_r(void)
{
#ifdef CONFIG_MCFRTC
- volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
+ volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
- u32 oscillator = CFG_RTC_OSCILLATOR;
+ u32 oscillator = CONFIG_SYS_RTC_OSCILLATOR;
- rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
- rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
+ rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
+ rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
#endif
return (0);
@@ -123,7 +131,7 @@ void uart_port_conf(void)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->par_uart &=
(GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK);
diff --git a/cpu/mcf5227x/dspi.c b/cpu/mcf5227x/dspi.c
new file mode 100644
index 0000000..7f48f91
--- /dev/null
+++ b/cpu/mcf5227x/dspi.c
@@ -0,0 +1,261 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <malloc.h>
+
+#if defined(CONFIG_CF_DSPI)
+#include <asm/immap.h>
+
+void dspi_init(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ gpio->par_dspi =
+ GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK;
+
+ dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
+ DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
+ DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
+ DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
+
+#ifdef CONFIG_SYS_DSPI_DCTAR0
+ dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR1
+ dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR2
+ dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR3
+ dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR4
+ dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR5
+ dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR6
+ dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR7
+ dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
+#endif
+}
+
+void dspi_tx(int chipsel, u8 attrib, u16 data)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ while ((dspi->dsr & 0x0000F000) >= 4) ;
+
+ dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
+}
+
+u16 dspi_rx(void)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ while ((dspi->dsr & 0x000000F0) == 0) ;
+
+ return (dspi->drfr & 0xFFFF);
+}
+
+#if defined(CONFIG_CMD_SPI)
+void spi_init_f(void)
+{
+}
+
+void spi_init_r(void)
+{
+}
+
+void spi_init(void)
+{
+ dspi_init();
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ struct spi_slave *slave;
+
+ slave = malloc(sizeof(struct spi_slave));
+ if (!slave)
+ return NULL;
+
+ switch (cs) {
+ case 0:
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+ gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+ break;
+ case 2:
+ gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+ gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
+ break;
+ }
+
+ slave->bus = bus;
+ slave->cs = cs;
+
+ return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ switch (slave->cs) {
+ case 0:
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+ break;
+ case 2:
+ gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+ break;
+ }
+
+ free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ static int bWrite = 0;
+ u8 *spi_rd, *spi_wr;
+ int len = bitlen >> 3;
+
+ spi_rd = (u8 *) din;
+ spi_wr = (u8 *) dout;
+
+ /* command handling */
+ if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
+ switch (*spi_wr) {
+ case 0x02: /* Page Prog */
+ bWrite = 1;
+ dspi_tx(slave->cs, 0x80, spi_wr[0]);
+ dspi_rx();
+ dspi_tx(slave->cs, 0x80, spi_wr[1]);
+ dspi_rx();
+ dspi_tx(slave->cs, 0x80, spi_wr[2]);
+ dspi_rx();
+ dspi_tx(slave->cs, 0x80, spi_wr[3]);
+ dspi_rx();
+ return 0;
+ case 0x05: /* Read Status */
+ if (len == 4)
+ if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
+ && (spi_wr[3] == 0xFF)) {
+ dspi_tx(slave->cs, 0x80, *spi_wr);
+ dspi_rx();
+ }
+ return 0;
+ case 0x06: /* WREN */
+ dspi_tx(slave->cs, 0x00, *spi_wr);
+ dspi_rx();
+ return 0;
+ case 0x0B: /* Fast read */
+ if ((len == 5) && (spi_wr[4] == 0)) {
+ dspi_tx(slave->cs, 0x80, spi_wr[0]);
+ dspi_rx();
+ dspi_tx(slave->cs, 0x80, spi_wr[1]);
+ dspi_rx();
+ dspi_tx(slave->cs, 0x80, spi_wr[2]);
+ dspi_rx();
+ dspi_tx(slave->cs, 0x80, spi_wr[3]);
+ dspi_rx();
+ dspi_tx(slave->cs, 0x80, spi_wr[4]);
+ dspi_rx();
+ }
+ return 0;
+ case 0x9F: /* RDID */
+ dspi_tx(slave->cs, 0x80, *spi_wr);
+ dspi_rx();
+ return 0;
+ case 0xD8: /* Sector erase */
+ if (len == 4)
+ if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
+ dspi_tx(slave->cs, 0x80, spi_wr[0]);
+ dspi_rx();
+ dspi_tx(slave->cs, 0x80, spi_wr[1]);
+ dspi_rx();
+ dspi_tx(slave->cs, 0x80, spi_wr[2]);
+ dspi_rx();
+ dspi_tx(slave->cs, 0x00, spi_wr[3]);
+ dspi_rx();
+ }
+ return 0;
+ }
+ }
+
+ if (bWrite)
+ len--;
+
+ while (len--) {
+ if (dout != NULL) {
+ dspi_tx(slave->cs, 0x80, *spi_wr);
+ dspi_rx();
+ spi_wr++;
+ }
+
+ if (din != NULL) {
+ dspi_tx(slave->cs, 0x80, 0);
+ *spi_rd = dspi_rx();
+ spi_rd++;
+ }
+ }
+
+ if (flags == SPI_XFER_END) {
+ if (bWrite) {
+ dspi_tx(slave->cs, 0x00, *spi_wr);
+ dspi_rx();
+ bWrite = 0;
+ } else {
+ dspi_tx(slave->cs, 0x00, 0);
+ dspi_rx();
+ }
+ }
+
+ return 0;
+}
+#endif /* CONFIG_CMD_SPI */
+
+#endif /* CONFIG_CF_DSPI */
diff --git a/cpu/mcf5227x/interrupts.c b/cpu/mcf5227x/interrupts.c
index 9572a7b..85828a6 100644
--- a/cpu/mcf5227x/interrupts.c
+++ b/cpu/mcf5227x/interrupts.c
@@ -31,7 +31,7 @@
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrh0 |= 0xFFFFFFFF;
@@ -44,9 +44,9 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
- intp->imrh0 &= ~CFG_TMRINTR_MASK;
+ intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
+ intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
}
#endif
diff --git a/cpu/mcf5227x/speed.c b/cpu/mcf5227x/speed.c
index 0baf9bc..7e385d3 100644
--- a/cpu/mcf5227x/speed.c
+++ b/cpu/mcf5227x/speed.c
@@ -90,23 +90,39 @@ int get_clocks(void)
int vco, temp, pcrvalue, pfdr;
u8 bootmode;
- bootmode = (ccm->ccr & 0x000C) >> 2;
-
pcrvalue = pll->pcr & 0xFF0F0FFF;
pfdr = pcrvalue >> 24;
- if (pfdr != 0x1E) {
+ if (pfdr == 0x1E)
+ bootmode = 0; /* Normal Mode */
+
+#ifdef CONFIG_CF_SBF
+ bootmode = 3; /* Serial Mode */
+#endif
+
+ if (bootmode == 0) {
+ /* Normal mode */
+ vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+ if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
+ /* Default value */
+ pcrvalue = (pll->pcr & 0x00FFFFFF);
+ pcrvalue |= 0x1E << 24;
+ pll->pcr = pcrvalue;
+ vco =
+ ((pll->pcr & 0xFF000000) >> 24) *
+ CONFIG_SYS_INPUT_CLKSRC;
+ }
+ gd->vco_clk = vco; /* Vco clock */
+ } else if (bootmode == 3) {
/* serial mode */
- } else {
- /* Normal Mode */
- vco = pfdr * CFG_INPUT_CLKSRC;
- gd->vco_clk = vco;
+ vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+ gd->vco_clk = vco; /* Vco clock */
}
if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */
} else {
- gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */
+ gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */
diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S
index 1b47c97..0c9c89c 100644
--- a/cpu/mcf5227x/start.S
+++ b/cpu/mcf5227x/start.S
@@ -22,6 +22,7 @@
*/
#include <config.h>
+#include <timestamp.h>
#include "version.h"
#ifndef CONFIG_IDENT_STRING
@@ -29,9 +30,9 @@
#endif
/* last three long word reserved for cache status */
-#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
-#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
-#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
+#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
#define _START _start
#define _FAULT _fault
@@ -46,6 +47,11 @@
addl #60,%sp; /* space for 15 regs */ \
rte;
+#if defined(CONFIG_CF_SBF)
+#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+
.text
/*
* Vector table. This is used for initial platform startup.
@@ -53,8 +59,14 @@
*/
_vectors:
-INITSP: .long 0x00000000 /* Initial SP */
-INITPC: .long _START /* Initial PC */
+#if defined(CONFIG_CF_SBF)
+INITSP: .long 0 /* Initial SP */
+INITPC: .long ASM_DRAMINIT /* Initial PC */
+#else
+INITSP: .long 0 /* Initial SP */
+INITPC: .long _START /* Initial PC */
+#endif
+
vector02: .long _FAULT /* Access Error */
vector03: .long _FAULT /* Address Error */
vector04: .long _FAULT /* Illegal Instruction */
@@ -83,6 +95,7 @@ vector1D: .long _FAULT /* Autovector Level 5 */
vector1E: .long _FAULT /* Autovector Level 6 */
vector1F: .long _FAULT /* Autovector Level 7 */
+#if !defined(CONFIG_CF_SBF)
/* TRAP #0 - #15 */
vector20_2F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
@@ -122,9 +135,231 @@ vector192_255:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+#endif
- .text
+#if defined(CONFIG_CF_SBF)
+ /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
+asm_sbf_img_hdr:
+ .long 0x00000000 /* checksum, not yet implemented */
+ .long 0x00020000 /* image length */
+ .long TEXT_BASE /* image to be relocated at */
+
+asm_dram_init:
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ movec %d0, %RAMBAR1 /* init Rambar */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ clr.l %sp@-
+
+ /* Must disable global address */
+ move.l #0xFC008000, %a1
+ move.l #(CONFIG_SYS_CS0_BASE), (%a1)
+ move.l #0xFC008008, %a1
+ move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
+ move.l #0xFC008004, %a1
+ move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+
+ /*
+ * Dram Initialization
+ * a1, a2, and d0
+ */
+ /* mscr sdram */
+ move.l #0xFC0A4074, %a1
+ move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
+ nop
+
+ /* SDRAM Chip 0 and 1 */
+ move.l #0xFC0B8110, %a1
+ move.l #0xFC0B8114, %a2
+
+ /* calculate the size */
+ move.l #0x13, %d1
+ move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
+#ifdef CONFIG_SYS_SDRAM_BASE1
+ lsr.l #1, %d2
+#endif
+
+dramsz_loop:
+ lsr.l #1, %d2
+ add.l #1, %d1
+ cmp.l #1, %d2
+ bne dramsz_loop
+
+ /* SDRAM Chip 0 and 1 */
+ move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
+ or.l %d1, (%a1)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+ move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
+ or.l %d1, (%a2)
+#endif
+ nop
+
+ /* dram cfg1 and cfg2 */
+ move.l #0xFC0B8008, %a1
+ move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
+ nop
+ move.l #0xFC0B800C, %a2
+ move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
+ nop
+
+ move.l #0xFC0B8000, %a1 /* Mode */
+ move.l #0xFC0B8004, %a2 /* Ctrl */
+
+ /* Issue PALL */
+ move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+ nop
+
+ /* Issue LEMR */
+ move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
+ nop
+ move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
+ nop
+
+ move.l #1000, %d0
+wait1000:
+ nop
+ subq.l #1, %d0
+ bne wait1000
+
+ /* Issue PALL */
+ move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+ nop
+
+ /* Perform two refresh cycles */
+ move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
+ nop
+ move.l %d0, (%a2)
+ move.l %d0, (%a2)
+ nop
+
+ move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
+ and.l #0x7FFFFFFF, %d0
+ or.l #0x10000c00, %d0
+ move.l %d0, (%a2)
+ nop
+ /*
+ * DSPI Initialization
+ * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
+ * a1 - dspi status
+ * a2 - dtfr
+ * a3 - drfr
+ * a4 - Dst addr
+ */
+
+ /* Enable pins for DSPI mode - chip-selects are enabled later */
+ move.l #0xFC0A4036, %a0
+ move.b #0x3F, %d0
+ move.b %d0, (%a0)
+
+ /* DSPI CS */
+#ifdef CONFIG_SYS_DSPI_CS0
+ move.b (%a0), %d0
+ or.l #0xC0, %d0
+ move.b %d0, (%a0)
+#endif
+#ifdef CONFIG_SYS_DSPI_CS2
+ move.l #0xFC0A4037, %a0
+ move.b (%a0), %d0
+ or.l #0x10, %d0
+ move.b %d0, (%a0)
+#endif
+ nop
+
+ /* Configure DSPI module */
+ move.l #0xFC05C000, %a0
+ move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
+
+ move.l #0xFC05C00C, %a0
+ move.l #0x3E000011, (%a0)
+
+ move.l #0xFC05C034, %a2 /* dtfr */
+ move.l #0xFC05C03B, %a3 /* drfr */
+
+ move.l #(ASM_SBF_IMG_HDR + 4), %a1
+ move.l (%a1)+, %d5
+ move.l (%a1), %a4
+
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
+ move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
+
+ move.l #0xFC05C02C, %a1 /* dspi status */
+
+ /* Issue commands and address */
+ move.l #0x8004000B, %d2 /* Fast Read Cmd */
+ jsr asm_dspi_wr_status
+ jsr asm_dspi_rd_status
+
+ move.l #0x80040000, %d2 /* Address byte 2 */
+ jsr asm_dspi_wr_status
+ jsr asm_dspi_rd_status
+
+ move.l #0x80040000, %d2 /* Address byte 1 */
+ jsr asm_dspi_wr_status
+ jsr asm_dspi_rd_status
+
+ move.l #0x80040000, %d2 /* Address byte 0 */
+ jsr asm_dspi_wr_status
+ jsr asm_dspi_rd_status
+
+ move.l #0x80040000, %d2 /* Dummy Wr and Rd */
+ jsr asm_dspi_wr_status
+ jsr asm_dspi_rd_status
+
+ /* Transfer serial boot header to sram */
+asm_dspi_rd_loop1:
+ move.l #0x80040000, %d2
+ jsr asm_dspi_wr_status
+ jsr asm_dspi_rd_status
+
+ move.b %d1, (%a0) /* read, copy to dst */
+
+ add.l #1, %a0 /* inc dst by 1 */
+ sub.l #1, %d4 /* dec cnt by 1 */
+ bne asm_dspi_rd_loop1
+
+ /* Transfer u-boot from serial flash to memory */
+asm_dspi_rd_loop2:
+ move.l #0x80040000, %d2
+ jsr asm_dspi_wr_status
+ jsr asm_dspi_rd_status
+
+ move.b %d1, (%a4) /* read, copy to dst */
+
+ add.l #1, %a4 /* inc dst by 1 */
+ sub.l #1, %d5 /* dec cnt by 1 */
+ bne asm_dspi_rd_loop2
+
+ move.l #0x00040000, %d2 /* Terminate */
+ jsr asm_dspi_wr_status
+ jsr asm_dspi_rd_status
+
+ /* jump to memory and execute */
+ move.l #(TEXT_BASE + 0x400), %a0
+ move.l %a0, (%a1)
+ jmp (%a0)
+
+asm_dspi_wr_status:
+ move.l (%a1), %d0 /* status */
+ and.l #0x0000F000, %d0
+ cmp.l #0x00003000, %d0
+ bgt asm_dspi_wr_status
+
+ move.l %d2, (%a2)
+ rts
+
+asm_dspi_rd_status:
+ move.l (%a1), %d0 /* status */
+ and.l #0x000000F0, %d0
+ lsr.l #4, %d0
+ cmp.l #0, %d0
+ beq asm_dspi_rd_status
+
+ move.b (%a3), %d1
+ rts
+#endif /* CONFIG_CF_SBF */
+
+ .text
+ . = 0x400
.globl _start
_start:
nop
@@ -132,11 +367,16 @@ _start:
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
- move.l #CFG_FLASH_BASE, %d0
+#if defined(CONFIG_CF_SBF)
+ move.l #TEXT_BASE, %d0
+ movec %d0, %VBR
+#else
+ move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
+#endif
/* initialize general use internal ram */
move.l #0, %d0
@@ -156,7 +396,7 @@ _start:
/* set stackpointer to end of internal ram to get some stackspace for
the first c-code */
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
@@ -187,7 +427,7 @@ relocate_code:
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
- move.l #CFG_MONITOR_BASE, %a1
+ move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
@@ -202,7 +442,7 @@ relocate_code:
* initialization, now running from RAM.
*/
move.l %a0, %a1
- add.l #(in_ram - CFG_MONITOR_BASE), %a1
+ add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
@@ -212,9 +452,9 @@ clear_bss:
* Now clear BSS segment
*/
move.l %a0, %a1
- add.l #(_sbss - CFG_MONITOR_BASE),%a1
+ add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
- add.l #(_ebss - CFG_MONITOR_BASE),%d1
+ add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -224,11 +464,11 @@ clear_bss:
* fix got table in RAM
*/
move.l %a0, %a1
- add.l #(__got_start - CFG_MONITOR_BASE),%a1
+ add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
- add.l #(__got_end - CFG_MONITOR_BASE),%a2
+ add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
@@ -240,7 +480,7 @@ clear_bss:
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
- add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+ add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
@@ -276,7 +516,7 @@ icache_enable:
move.l #0x01200000, %d0 /* Invalid cache */
movec %d0, %CACR
- move.l #(CFG_SDRAM_BASE + 0x1c000), %d0
+ move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
movec %d0, %ACR0
move.l #0x81600610, %d0 /* Enable cache */
@@ -352,6 +592,6 @@ dcache_status:
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
.align 4
diff --git a/cpu/mcf523x/cpu.c b/cpu/mcf523x/cpu.c
index 8d2152d..a1a5133 100644
--- a/cpu/mcf523x/cpu.c
+++ b/cpu/mcf523x/cpu.c
@@ -28,6 +28,7 @@
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <netdev.h>
#include <asm/immap.h>
@@ -59,11 +60,13 @@ int checkcpu(void)
}
if (id) {
+ char buf1[32], buf2[32];
+
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
ver);
- printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n",
- (int)(gd->cpu_clk / 1000000),
- (int)(gd->bus_clk / 1000000));
+ printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
+ strmhz(buf1, gd->cpu_clk),
+ strmhz(buf2, gd->bus_clk));
}
return 0;
@@ -97,7 +100,7 @@ int watchdog_init(void)
u32 wdog_module = 0;
/* set timeout and enable watchdog */
- wdog_module = ((CFG_CLK / CFG_HZ) * CONFIG_WATCHDOG_TIMEOUT);
+ wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
wdog_module |= (wdog_module / 8192);
wdp->mr = wdog_module;
@@ -114,8 +117,6 @@ int watchdog_init(void)
* int board_eth_init(bd_t *bis)
*/
-extern int mcffec_initialize(bd_t*);
-
int cpu_eth_init(bd_t *bis)
{
return mcffec_initialize(bis);
diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c
index 8ab5b8e..3c04fd4 100644
--- a/cpu/mcf523x/cpu_init.c
+++ b/cpu/mcf523x/cpu_init.c
@@ -27,9 +27,14 @@
#include <common.h>
#include <watchdog.h>
-
#include <asm/immap.h>
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
/*
* Breath some life into the CPU...
*
@@ -49,69 +54,69 @@ void cpu_init_f(void)
wdog->cr = 0;
#endif
- scm->rambar = (CFG_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
+ scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
/* Port configuration */
gpio->par_cs = 0;
-#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
- fbcs->csar0 = CFG_CS0_BASE;
- fbcs->cscr0 = CFG_CS0_CTRL;
- fbcs->csmr0 = CFG_CS0_MASK;
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+ fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+ fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+ fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
-#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS1;
- fbcs->csar1 = CFG_CS1_BASE;
- fbcs->cscr1 = CFG_CS1_CTRL;
- fbcs->csmr1 = CFG_CS1_MASK;
+ fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+ fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+ fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
-#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS2;
- fbcs->csar2 = CFG_CS2_BASE;
- fbcs->cscr2 = CFG_CS2_CTRL;
- fbcs->csmr2 = CFG_CS2_MASK;
+ fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+ fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+ fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
-#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS3;
- fbcs->csar3 = CFG_CS3_BASE;
- fbcs->cscr3 = CFG_CS3_CTRL;
- fbcs->csmr3 = CFG_CS3_MASK;
+ fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+ fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+ fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
-#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS4;
- fbcs->csar4 = CFG_CS4_BASE;
- fbcs->cscr4 = CFG_CS4_CTRL;
- fbcs->csmr4 = CFG_CS4_MASK;
+ fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+ fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+ fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
-#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS5;
- fbcs->csar5 = CFG_CS5_BASE;
- fbcs->cscr5 = CFG_CS5_CTRL;
- fbcs->csmr5 = CFG_CS5_MASK;
+ fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+ fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+ fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
-#if (defined(CFG_CS6_BASE) && defined(CFG_CS6_MASK) && defined(CFG_CS6_CTRL))
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS6;
- fbcs->csar6 = CFG_CS6_BASE;
- fbcs->cscr6 = CFG_CS6_CTRL;
- fbcs->csmr6 = CFG_CS6_MASK;
+ fbcs->csar6 = CONFIG_SYS_CS6_BASE;
+ fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
+ fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
#endif
-#if (defined(CFG_CS7_BASE) && defined(CFG_CS7_MASK) && defined(CFG_CS7_CTRL))
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS7;
- fbcs->csar7 = CFG_CS7_BASE;
- fbcs->cscr7 = CFG_CS7_CTRL;
- fbcs->csmr7 = CFG_CS7_MASK;
+ fbcs->csar7 = CONFIG_SYS_CS7_BASE;
+ fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
+ fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
#endif
#ifdef CONFIG_FSL_I2C
- CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR;
- CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
+ CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
+ CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif
icache_enable();
@@ -130,7 +135,7 @@ void uart_port_conf(void)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
break;
@@ -143,3 +148,20 @@ void uart_port_conf(void)
break;
}
}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if (setclear) {
+ gpio->par_feci2c |=
+ (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
+ } else {
+ gpio->par_feci2c &=
+ ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+ }
+
+ return 0;
+}
+#endif
diff --git a/cpu/mcf523x/interrupts.c b/cpu/mcf523x/interrupts.c
index 125c53b..db5ccdf 100644
--- a/cpu/mcf523x/interrupts.c
+++ b/cpu/mcf523x/interrupts.c
@@ -28,7 +28,7 @@
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrl0 |= 0x1;
@@ -40,10 +40,10 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
+ intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
intp->imrl0 &= ~INTC_IPRL_INT0;
- intp->imrl0 &= ~CFG_TMRINTR_MASK;
+ intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
}
#endif
diff --git a/cpu/mcf523x/speed.c b/cpu/mcf523x/speed.c
index 1bda2d4..6096ba4 100644
--- a/cpu/mcf523x/speed.c
+++ b/cpu/mcf523x/speed.c
@@ -42,7 +42,7 @@ int get_clocks(void)
while (!(pll->synsr & PLL_SYNSR_LOCK));
- gd->bus_clk = CFG_CLK;
+ gd->bus_clk = CONFIG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_FSL_I2C
diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S
index 2b638df..d44da37 100644
--- a/cpu/mcf523x/start.S
+++ b/cpu/mcf523x/start.S
@@ -22,6 +22,7 @@
*/
#include <config.h>
+#include <timestamp.h>
#include "version.h"
#ifndef CONFIG_IDENT_STRING
@@ -127,10 +128,10 @@ _start:
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
- move.l #CFG_FLASH_BASE, %d0
+ move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
@@ -143,14 +144,14 @@ _start:
/* initialize general use internal ram */
move.l #0, %d0
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2
move.l %d0, (%a1)
move.l %d0, (%a2)
/* set stackpointer to end of internal ram to get some stackspace for the
first c-code */
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
@@ -181,7 +182,7 @@ relocate_code:
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
- move.l #CFG_MONITOR_BASE, %a1
+ move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
@@ -196,7 +197,7 @@ relocate_code:
* initialization, now running from RAM.
*/
move.l %a0, %a1
- add.l #(in_ram - CFG_MONITOR_BASE), %a1
+ add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
@@ -206,9 +207,9 @@ clear_bss:
* Now clear BSS segment
*/
move.l %a0, %a1
- add.l #(_sbss - CFG_MONITOR_BASE),%a1
+ add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
- add.l #(_ebss - CFG_MONITOR_BASE),%d1
+ add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -218,11 +219,11 @@ clear_bss:
* fix got table in RAM
*/
move.l %a0, %a1
- add.l #(__got_start - CFG_MONITOR_BASE),%a1
+ add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
- add.l #(__got_end - CFG_MONITOR_BASE),%a2
+ add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
@@ -234,7 +235,7 @@ clear_bss:
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
- add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+ add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
@@ -270,16 +271,16 @@ icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
nop
- move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
+ move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
- move.l #(CFG_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */
+ move.l #(CONFIG_SYS_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */
movec %d0, %ACR1 /* Enable cache */
move.l #0x80400100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
nop
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
@@ -292,14 +293,14 @@ icache_disable:
movec %d0, %ACR0
movec %d0, %ACR1
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
moveq #0, %d0
move.l %d0, (%a1)
rts
.globl icache_status
icache_status:
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
move.l (%a1), %d0
rts
@@ -312,7 +313,7 @@ icache_invalid:
.globl dcache_enable
dcache_enable:
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
@@ -320,14 +321,14 @@ dcache_enable:
/* No dcache, just a dummy function */
.globl dcache_disable
dcache_disable:
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
moveq #0, %d0
move.l %d0, (%a1)
rts
.globl dcache_status
dcache_status:
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
move.l (%a1), %d0
rts
@@ -336,6 +337,6 @@ dcache_status:
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
.align 4
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index 2af31cb..32d6c40 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -32,6 +32,7 @@
#include <watchdog.h>
#include <command.h>
#include <asm/immap.h>
+#include <netdev.h>
#ifdef CONFIG_M5271
/*
@@ -65,11 +66,11 @@ int checkcpu(void)
if (cpu_model)
printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
- cpu_model, prn, strmhz(buf, CFG_CLK));
+ cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
else
printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
" (PIN: 0x%x) rev. %hu, at %s MHz\n",
- pin, prn, strmhz(buf, CFG_CLK));
+ pin, prn, strmhz(buf, CONFIG_SYS_CLK));
return 0;
}
@@ -173,7 +174,7 @@ int watchdog_init(void)
/* set timeout and enable watchdog */
wdt->wdog_wrrr =
- ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
+ ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
wdt->wdog_wcr = 0; /* reset watchdog counter */
puts("WATCHDOG:enabled\n");
@@ -201,7 +202,7 @@ int checkcpu(void)
char buf[32];
printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
- strmhz(buf, CFG_CLK));
+ strmhz(buf, CONFIG_SYS_CLK));
return 0;
};
@@ -235,7 +236,7 @@ int watchdog_init(void)
/* set timeout and enable watchdog */
wdt->wmr =
- ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
+ ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
wdt->wsr = 0x5555; /* reset watchdog counter */
wdt->wsr = 0xAAAA;
@@ -277,7 +278,7 @@ int checkcpu(void)
char buf[32];
printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
- strmhz(buf, CFG_CLK));
+ strmhz(buf, CONFIG_SYS_CLK));
return 0;
}
@@ -299,7 +300,7 @@ int checkcpu(void)
unsigned char resetsource = mbar_readLong(SIM_RSR);
printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
- strmhz(buf, CFG_CLK));
+ strmhz(buf, CONFIG_SYS_CLK));
if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
printf("Reset:%s%s\n",
@@ -328,11 +329,8 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
* int board_eth_init(bd_t *bis)
*/
-extern int mcffec_initialize(bd_t*);
-
int cpu_eth_init(bd_t *bis)
{
return mcffec_initialize(bis);
}
#endif
-
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 68aefe9..66f9164 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -36,6 +36,71 @@
#include <watchdog.h>
#include <asm/immap.h>
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
+#ifndef CONFIG_M5272
+/* Only 5272 Flexbus chipselect is different from the rest */
+void init_fbcs(void)
+{
+ volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+ && defined(CONFIG_SYS_CS0_CTRL))
+ fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+ fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+ fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+#else
+#warning "Chip Select 0 are not initialized/used"
+#endif
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+ && defined(CONFIG_SYS_CS1_CTRL))
+ fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+ fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+ fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+ && defined(CONFIG_SYS_CS2_CTRL))
+ fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+ fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+ fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+ && defined(CONFIG_SYS_CS3_CTRL))
+ fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+ fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+ fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+ && defined(CONFIG_SYS_CS4_CTRL))
+ fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+ fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+ fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+ && defined(CONFIG_SYS_CS5_CTRL))
+ fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+ fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+ fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
+ && defined(CONFIG_SYS_CS6_CTRL))
+ fbcs->csar6 = CONFIG_SYS_CS6_BASE;
+ fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
+ fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
+ && defined(CONFIG_SYS_CS7_CTRL))
+ fbcs->csar7 = CONFIG_SYS_CS7_BASE;
+ fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
+ fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+#endif
+}
+#endif
+
#if defined(CONFIG_M5253)
/*
* Breath some life into the CPU...
@@ -68,24 +133,16 @@ void cpu_init_f(void)
/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
- /*
- * Setup chip selects...
- */
-
- mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
- mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
- mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
-
- mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
- mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
- mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
+ /* FlexBus Chipselect */
+ init_fbcs();
#ifdef CONFIG_FSL_I2C
- CFG_I2C_PINMUX_REG = CFG_I2C_PINMUX_REG & CFG_I2C_PINMUX_CLR;
- CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
-#ifdef CFG_I2C2_OFFSET
- CFG_I2C2_PINMUX_REG &= CFG_I2C2_PINMUX_CLR;
- CFG_I2C2_PINMUX_REG |= CFG_I2C2_PINMUX_SET;
+ CONFIG_SYS_I2C_PINMUX_REG =
+ CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
+ CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+#ifdef CONFIG_SYS_I2C2_OFFSET
+ CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
+ CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
#endif
#endif
@@ -102,7 +159,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
break;
case 1:
@@ -121,6 +178,9 @@ void cpu_init_f(void)
mbar_writeShort(MCF_WTM_WCR, 0);
#endif
+ /* FlexBus Chipselect */
+ init_fbcs();
+
/* Set clockspeed to 100MHz */
mbar_writeShort(MCF_FMPLL_SYNCR,
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
@@ -138,7 +198,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
MCF_GPIO_PAR_UART_U0RXD);
@@ -153,6 +213,19 @@ void uart_port_conf(void)
break;
}
}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ if (setclear) {
+ /* Enable Ethernet pins */
+ mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
+ } else {
+ }
+
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
#endif
#if defined(CONFIG_M5272)
@@ -169,59 +242,59 @@ void cpu_init_f(void)
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
+ volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
- sysctrl->sc_scr = CFG_SCR;
- sysctrl->sc_spr = CFG_SPR;
+ sysctrl->sc_scr = CONFIG_SYS_SCR;
+ sysctrl->sc_spr = CONFIG_SYS_SPR;
/* Setup Ports: */
- gpio->gpio_pacnt = CFG_PACNT;
- gpio->gpio_paddr = CFG_PADDR;
- gpio->gpio_padat = CFG_PADAT;
- gpio->gpio_pbcnt = CFG_PBCNT;
- gpio->gpio_pbddr = CFG_PBDDR;
- gpio->gpio_pbdat = CFG_PBDAT;
- gpio->gpio_pdcnt = CFG_PDCNT;
+ gpio->gpio_pacnt = CONFIG_SYS_PACNT;
+ gpio->gpio_paddr = CONFIG_SYS_PADDR;
+ gpio->gpio_padat = CONFIG_SYS_PADAT;
+ gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
+ gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
+ gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
+ gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
/* Memory Controller: */
- csctrl->cs_br0 = CFG_BR0_PRELIM;
- csctrl->cs_or0 = CFG_OR0_PRELIM;
+ csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
+ csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
-#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
- csctrl->cs_br1 = CFG_BR1_PRELIM;
- csctrl->cs_or1 = CFG_OR1_PRELIM;
+#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
+ csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
+ csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
#endif
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
- csctrl->cs_br2 = CFG_BR2_PRELIM;
- csctrl->cs_or2 = CFG_OR2_PRELIM;
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+ csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
+ csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
#endif
-#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
- csctrl->cs_br3 = CFG_BR3_PRELIM;
- csctrl->cs_or3 = CFG_OR3_PRELIM;
+#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+ csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
+ csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
#endif
-#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
- csctrl->cs_br4 = CFG_BR4_PRELIM;
- csctrl->cs_or4 = CFG_OR4_PRELIM;
+#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
+ csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
+ csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
#endif
-#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
- csctrl->cs_br5 = CFG_BR5_PRELIM;
- csctrl->cs_or5 = CFG_OR5_PRELIM;
+#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
+ csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
+ csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
#endif
-#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
- csctrl->cs_br6 = CFG_BR6_PRELIM;
- csctrl->cs_or6 = CFG_OR6_PRELIM;
+#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
+ csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
+ csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
#endif
-#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
- csctrl->cs_br7 = CFG_BR7_PRELIM;
- csctrl->cs_or7 = CFG_OR7_PRELIM;
+#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
+ csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
+ csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
#endif
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
@@ -244,7 +317,7 @@ void uart_port_conf(void)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
@@ -255,6 +328,22 @@ void uart_port_conf(void)
break;
}
}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if (setclear) {
+ gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
+ GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
+ GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
+ GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+ } else {
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
#endif /* #if defined(CONFIG_M5272) */
#if defined(CONFIG_M5275)
@@ -268,71 +357,25 @@ void uart_port_conf(void)
*/
void cpu_init_f(void)
{
- /* if we come from RAM we assume the CPU is
+ /*
+ * if we come from RAM we assume the CPU is
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
- volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
- volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
+ volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
+ volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
/* Kill watchdog so we can initialize the PLL */
wdog_reg->wcr = 0;
- /* Memory Controller: */
- /* Flash */
- csctrl_reg->ar0 = CFG_AR0_PRELIM;
- csctrl_reg->cr0 = CFG_CR0_PRELIM;
- csctrl_reg->mr0 = CFG_MR0_PRELIM;
-
-#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
- csctrl_reg->ar1 = CFG_AR1_PRELIM;
- csctrl_reg->cr1 = CFG_CR1_PRELIM;
- csctrl_reg->mr1 = CFG_MR1_PRELIM;
-#endif
-
-#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
- csctrl_reg->ar2 = CFG_AR2_PRELIM;
- csctrl_reg->cr2 = CFG_CR2_PRELIM;
- csctrl_reg->mr2 = CFG_MR2_PRELIM;
-#endif
-
-#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
- csctrl_reg->ar3 = CFG_AR3_PRELIM;
- csctrl_reg->cr3 = CFG_CR3_PRELIM;
- csctrl_reg->mr3 = CFG_MR3_PRELIM;
-#endif
-
-#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
- csctrl_reg->ar4 = CFG_AR4_PRELIM;
- csctrl_reg->cr4 = CFG_CR4_PRELIM;
- csctrl_reg->mr4 = CFG_MR4_PRELIM;
-#endif
-
-#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
- csctrl_reg->ar5 = CFG_AR5_PRELIM;
- csctrl_reg->cr5 = CFG_CR5_PRELIM;
- csctrl_reg->mr5 = CFG_MR5_PRELIM;
-#endif
-
-#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
- csctrl_reg->ar6 = CFG_AR6_PRELIM;
- csctrl_reg->cr6 = CFG_CR6_PRELIM;
- csctrl_reg->mr6 = CFG_MR6_PRELIM;
-#endif
-
-#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
- csctrl_reg->ar7 = CFG_AR7_PRELIM;
- csctrl_reg->cr7 = CFG_CR7_PRELIM;
- csctrl_reg->mr7 = CFG_MR7_PRELIM;
-#endif
-
+ /* FlexBus Chipselect */
+ init_fbcs();
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_FSL_I2C
- CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR;
- CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
+ CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
+ CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif
/* enable instruction cache now */
@@ -349,10 +392,10 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
- volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->par_uart |= UART0_ENABLE_MASK;
break;
@@ -364,6 +407,35 @@ void uart_port_conf(void)
break;
}
}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ struct fec_info_s *info = (struct fec_info_s *) dev->priv;
+ volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+ if (setclear) {
+ /* Enable Ethernet pins */
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ gpio->par_feci2c |= 0x0F00;
+ gpio->par_fec0hl |= 0xC0;
+ } else {
+ gpio->par_feci2c |= 0x00A0;
+ gpio->par_fec1hl |= 0xC0;
+ }
+ } else {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ gpio->par_feci2c &= ~0x0F00;
+ gpio->par_fec0hl &= ~0xC0;
+ } else {
+ gpio->par_feci2c &= ~0x00A0;
+ gpio->par_fec1hl &= ~0xC0;
+ }
+ }
+
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
#endif /* #if defined(CONFIG_M5275) */
#if defined(CONFIG_M5282)
@@ -384,160 +456,50 @@ void cpu_init_f(void)
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR =
- MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
+ MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
+ MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
/* Set up the GPIO ports */
-#ifdef CFG_PEPAR
- MCFGPIO_PEPAR = CFG_PEPAR;
-#endif
-#ifdef CFG_PFPAR
- MCFGPIO_PFPAR = CFG_PFPAR;
-#endif
-#ifdef CFG_PJPAR
- MCFGPIO_PJPAR = CFG_PJPAR;
+#ifdef CONFIG_SYS_PEPAR
+ MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
#endif
-#ifdef CFG_PSDPAR
- MCFGPIO_PSDPAR = CFG_PSDPAR;
+#ifdef CONFIG_SYS_PFPAR
+ MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
#endif
-#ifdef CFG_PASPAR
- MCFGPIO_PASPAR = CFG_PASPAR;
+#ifdef CONFIG_SYS_PJPAR
+ MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
#endif
-#ifdef CFG_PEHLPAR
- MCFGPIO_PEHLPAR = CFG_PEHLPAR;
+#ifdef CONFIG_SYS_PSDPAR
+ MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
#endif
-#ifdef CFG_PQSPAR
- MCFGPIO_PQSPAR = CFG_PQSPAR;
+#ifdef CONFIG_SYS_PASPAR
+ MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
#endif
-#ifdef CFG_PTCPAR
- MCFGPIO_PTCPAR = CFG_PTCPAR;
+#ifdef CONFIG_SYS_PEHLPAR
+ MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
#endif
-#ifdef CFG_PTDPAR
- MCFGPIO_PTDPAR = CFG_PTDPAR;
-#endif
-#ifdef CFG_PUAPAR
- MCFGPIO_PUAPAR = CFG_PUAPAR;
-#endif
-
-#ifdef CFG_DDRUA
- MCFGPIO_DDRUA = CFG_DDRUA;
-#endif
-
- /* This is probably a bad place to setup chip selects, but everyone
- else is doing it! */
-
-#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
- defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
-
- MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
-
-#if (CFG_CS0_WIDTH == 8)
-#define CFG_CS0_PS MCFCSM_CSCR_PS_8
-#elif (CFG_CS0_WIDTH == 16)
-#define CFG_CS0_PS MCFCSM_CSCR_PS_16
-#elif (CFG_CS0_WIDTH == 32)
-#define CFG_CS0_PS MCFCSM_CSCR_PS_32
-#else
-#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
+#ifdef CONFIG_SYS_PQSPAR
+ MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
#endif
- MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
- | CFG_CS0_PS | MCFCSM_CSCR_AA;
-
-#if (CFG_CS0_RO != 0)
- MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
- | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
- MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
+#ifdef CONFIG_SYS_PTCPAR
+ MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
#endif
-#else
-#warning "Chip Select 0 are not initialized/used"
+#ifdef CONFIG_SYS_PTDPAR
+ MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
#endif
-
-#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
- defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
-
- MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
-
-#if (CFG_CS1_WIDTH == 8)
-#define CFG_CS1_PS MCFCSM_CSCR_PS_8
-#elif (CFG_CS1_WIDTH == 16)
-#define CFG_CS1_PS MCFCSM_CSCR_PS_16
-#elif (CFG_CS1_WIDTH == 32)
-#define CFG_CS1_PS MCFCSM_CSCR_PS_32
-#else
-#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
+#ifdef CONFIG_SYS_PUAPAR
+ MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
#endif
- MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
- | CFG_CS1_PS | MCFCSM_CSCR_AA;
-#if (CFG_CS1_RO != 0)
- MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
- | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
- MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
- | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 1 are not initialized/used"
+#ifdef CONFIG_SYS_DDRUA
+ MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
#endif
-#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
- defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
-
- MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
-
-#if (CFG_CS2_WIDTH == 8)
-#define CFG_CS2_PS MCFCSM_CSCR_PS_8
-#elif (CFG_CS2_WIDTH == 16)
-#define CFG_CS2_PS MCFCSM_CSCR_PS_16
-#elif (CFG_CS2_WIDTH == 32)
-#define CFG_CS2_PS MCFCSM_CSCR_PS_32
-#else
-#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
-#endif
- MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
- | CFG_CS2_PS | MCFCSM_CSCR_AA;
-
-#if (CFG_CS2_RO != 0)
- MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
- | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
- MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
- | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 2 are not initialized/used"
-#endif
-
-#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
- defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
-
- MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
-
-#if (CFG_CS3_WIDTH == 8)
-#define CFG_CS3_PS MCFCSM_CSCR_PS_8
-#elif (CFG_CS3_WIDTH == 16)
-#define CFG_CS3_PS MCFCSM_CSCR_PS_16
-#elif (CFG_CS3_WIDTH == 32)
-#define CFG_CS3_PS MCFCSM_CSCR_PS_32
-#else
-#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
-#endif
- MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
- | CFG_CS3_PS | MCFCSM_CSCR_AA;
-
-#if (CFG_CS3_RO != 0)
- MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
- | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
- MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
- | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 3 are not initialized/used"
-#endif
+ /* FlexBus Chipselect */
+ init_fbcs();
#endif /* CONFIG_MONITOR_IS_IN_RAM */
@@ -556,7 +518,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
MCFGPIO_PUAPAR &= 0xFc;
MCFGPIO_PUAPAR |= 0x03;
@@ -571,6 +533,20 @@ void uart_port_conf(void)
break;
}
}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ if (setclear) {
+ MCFGPIO_PASPAR |= 0x0F00;
+ MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+ } else {
+ MCFGPIO_PASPAR &= 0xF0FF;
+ MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
#endif
#if defined(CONFIG_M5249)
@@ -589,12 +565,12 @@ void cpu_init_f(void)
* which is their primary function.
* ~Jeremy
*/
- mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
- mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
- mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
- mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
- mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
- mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
+ mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
+ mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
+ mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
+ mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
/*
* dBug Compliance:
@@ -632,17 +608,8 @@ void cpu_init_f(void)
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
- /*
- * Setup chip selects...
- */
-
- mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
- mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
- mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
-
- mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
- mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
- mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
+ /* FlexBus Chipselect */
+ init_fbcs();
/* enable instruction cache now */
icache_enable();
@@ -659,7 +626,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
break;
case 1:
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c
index b8fb7bb..0181e4b 100644
--- a/cpu/mcf52x2/interrupts.c
+++ b/cpu/mcf52x2/interrupts.c
@@ -51,10 +51,10 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile intctrl_t *intp = (intctrl_t *) (CFG_INTR_BASE);
+ volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
- intp->int_icr1 |= CFG_TMRINTR_PRI;
+ intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI;
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
@@ -62,7 +62,7 @@ void dtimer_intr_setup(void)
#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrl0 |= 0x1;
@@ -74,11 +74,11 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
+ intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
intp->imrl0 &= 0xFFFFFFFE;
- intp->imrl0 &= ~CFG_TMRINTR_MASK;
+ intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
@@ -95,7 +95,7 @@ int interrupt_init(void)
void dtimer_intr_setup(void)
{
mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
- mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI);
+ mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI);
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index 4cb8f93..fe51fb4 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -39,11 +39,11 @@ int get_clocks (void)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
-#ifndef CFG_PLL_BYPASS
+#ifndef CONFIG_SYS_PLL_BYPASS
#ifdef CONFIG_M5249
/* Setup the PLL to run at the specified speed */
-#ifdef CFG_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
@@ -51,7 +51,7 @@ int get_clocks (void)
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
- pllcr = CFG_PLLCR;
+ pllcr = CONFIG_SYS_PLLCR;
#endif /* CONFIG_M5253 */
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
@@ -60,7 +60,7 @@ int get_clocks (void)
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
udelay(0x20); /* Wait for a lock ... */
-#endif /* #ifndef CFG_PLL_BYPASS */
+#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
@@ -76,7 +76,7 @@ int get_clocks (void)
;
#endif
- gd->cpu_clk = CFG_CLK;
+ gd->cpu_clk = CONFIG_SYS_CLK;
#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
#else
@@ -85,7 +85,7 @@ int get_clocks (void)
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
-#ifdef CFG_I2C2_OFFSET
+#ifdef CONFIG_SYS_I2C2_OFFSET
gd->i2c2_clk = gd->bus_clk;
#endif
#endif
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index 2e8ecfb..ba6b884 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -22,6 +22,7 @@
*/
#include <config.h>
+#include <timestamp.h>
#include "version.h"
#ifndef CONFIG_IDENT_STRING
@@ -56,7 +57,7 @@
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
.long _start - TEXT_BASE
#else
.long _START
@@ -103,9 +104,9 @@ _vectors:
.text
-#if defined(CFG_INT_FLASH_BASE) && \
+#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
(defined(CONFIG_M5282) || defined(CONFIG_M5281))
- #if (TEXT_BASE == CFG_INT_FLASH_BASE)
+ #if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
.long 0xFFFFFFFF /* all sectors protected */
.long 0x00000000 /* supervisor/User restriction */
@@ -120,44 +121,44 @@ _start:
move.w #0x2700,%sr
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
- move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
+ move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */
move.c %d0, %MBAR
/*** The 5249 has MBAR2 as well ***/
-#ifdef CFG_MBAR2
- move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */
+#ifdef CONFIG_SYS_MBAR2
+ move.l #(CONFIG_SYS_MBAR2 + 1), %d0 /* Get MBAR2 address */
movec %d0, #0xc0e /* Set MBAR2 */
#endif
- move.l #(CFG_INIT_RAM_ADDR + 1), %d0
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
movec %d0, %RAMBAR0
#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
/* Initialize IPSBAR */
- move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
+ move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
/* Initialize RAMBAR1: locate SRAM and validate it */
- move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#if defined(CONFIG_M5282)
-#if (TEXT_BASE == CFG_INT_FLASH_BASE)
+#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
- move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
- move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
- move.l #(CFG_INIT_RAM_ADDR), %a2
+ move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
+ move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2
_copy_flash:
move.l (%a0)+, (%a2)+
cmp.l %a0, %a1
bgt.s _copy_flash
- jmp CFG_INIT_RAM_ADDR
+ jmp CONFIG_SYS_INIT_RAM_ADDR
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
- move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
+ move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
@@ -165,9 +166,9 @@ _flashbar_setup_end:
_after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
- move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
+ move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
-#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
+#endif /* (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
#endif
#endif
@@ -175,22 +176,22 @@ _after_flashbar_copy:
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
-#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
- move.l #CFG_INT_FLASH_BASE, %d0
+#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+ move.l #CONFIG_SYS_INT_FLASH_BASE, %d0
#else
- move.l #CFG_FLASH_BASE, %d0
+ move.l #CONFIG_SYS_FLASH_BASE, %d0
#endif
movec %d0, %VBR
#endif
#ifdef CONFIG_M5275
/* Initialize IPSBAR */
- move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
+ move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
/* movec %d0, %MBAR */
/* Initialize RAMBAR: locate SRAM and validate it */
- move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#endif
@@ -204,7 +205,7 @@ _after_flashbar_copy:
#endif
/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
@@ -235,7 +236,7 @@ relocate_code:
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
- move.l #CFG_MONITOR_BASE, %a1
+ move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
@@ -249,7 +250,7 @@ relocate_code:
* initialization, now running from RAM.
*/
move.l %a0, %a1
- add.l #(in_ram - CFG_MONITOR_BASE), %a1
+ add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
@@ -259,9 +260,9 @@ clear_bss:
* Now clear BSS segment
*/
move.l %a0, %a1
- add.l #(_sbss - CFG_MONITOR_BASE),%a1
+ add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
- add.l #(_ebss - CFG_MONITOR_BASE),%d1
+ add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -271,11 +272,11 @@ clear_bss:
* fix got table in RAM
*/
move.l %a0, %a1
- add.l #(__got_start - CFG_MONITOR_BASE),%a1
+ add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
- add.l #(__got_end - CFG_MONITOR_BASE),%a2
+ add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
@@ -290,27 +291,27 @@ clear_bss:
/* quick and dirty */
move.l %a0,%d1
- add.l #(icache_state - CFG_MONITOR_BASE),%d1
+ add.l #(icache_state - CONFIG_SYS_MONITOR_BASE),%d1
move.l %a0,%a1
- add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
+ add.l #(icache_state_access_1+2 - CONFIG_SYS_MONITOR_BASE),%a1
move.l %d1,(%a1)
move.l %a0,%a1
- add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
+ add.l #(icache_state_access_2+2 - CONFIG_SYS_MONITOR_BASE),%a1
move.l %d1,(%a1)
move.l %a0,%a1
- add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
+ add.l #(icache_state_access_3+2 - CONFIG_SYS_MONITOR_BASE),%a1
move.l %d1,(%a1)
#endif
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
- add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+ add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
-#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
- defined(CFG_HALT_BEFOR_RAM_JUMP)
+#if defined(DEBUG) && (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
+ defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
halt
#endif
jsr (%a1)
@@ -344,14 +345,14 @@ _int_handler:
icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
- move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
+ move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
move.l #0x80000200, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
nop
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
@@ -474,6 +475,6 @@ dcache_status:
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
.align 4
diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c
index 20d0d5c..331cc15 100644
--- a/cpu/mcf532x/cpu.c
+++ b/cpu/mcf532x/cpu.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <netdev.h>
#include <asm/immap.h>
@@ -55,6 +56,24 @@ int checkcpu(void)
msk = (ccm->cir >> 6);
ver = (ccm->cir & 0x003f);
switch (msk) {
+#ifdef CONFIG_MCF5301x
+ case 0x78:
+ id = 53010;
+ break;
+ case 0x77:
+ id = 53012;
+ break;
+ case 0x76:
+ id = 53015;
+ break;
+ case 0x74:
+ id = 53011;
+ break;
+ case 0x73:
+ id = 53013;
+ break;
+#endif
+#ifdef CONFIG_MCF532x
case 0x54:
id = 5329;
break;
@@ -76,14 +95,17 @@ int checkcpu(void)
case 0x6B:
id = 5372;
break;
+#endif
}
if (id) {
+ char buf1[32], buf2[32];
+
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
ver);
- printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n",
- (int)(gd->cpu_clk / 1000000),
- (int)(gd->bus_clk / 1000000));
+ printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
+ strmhz(buf1, gd->cpu_clk),
+ strmhz(buf2, gd->bus_clk));
}
return 0;
@@ -116,7 +138,7 @@ int watchdog_init(void)
u32 wdog_module = 0;
/* set timeout and enable watchdog */
- wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
+ wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
#ifdef CONFIG_M5329
wdp->mr = (wdog_module / 8192);
#else
@@ -136,8 +158,6 @@ int watchdog_init(void)
* int board_eth_init(bd_t *bis)
*/
-extern int mcffec_initialize(bd_t*);
-
int cpu_eth_init(bd_t *bis)
{
return mcffec_initialize(bis);
diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c
index 93086f7..687c7e4 100644
--- a/cpu/mcf532x/cpu_init.c
+++ b/cpu/mcf532x/cpu_init.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,16 +27,188 @@
#include <common.h>
#include <watchdog.h>
-
#include <asm/immap.h>
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
+#ifdef CONFIG_MCF5301x
+void cpu_init_f(void)
+{
+ volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+ /* watchdog is enabled by default - disable the watchdog */
+#ifndef CONFIG_WATCHDOG
+ /*wdog->cr = 0; */
+#endif
+
+ scm1->mpr = 0x77777777;
+ scm1->pacra = 0;
+ scm1->pacrb = 0;
+ scm1->pacrc = 0;
+ scm1->pacrd = 0;
+ scm1->pacre = 0;
+ scm1->pacrf = 0;
+ scm1->pacrg = 0;
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+ && defined(CONFIG_SYS_CS0_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS0_CS0;
+ fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+ fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+ fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+ && defined(CONFIG_SYS_CS1_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS1_CS1;
+ fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+ fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+ fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+ && defined(CONFIG_SYS_CS2_CTRL))
+ fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+ fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+ fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+ && defined(CONFIG_SYS_CS3_CTRL))
+ fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+ fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+ fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+ && defined(CONFIG_SYS_CS4_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS4;
+ fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+ fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+ fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+ && defined(CONFIG_SYS_CS5_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS5;
+ fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+ fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+ fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+#endif
+
+#ifdef CONFIG_FSL_I2C
+ gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
+#endif
+
+ icache_enable();
+}
+
+/* initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+#ifdef CONFIG_MCFFEC
+ volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+#endif
+#ifdef CONFIG_MCFRTC
+ volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
+ volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
+
+ rtcex->gocu = CONFIG_SYS_RTC_CNT;
+ rtcex->gocl = CONFIG_SYS_RTC_SETUP;
+
+#endif
+#ifdef CONFIG_MCFFEC
+ if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
+ ccm->misccr |= CCM_MISCCR_FECM;
+ else
+ ccm->misccr &= ~CCM_MISCCR_FECM;
+#endif
+
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CONFIG_SYS_UART_PORT) {
+ case 0:
+ gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+ break;
+ case 1:
+#ifdef CONFIG_SYS_UART1_ALT1_GPIO
+ gpio->par_simp1h &=
+ ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK);
+ gpio->par_simp1h |=
+ (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
+#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
+ gpio->par_ssih &=
+ ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK);
+ gpio->par_ssih |=
+ (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
+#endif
+ break;
+ case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+ gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
+#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
+ gpio->par_dspih &=
+ ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK);
+ gpio->par_dspih |=
+ (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
+#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
+ gpio->par_feci2c &=
+ ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+ gpio->par_feci2c |=
+ (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+#endif
+ break;
+ }
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+
+ if (setclear) {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ gpio->par_fec |=
+ GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
+ gpio->par_feci2c |=
+ GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
+ } else {
+ gpio->par_fec |=
+ GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
+ gpio->par_feci2c |=
+ GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
+ }
+ } else {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ gpio->par_fec &=
+ ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
+ gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK;
+ } else {
+ gpio->par_fec &=
+ ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
+ gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK;
+ }
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_MCF5301x */
+
+#ifdef CONFIG_MCF532x
void cpu_init_f(void)
{
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
@@ -63,46 +235,52 @@ void cpu_init_f(void)
/* Port configuration */
gpio->par_cs = 0;
-#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
- fbcs->csar0 = CFG_CS0_BASE;
- fbcs->cscr0 = CFG_CS0_CTRL;
- fbcs->csmr0 = CFG_CS0_MASK;
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+ && defined(CONFIG_SYS_CS0_CTRL))
+ fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+ fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+ fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
-#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+ && defined(CONFIG_SYS_CS1_CTRL))
/* Latch chipselect */
gpio->par_cs |= GPIO_PAR_CS1;
- fbcs->csar1 = CFG_CS1_BASE;
- fbcs->cscr1 = CFG_CS1_CTRL;
- fbcs->csmr1 = CFG_CS1_MASK;
+ fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+ fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+ fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
-#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+ && defined(CONFIG_SYS_CS2_CTRL))
gpio->par_cs |= GPIO_PAR_CS2;
- fbcs->csar2 = CFG_CS2_BASE;
- fbcs->cscr2 = CFG_CS2_CTRL;
- fbcs->csmr2 = CFG_CS2_MASK;
+ fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+ fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+ fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
-#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+ && defined(CONFIG_SYS_CS3_CTRL))
gpio->par_cs |= GPIO_PAR_CS3;
- fbcs->csar3 = CFG_CS3_BASE;
- fbcs->cscr3 = CFG_CS3_CTRL;
- fbcs->csmr3 = CFG_CS3_MASK;
+ fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+ fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+ fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
-#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+ && defined(CONFIG_SYS_CS4_CTRL))
gpio->par_cs |= GPIO_PAR_CS4;
- fbcs->csar4 = CFG_CS4_BASE;
- fbcs->cscr4 = CFG_CS4_CTRL;
- fbcs->csmr4 = CFG_CS4_MASK;
+ fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+ fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+ fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
-#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+ && defined(CONFIG_SYS_CS5_CTRL))
gpio->par_cs |= GPIO_PAR_CS5;
- fbcs->csar5 = CFG_CS5_BASE;
- fbcs->cscr5 = CFG_CS5_CTRL;
- fbcs->csmr5 = CFG_CS5_MASK;
+ fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+ fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+ fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
#ifdef CONFIG_FSL_I2C
@@ -125,7 +303,7 @@ void uart_port_conf(void)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
break;
@@ -139,3 +317,22 @@ void uart_port_conf(void)
break;
}
}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if (setclear) {
+ gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
+ gpio->par_feci2c |=
+ GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
+ } else {
+ gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+ gpio->par_feci2c &=
+ ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
+ }
+ return 0;
+}
+#endif
+#endif /* CONFIG_MCF532x */
diff --git a/cpu/mcf532x/interrupts.c b/cpu/mcf532x/interrupts.c
index ff50d7d..d6c8205 100644
--- a/cpu/mcf532x/interrupts.c
+++ b/cpu/mcf532x/interrupts.c
@@ -28,7 +28,7 @@
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrh0 |= 0xFFFFFFFF;
@@ -41,9 +41,9 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
- intp->imrh0 &= ~CFG_TMRINTR_MASK;
+ intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
+ intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
}
#endif
diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c
index a11e425..0d378e6 100644
--- a/cpu/mcf532x/speed.c
+++ b/cpu/mcf532x/speed.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -36,26 +36,33 @@ DECLARE_GLOBAL_DATA_PTR;
#define MAX_FVCO 500000 /* KHz */
#define MAX_FSYS 80000 /* KHz */
#define MIN_FSYS 58333 /* KHz */
+
+#ifdef CONFIG_MCF5301x
+#define FREF 20000 /* KHz */
+#define MAX_MFD 63 /* Multiplier */
+#define MIN_MFD 0 /* Multiplier */
+#define USBDIV 8
+
+/* Low Power Divider specifications */
+#define MIN_LPD (0) /* Divider (not encoded) */
+#define MAX_LPD (15) /* Divider (not encoded) */
+#define DEFAULT_LPD (0) /* Divider (not encoded) */
+#endif
+
+#ifdef CONFIG_MCF532x
#define FREF 16000 /* KHz */
#define MAX_MFD 135 /* Multiplier */
#define MIN_MFD 88 /* Multiplier */
-#define BUSDIV 6 /* Divider */
-/*
- * Low Power Divider specifications
- */
+
+/* Low Power Divider specifications */
#define MIN_LPD (1 << 0) /* Divider (not encoded) */
#define MAX_LPD (1 << 15) /* Divider (not encoded) */
#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
+#endif
-/*
- * Get the value of the current system clock
- *
- * Parameters:
- * none
- *
- * Return Value:
- * The current output system frequency
- */
+#define BUSDIV 6 /* Divider */
+
+/* Get the value of the current system clock */
int get_sys_clock(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
@@ -65,9 +72,23 @@ int get_sys_clock(void)
/* Test to see if device is in LIMP mode */
if (ccm->misccr & CCM_MISCCR_LIMP) {
divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
+#ifdef CONFIG_MCF5301x
+ return (FREF / (3 * (1 << divider)));
+#endif
+#ifdef CONFIG_MCF532x
return (FREF / (2 << divider));
+#endif
} else {
+#ifdef CONFIG_MCF5301x
+ u32 pfdr = (pll->pcr & 0x3F) + 1;
+ u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
+ u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
+
+ return (((FREF * pfdr) / refdiv) / busdiv);
+#endif
+#ifdef CONFIG_MCF532x
return ((FREF * pll->pfdr) / (BUSDIV * 4));
+#endif
}
}
@@ -92,7 +113,7 @@ int clock_limp(int div)
div = MAX_LPD;
/* Save of the current value of the SSIDIV so we don't overwrite the value */
- temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF));
+ temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
/* Apply the divider to the system clock */
ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
@@ -102,15 +123,7 @@ int clock_limp(int div)
return (FREF / (3 * (1 << div)));
}
-/*
- * Exit low power LIMP mode
- *
- * Parameters:
- * div Desired system frequency divider
- *
- * Return Value:
- * The resulting output system frequency
- */
+/* Exit low power LIMP mode */
int clock_exit_limp(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
@@ -139,7 +152,10 @@ int clock_exit_limp(void)
*/
int clock_pll(int fsys, int flags)
{
+#ifdef CONFIG_MCF532x
volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
+#endif
+ volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
int fref, temp, fout, mfd;
u32 i;
@@ -148,9 +164,17 @@ int clock_pll(int fsys, int flags)
if (fsys == 0) {
/* Return current PLL output */
+#ifdef CONFIG_MCF5301x
+ u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
+ mfd = (pll->pcr & 0x3F) + 1;
+
+ return (fref * mfd) / busdiv;
+#endif
+#ifdef CONFIG_MCF532x
mfd = pll->pfdr;
return (fref * mfd / (BUSDIV * 4));
+#endif
}
/* Check bounds of requested system clock */
@@ -160,21 +184,33 @@ int clock_pll(int fsys, int flags)
if (fsys < MIN_FSYS)
fsys = MIN_FSYS;
- /* Multiplying by 100 when calculating the temp value,
- and then dividing by 100 to calculate the mfd allows
- for exact values without needing to include floating
- point libraries. */
+ /*
+ * Multiplying by 100 when calculating the temp value,
+ * and then dividing by 100 to calculate the mfd allows
+ * for exact values without needing to include floating
+ * point libraries.
+ */
temp = (100 * fsys) / fref;
+#ifdef CONFIG_MCF5301x
+ mfd = (BUSDIV * temp) / 100;
+
+ /* Determine the output frequency for selected values */
+ fout = ((fref * mfd) / BUSDIV);
+#endif
+#ifdef CONFIG_MCF532x
mfd = (4 * BUSDIV * temp) / 100;
/* Determine the output frequency for selected values */
fout = ((fref * mfd) / (BUSDIV * 4));
+#endif
/*
* Check to see if the SDRAM has already been initialized.
* If it has then the SDRAM needs to be put into self refresh
* mode before reprogramming the PLL.
*/
+ if (sdram->ctrl & SDRAMC_SDCR_REF)
+ sdram->ctrl &= ~SDRAMC_SDCR_CKE;
/*
* Initialize the PLL to generate the new system clock frequency.
@@ -184,20 +220,37 @@ int clock_pll(int fsys, int flags)
/* Enter LIMP mode */
clock_limp(DEFAULT_LPD);
+#ifdef CONFIG_MCF5301x
+ pll->pdr =
+ PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
+ PLL_PDR_OUTDIV2(BUSDIV - 1) |
+ PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
+ PLL_PDR_OUTDIV4(USBDIV - 1);
+
+ pll->pcr &= PLL_PCR_FBDIV_MASK;
+ pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
+#endif
+#ifdef CONFIG_MCF532x
/* Reprogram PLL for desired fsys */
pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
pll->pfdr = mfd;
+#endif
/* Exit LIMP mode */
clock_exit_limp();
+ /* Return the SDRAM to normal operation if it is in use. */
+ if (sdram->ctrl & SDRAMC_SDCR_REF)
+ sdram->ctrl |= SDRAMC_SDCR_CKE;
+
+#ifdef CONFIG_MCF532x
/*
- * Return the SDRAM to normal operation if it is in use.
+ * software workaround for SDRAM opeartion after exiting LIMP
+ * mode errata
*/
-
- /* software workaround for SDRAM opeartion after exiting LIMP mode errata */
- *sdram_workaround = CFG_SDRAM_BASE;
+ *sdram_workaround = CONFIG_SYS_SDRAM_BASE;
+#endif
/* wait for DQS logic to relock */
for (i = 0; i < 0x200; i++) ;
@@ -205,12 +258,10 @@ int clock_pll(int fsys, int flags)
return fout;
}
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
- gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000;
+ gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
gd->cpu_clk = (gd->bus_clk * 3);
#ifdef CONFIG_FSL_I2C
diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index c806f7a..a46c47a 100644
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -2,6 +2,9 @@
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
+ * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -22,6 +25,7 @@
*/
#include <config.h>
+#include <timestamp.h>
#include "version.h"
#ifndef CONFIG_IDENT_STRING
@@ -127,10 +131,10 @@ _start:
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
- move.l #CFG_FLASH_BASE, %d0
+ move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
@@ -140,16 +144,24 @@ _start:
movec %d0, %ACR0
movec %d0, %ACR1
+#ifdef CONFIG_MCF5301x
+ move.l #(0xFC0a0010), %a0
+ move.w (%a0), %d0
+ and.l %d0, 0xEFFF
+
+ move.w %d0, (%a0)
+#endif
+
/* initialize general use internal ram */
move.l #0, %d0
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2
move.l %d0, (%a1)
move.l %d0, (%a2)
/* set stackpointer to end of internal ram to get some stackspace for the
first c-code */
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
@@ -180,7 +192,7 @@ relocate_code:
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
- move.l #CFG_MONITOR_BASE, %a1
+ move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
@@ -195,7 +207,7 @@ relocate_code:
* initialization, now running from RAM.
*/
move.l %a0, %a1
- add.l #(in_ram - CFG_MONITOR_BASE), %a1
+ add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
@@ -205,9 +217,9 @@ clear_bss:
* Now clear BSS segment
*/
move.l %a0, %a1
- add.l #(_sbss - CFG_MONITOR_BASE),%a1
+ add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
- add.l #(_ebss - CFG_MONITOR_BASE),%d1
+ add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -217,11 +229,11 @@ clear_bss:
* fix got table in RAM
*/
move.l %a0, %a1
- add.l #(__got_start - CFG_MONITOR_BASE),%a1
+ add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
- add.l #(__got_end - CFG_MONITOR_BASE),%a2
+ add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
@@ -233,7 +245,7 @@ clear_bss:
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
- add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+ add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
@@ -268,14 +280,14 @@ _int_handler:
icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
- move.l #(CFG_SDRAM_BASE + 0x1c000), %d0
+ move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
movec %d0, %ACR0 /* Enable cache */
move.l #0x80000200, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
nop
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
@@ -288,14 +300,14 @@ icache_disable:
movec %d0, %ACR0
movec %d0, %ACR1
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
moveq #0, %d0
move.l %d0, (%a1)
rts
.globl icache_status
icache_status:
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
move.l (%a1), %d0
rts
@@ -307,7 +319,7 @@ icache_invalid:
.globl dcache_enable
dcache_enable:
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
@@ -315,14 +327,14 @@ dcache_enable:
/* No dcache, just a dummy function */
.globl dcache_disable
dcache_disable:
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
moveq #0, %d0
move.l %d0, (%a1)
rts
.globl dcache_status
dcache_status:
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
move.l (%a1), %d0
rts
@@ -331,6 +343,6 @@ dcache_status:
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
.align 4
diff --git a/cpu/mcf5445x/cpu.c b/cpu/mcf5445x/cpu.c
index ab342dd..6238bc0 100644
--- a/cpu/mcf5445x/cpu.c
+++ b/cpu/mcf5445x/cpu.c
@@ -28,6 +28,7 @@
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <netdev.h>
#include <asm/immap.h>
@@ -75,21 +76,23 @@ int checkcpu(void)
}
if (id) {
+ char buf1[32], buf2[32], buf3[32];
+
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
ver);
- printf(" CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n",
- (int)(gd->cpu_clk / 1000000),
- (int)(gd->bus_clk / 1000000),
- (int)(gd->flb_clk / 1000000));
+ printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
+ strmhz(buf1, gd->cpu_clk),
+ strmhz(buf2, gd->bus_clk),
+ strmhz(buf3, gd->flb_clk));
#ifdef CONFIG_PCI
- printf(" PCI CLK %d Mhz INP CLK %d Mhz VCO CLK %d Mhz\n",
- (int)(gd->pci_clk / 1000000),
- (int)(gd->inp_clk / 1000000),
- (int)(gd->vco_clk / 1000000));
+ printf(" PCI CLK %s MHz INP CLK %s MHz VCO CLK %s MHz\n",
+ strmhz(buf1, gd->pci_clk),
+ strmhz(buf2, gd->inp_clk),
+ strmhz(buf3, gd->vco_clk));
#else
- printf(" INP CLK %d Mhz VCO CLK %d Mhz\n",
- (int)(gd->inp_clk / 1000000),
- (int)(gd->vco_clk / 1000000));
+ printf(" INP CLK %s MHz VCO CLK %s MHz\n",
+ strmhz(buf1, gd->inp_clk),
+ strmhz(buf2, gd->vco_clk));
#endif
}
@@ -102,8 +105,6 @@ int checkcpu(void)
* int board_eth_init(bd_t *bis)
*/
-extern int mcffec_initialize(bd_t*);
-
int cpu_eth_init(bd_t *bis)
{
return mcffec_initialize(bis);
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index 51a9e90..7e04e32 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -27,10 +27,15 @@
#include <common.h>
#include <watchdog.h>
-
#include <asm/immap.h>
#include <asm/rtc.h>
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
/*
* Breath some life into the CPU...
*
@@ -62,42 +67,42 @@ void cpu_init_f(void)
GPIO_PAR_FBCTL_TS_TS;
#if !defined(CONFIG_CF_SBF)
-#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
- fbcs->csar0 = CFG_CS0_BASE;
- fbcs->cscr0 = CFG_CS0_CTRL;
- fbcs->csmr0 = CFG_CS0_MASK;
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+ fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+ fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+ fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
#endif
-#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
/* Latch chipselect */
- fbcs->csar1 = CFG_CS1_BASE;
- fbcs->cscr1 = CFG_CS1_CTRL;
- fbcs->csmr1 = CFG_CS1_MASK;
+ fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+ fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+ fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
-#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
- fbcs->csar2 = CFG_CS2_BASE;
- fbcs->cscr2 = CFG_CS2_CTRL;
- fbcs->csmr2 = CFG_CS2_MASK;
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+ fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+ fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+ fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
-#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
- fbcs->csar3 = CFG_CS3_BASE;
- fbcs->cscr3 = CFG_CS3_CTRL;
- fbcs->csmr3 = CFG_CS3_MASK;
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+ fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+ fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+ fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
-#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
- fbcs->csar4 = CFG_CS4_BASE;
- fbcs->cscr4 = CFG_CS4_CTRL;
- fbcs->csmr4 = CFG_CS4_MASK;
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
+ fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+ fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+ fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
-#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
- fbcs->csar5 = CFG_CS5_BASE;
- fbcs->cscr5 = CFG_CS5_CTRL;
- fbcs->csmr5 = CFG_CS5_MASK;
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
+ fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+ fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+ fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
#ifdef CONFIG_FSL_I2C
@@ -113,11 +118,11 @@ void cpu_init_f(void)
int cpu_init_r(void)
{
#ifdef CONFIG_MCFRTC
- volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
+ volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
- rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
- rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
+ rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
+ rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
#endif
return (0);
@@ -128,7 +133,7 @@ void uart_port_conf(void)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->par_uart =
(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
@@ -139,3 +144,30 @@ void uart_port_conf(void)
break;
}
}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+
+ if (setclear) {
+ gpio->par_feci2c |=
+ (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+ gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
+ else
+ gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
+ } else {
+ gpio->par_feci2c &=
+ ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+ gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
+ else
+ gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
+ }
+ return 0;
+}
+#endif
diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c
index 959d6bd..6d3ebab 100644
--- a/cpu/mcf5445x/dspi.c
+++ b/cpu/mcf5445x/dspi.c
@@ -47,29 +47,29 @@ void dspi_init(void)
DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
-#ifdef CFG_DSPI_DCTAR0
- dspi->dctar0 = CFG_DSPI_DCTAR0;
+#ifdef CONFIG_SYS_DSPI_DCTAR0
+ dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
#endif
-#ifdef CFG_DSPI_DCTAR1
- dspi->dctar1 = CFG_DSPI_DCTAR1;
+#ifdef CONFIG_SYS_DSPI_DCTAR1
+ dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
#endif
-#ifdef CFG_DSPI_DCTAR2
- dspi->dctar2 = CFG_DSPI_DCTAR2;
+#ifdef CONFIG_SYS_DSPI_DCTAR2
+ dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
#endif
-#ifdef CFG_DSPI_DCTAR3
- dspi->dctar3 = CFG_DSPI_DCTAR3;
+#ifdef CONFIG_SYS_DSPI_DCTAR3
+ dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
#endif
-#ifdef CFG_DSPI_DCTAR4
- dspi->dctar4 = CFG_DSPI_DCTAR4;
+#ifdef CONFIG_SYS_DSPI_DCTAR4
+ dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
#endif
-#ifdef CFG_DSPI_DCTAR5
- dspi->dctar5 = CFG_DSPI_DCTAR5;
+#ifdef CONFIG_SYS_DSPI_DCTAR5
+ dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
#endif
-#ifdef CFG_DSPI_DCTAR6
- dspi->dctar6 = CFG_DSPI_DCTAR6;
+#ifdef CONFIG_SYS_DSPI_DCTAR6
+ dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
#endif
-#ifdef CFG_DSPI_DCTAR7
- dspi->dctar7 = CFG_DSPI_DCTAR7;
+#ifdef CONFIG_SYS_DSPI_DCTAR7
+ dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
#endif
}
diff --git a/cpu/mcf5445x/interrupts.c b/cpu/mcf5445x/interrupts.c
index 9572a7b..85828a6 100644
--- a/cpu/mcf5445x/interrupts.c
+++ b/cpu/mcf5445x/interrupts.c
@@ -31,7 +31,7 @@
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrh0 |= 0xFFFFFFFF;
@@ -44,9 +44,9 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
- intp->imrh0 &= ~CFG_TMRINTR_MASK;
+ intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
+ intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
}
#endif
diff --git a/cpu/mcf5445x/pci.c b/cpu/mcf5445x/pci.c
index 0398469..c4a3b05 100644
--- a/cpu/mcf5445x/pci.c
+++ b/cpu/mcf5445x/pci.c
@@ -31,9 +31,9 @@
#if defined(CONFIG_PCI)
/* System RAM mapped over PCI */
-#define CFG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
-#define CFG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
-#define CFG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
+#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
#define cfg_read(val, addr, type, op) *val = op((type)(addr));
#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
@@ -80,9 +80,9 @@ void pci_mcf5445x_init(struct pci_controller *hose)
pci->tcr1 |= PCI_TCR1_P;
/* Initiator windows */
- pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
- pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
- pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
+ pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
+ pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
+ pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
pci->iwcr =
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
@@ -97,34 +97,34 @@ void pci_mcf5445x_init(struct pci_controller *hose)
pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
pci->cr2 = 0;
-#ifdef CFG_PCI_BAR0
- pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
- pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR0
+ pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
+ pci->tbatr0 = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B0E;
#endif
-#ifdef CFG_PCI_BAR1
- pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
- pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR1
+ pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
+ pci->tbatr1 = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B1E;
#endif
-#ifdef CFG_PCI_BAR2
- pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2);
- pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR2
+ pci->bar2 = PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2);
+ pci->tbatr2 = CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B2E;
#endif
-#ifdef CFG_PCI_BAR3
- pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3);
- pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR3
+ pci->bar3 = PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3);
+ pci->tbatr3 = CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B3E;
#endif
-#ifdef CFG_PCI_BAR4
- pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4);
- pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR4
+ pci->bar4 = PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4);
+ pci->tbatr4 = CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B4E;
#endif
-#ifdef CFG_PCI_BAR5
- pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5);
- pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR5
+ pci->bar5 = PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5);
+ pci->tbatr5 = CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B5E;
#endif
@@ -138,20 +138,20 @@ void pci_mcf5445x_init(struct pci_controller *hose)
hose->first_busno = 0;
hose->last_busno = 0xff;
- pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
- CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
+ pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
+ CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
- pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
- CFG_PCI_IO_SIZE, PCI_REGION_IO);
+ pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
+ CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
- pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
- CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
+ pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
+ CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
hose->region_count = 3;
hose->cfg_addr = &(pci->car);
- hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;
+ hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
diff --git a/cpu/mcf5445x/speed.c b/cpu/mcf5445x/speed.c
index 6711a1d..9c0c077 100644
--- a/cpu/mcf5445x/speed.c
+++ b/cpu/mcf5445x/speed.c
@@ -94,7 +94,7 @@ int get_clocks(void)
u16 fbpll_mask;
#ifdef CONFIG_M54455EVB
- volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3);
+ volatile u8 *cpld = (volatile u8 *)(CONFIG_SYS_CS2_BASE + 3);
#endif
u8 bootmode;
@@ -145,7 +145,7 @@ int get_clocks(void)
if (bootmode == 0) {
/* RCON mode */
- vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC;
+ vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
/* invaild range, re-set in PCR */
@@ -154,7 +154,7 @@ int get_clocks(void)
j = (pll->pcr & 0xFF000000) >> 24;
for (i = j; i < 0xFF; i++) {
- vco = i * CFG_INPUT_CLKSRC;
+ vco = i * CONFIG_SYS_INPUT_CLKSRC;
if (vco >= CLOCK_PLL_FVCO_MIN) {
bus = vco / temp;
if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
@@ -172,25 +172,25 @@ int get_clocks(void)
gd->vco_clk = vco; /* Vco clock */
} else if (bootmode == 2) {
/* Normal mode */
- vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC;
+ vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
/* Default value */
pcrvalue = (pll->pcr & 0x00FFFFFF);
pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24;
pll->pcr = pcrvalue;
- vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC;
+ vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
}
gd->vco_clk = vco; /* Vco clock */
} else if (bootmode == 3) {
/* serial mode */
- vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC;
+ vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
gd->vco_clk = vco; /* Vco clock */
}
if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */
} else {
- gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */
+ gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index 2a6019b..d5a7f93 100644
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -22,6 +22,7 @@
*/
#include <config.h>
+#include <timestamp.h>
#include "version.h"
#ifndef CONFIG_IDENT_STRING
@@ -29,9 +30,9 @@
#endif
/* last three long word reserved for cache status */
-#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
-#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
-#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
+#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
#define _START _start
#define _FAULT _fault
@@ -47,8 +48,8 @@
rte;
#if defined(CONFIG_CF_SBF)
-#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CFG_INIT_RAM_ADDR)
-#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CFG_INIT_RAM_ADDR)
+#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#endif
.text
@@ -149,18 +150,18 @@ asm_sbf_img_hdr:
.long TEXT_BASE /* image to be relocated at */
asm_dram_init:
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1 /* init Rambar */
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
/* Must disable global address */
move.l #0xFC008000, %a1
- move.l #(CFG_CS0_BASE), (%a1)
+ move.l #(CONFIG_SYS_CS0_BASE), (%a1)
move.l #0xFC008008, %a1
- move.l #(CFG_CS0_CTRL), (%a1)
+ move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
- move.l #(CFG_CS0_MASK), (%a1)
+ move.l #(CONFIG_SYS_CS0_MASK), (%a1)
/*
* Dram Initialization
@@ -168,7 +169,7 @@ asm_dram_init:
*/
/* mscr sdram */
move.l #0xFC0A4074, %a1
- move.b #(CFG_SDRAM_DRV_STRENGTH), (%a1)
+ move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
nop
/* SDRAM Chip 0 and 1 */
@@ -177,8 +178,8 @@ asm_dram_init:
/* calculate the size */
move.l #0x13, %d1
- move.l #(CFG_SDRAM_SIZE), %d2
-#ifdef CFG_SDRAM_BASE1
+ move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
+#ifdef CONFIG_SYS_SDRAM_BASE1
lsr.l #1, %d2
#endif
@@ -189,20 +190,20 @@ dramsz_loop:
bne dramsz_loop
/* SDRAM Chip 0 and 1 */
- move.l #(CFG_SDRAM_BASE), (%a1)
+ move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
or.l %d1, (%a1)
-#ifdef CFG_SDRAM_BASE1
- move.l #(CFG_SDRAM_BASE1), (%a2)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+ move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
or.l %d1, (%a2)
#endif
nop
/* dram cfg1 and cfg2 */
move.l #0xFC0B8008, %a1
- move.l #(CFG_SDRAM_CFG1), (%a1)
+ move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
nop
move.l #0xFC0B800C, %a2
- move.l #(CFG_SDRAM_CFG2), (%a2)
+ move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
nop
move.l #0xFC0B8000, %a1 /* Mode */
@@ -210,13 +211,13 @@ dramsz_loop:
#ifdef CONFIG_M54455EVB
/* Issue PALL */
- move.l #(CFG_SDRAM_CTRL + 2), (%a2)
+ move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
nop
/* Issue LEMR */
- move.l #(CFG_SDRAM_EMOD + 0x408), (%a1)
+ move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
nop
- move.l #(CFG_SDRAM_MODE + 0x300), (%a1)
+ move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
nop
move.l #1000, %d0
@@ -227,24 +228,24 @@ wait1000:
#endif
/* Issue PALL */
- move.l #(CFG_SDRAM_CTRL + 2), (%a2)
+ move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
nop
/* Perform two refresh cycles */
- move.l #(CFG_SDRAM_CTRL + 4), %d0
+ move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
nop
move.l %d0, (%a2)
move.l %d0, (%a2)
nop
#ifdef CONFIG_M54455EVB
- move.l #(CFG_SDRAM_MODE + 0x200), (%a1)
+ move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
nop
#elif defined(CONFIG_M54451EVB)
/* Issue LEMR */
- move.l #(CFG_SDRAM_MODE), (%a2)
+ move.l #(CONFIG_SYS_SDRAM_MODE), (%a2)
nop
- move.l #(CFG_SDRAM_EMOD), (%a2)
+ move.l #(CONFIG_SYS_SDRAM_EMOD), (%a2)
nop
#endif
@@ -254,7 +255,7 @@ wait500:
subq.l #1, %d0
bne wait500
- move.l #(CFG_SDRAM_CTRL), %d0
+ move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
and.l #0x7FFFFFFF, %d0
#ifdef CONFIG_M54455EVB
or.l #0x10000c00, %d0
@@ -290,8 +291,8 @@ wait500:
move.l (%a1)+, %d5
move.l (%a1), %a4
- move.l #(CFG_INIT_RAM_ADDR + CFG_SBFHDR_DATA_OFFSET), %a0
- move.l #(CFG_SBFHDR_SIZE), %d4
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
+ move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
move.l #0xFC05C02C, %a1 /* dspi status */
@@ -381,10 +382,10 @@ _start:
move.l #TEXT_BASE, %d0
movec %d0, %VBR
#else
- move.l #CFG_FLASH_BASE, %d0
+ move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
@@ -408,7 +409,7 @@ _start:
/* set stackpointer to end of internal ram to get some stackspace for
the first c-code */
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
@@ -439,7 +440,7 @@ relocate_code:
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
- move.l #CFG_MONITOR_BASE, %a1
+ move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
@@ -454,7 +455,7 @@ relocate_code:
* initialization, now running from RAM.
*/
move.l %a0, %a1
- add.l #(in_ram - CFG_MONITOR_BASE), %a1
+ add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
@@ -464,9 +465,9 @@ clear_bss:
* Now clear BSS segment
*/
move.l %a0, %a1
- add.l #(_sbss - CFG_MONITOR_BASE),%a1
+ add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
- add.l #(_ebss - CFG_MONITOR_BASE),%d1
+ add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -476,11 +477,11 @@ clear_bss:
* fix got table in RAM
*/
move.l %a0, %a1
- add.l #(__got_start - CFG_MONITOR_BASE),%a1
+ add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
- add.l #(__got_end - CFG_MONITOR_BASE),%a2
+ add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
@@ -492,7 +493,7 @@ clear_bss:
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
- add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+ add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
@@ -531,7 +532,7 @@ icache_enable:
move.l #0x00040100, %d0 /* Invalidate icache */
movec %d0, %CACR
- move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */
+ move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */
movec %d0, %ACR2
move.l #0x04088020, %d0 /* Enable bcache and icache */
@@ -627,6 +628,6 @@ dcache_status:
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
.align 4
diff --git a/cpu/mcf547x_8x/cpu.c b/cpu/mcf547x_8x/cpu.c
index 1ba7aa8..3912a74 100644
--- a/cpu/mcf547x_8x/cpu.c
+++ b/cpu/mcf547x_8x/cpu.c
@@ -28,6 +28,7 @@
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <netdev.h>
#include <asm/immap.h>
@@ -95,10 +96,12 @@ int checkcpu(void)
}
if (id) {
+ char buf1[32], buf2[32];
+
printf("Freescale MCF%d\n", id);
- printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n",
- (int)(gd->cpu_clk / 1000000),
- (int)(gd->bus_clk / 1000000));
+ printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
+ strmhz(buf1, gd->cpu_clk),
+ strmhz(buf2, gd->bus_clk));
}
return 0;
@@ -132,7 +135,7 @@ int watchdog_init(void)
volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
gptmr->pre = CONFIG_WATCHDOG_TIMEOUT;
- gptmr->cnt = CFG_TIMER_PRESCALER * 1000;
+ gptmr->cnt = CONFIG_SYS_TIMER_PRESCALER * 1000;
gptmr->mode = GPT_TMS_SGPIO;
gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN;
@@ -148,9 +151,6 @@ int watchdog_init(void)
* int board_eth_init(bd_t *bis)
*/
-extern int mcdmafec_initialize(bd_t *bis);
-extern int mcffec_initialize(bd_t*);
-
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSLDMAFEC)
diff --git a/cpu/mcf547x_8x/cpu_init.c b/cpu/mcf547x_8x/cpu_init.c
index 11154c6..1ba5783 100644
--- a/cpu/mcf547x_8x/cpu_init.c
+++ b/cpu/mcf547x_8x/cpu_init.c
@@ -29,6 +29,12 @@
#include <MCD_dma.h>
#include <asm/immap.h>
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fsl_mcdmafec.h>
+#endif
+
/*
* Breath some life into the CPU...
*
@@ -52,40 +58,40 @@ void cpu_init_f(void)
xlbarb->pri = 0;
xlbarb->prien = 0xff;
-#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
- fbcs->csar0 = CFG_CS0_BASE;
- fbcs->cscr0 = CFG_CS0_CTRL;
- fbcs->csmr0 = CFG_CS0_MASK;
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+ fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+ fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+ fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
-#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
- fbcs->csar1 = CFG_CS1_BASE;
- fbcs->cscr1 = CFG_CS1_CTRL;
- fbcs->csmr1 = CFG_CS1_MASK;
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+ fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+ fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+ fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
-#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
- fbcs->csar2 = CFG_CS2_BASE;
- fbcs->cscr2 = CFG_CS2_CTRL;
- fbcs->csmr2 = CFG_CS2_MASK;
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+ fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+ fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+ fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
-#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
- fbcs->csar3 = CFG_CS3_BASE;
- fbcs->cscr3 = CFG_CS3_CTRL;
- fbcs->csmr3 = CFG_CS3_MASK;
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+ fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+ fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+ fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
-#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
- fbcs->csar4 = CFG_CS4_BASE;
- fbcs->cscr4 = CFG_CS4_CTRL;
- fbcs->csmr4 = CFG_CS4_MASK;
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
+ fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+ fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+ fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
-#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
- fbcs->csar5 = CFG_CS5_BASE;
- fbcs->cscr5 = CFG_CS5_CTRL;
- fbcs->csmr5 = CFG_CS5_MASK;
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
+ fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+ fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+ fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
#ifdef CONFIG_FSL_I2C
@@ -110,10 +116,10 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile u8 *pscsicr = (u8 *) (CFG_UART_BASE + 0x40);
+ volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
break;
@@ -130,3 +136,24 @@ void uart_port_conf(void)
*pscsicr &= 0xF8;
}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
+
+ if (setclear) {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+ gpio->par_feci2cirq |= 0xF000;
+ else
+ gpio->par_feci2cirq |= 0x0FC0;
+ } else {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+ gpio->par_feci2cirq &= 0x0FFF;
+ else
+ gpio->par_feci2cirq &= 0xF03F;
+ }
+ return 0;
+}
+#endif
diff --git a/cpu/mcf547x_8x/interrupts.c b/cpu/mcf547x_8x/interrupts.c
index d684ffe..76be876 100644
--- a/cpu/mcf547x_8x/interrupts.c
+++ b/cpu/mcf547x_8x/interrupts.c
@@ -28,7 +28,7 @@
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrh0 |= 0xFFFFFFFF;
@@ -42,9 +42,9 @@ int interrupt_init(void)
#if defined(CONFIG_SLTTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
- intp->imrh0 &= ~CFG_TMRINTR_MASK;
+ intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
+ intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
}
#endif
diff --git a/cpu/mcf547x_8x/pci.c b/cpu/mcf547x_8x/pci.c
index 70378b0..f5c2536 100644
--- a/cpu/mcf547x_8x/pci.c
+++ b/cpu/mcf547x_8x/pci.c
@@ -31,9 +31,9 @@
#if defined(CONFIG_PCI)
/* System RAM mapped over PCI */
-#define CFG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
-#define CFG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
-#define CFG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
+#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
#define cfg_read(val, addr, type, op) *val = op((type)(addr));
#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
@@ -107,9 +107,9 @@ void pci_mcf547x_8x_init(struct pci_controller *hose)
pci->tcr1 = PCI_TCR1_P;
/* Initiator windows */
- pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
- pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
- pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
+ pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
+ pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
+ pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
pci->iwcr =
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
@@ -124,13 +124,13 @@ void pci_mcf547x_8x_init(struct pci_controller *hose)
pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
pci->cr2 = 0;
-#ifdef CFG_PCI_BAR0
- pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
- pci->tbatr0a = CFG_PCI_TBATR0 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR0
+ pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
+ pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
#endif
-#ifdef CFG_PCI_BAR1
- pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
- pci->tbatr1a = CFG_PCI_TBATR1 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR1
+ pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
+ pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
#endif
/* Deassert reset bit */
@@ -141,20 +141,20 @@ void pci_mcf547x_8x_init(struct pci_controller *hose)
hose->first_busno = 0;
hose->last_busno = 0xff;
- pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
- CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
+ pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
+ CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
- pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
- CFG_PCI_IO_SIZE, PCI_REGION_IO);
+ pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
+ CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
- pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
- CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
+ pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
+ CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
hose->region_count = 3;
hose->cfg_addr = &(pci->car);
- hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;
+ hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
diff --git a/cpu/mcf547x_8x/slicetimer.c b/cpu/mcf547x_8x/slicetimer.c
index 494f98f..67e8189 100644
--- a/cpu/mcf547x_8x/slicetimer.c
+++ b/cpu/mcf547x_8x/slicetimer.c
@@ -31,22 +31,22 @@ DECLARE_GLOBAL_DATA_PTR;
static ulong timestamp;
#if defined(CONFIG_SLTTMR)
-#ifndef CFG_UDELAY_BASE
+#ifndef CONFIG_SYS_UDELAY_BASE
# error "uDelay base not defined!"
#endif
-#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK)
+#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
#endif
extern void dtimer_intr_setup(void);
void udelay(unsigned long usec)
{
- volatile slt_t *timerp = (slt_t *) (CFG_UDELAY_BASE);
+ volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
u32 now, freq;
/* 1 us period */
- freq = CFG_TIMER_PRESCALER;
+ freq = CONFIG_SYS_TIMER_PRESCALER;
timerp->cr = 0; /* Disable */
timerp->tcnt = usec * freq;
@@ -62,10 +62,10 @@ void udelay(unsigned long usec)
void dtimer_interrupt(void *not_used)
{
- volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE);
+ volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
/* check for timer interrupt asserted */
- if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) {
+ if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
timerp->sr |= SLT_SR_ST;
timestamp++;
return;
@@ -74,7 +74,7 @@ void dtimer_interrupt(void *not_used)
void timer_init(void)
{
- volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE);
+ volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
timestamp = 0;
@@ -83,10 +83,10 @@ void timer_init(void)
timerp->sr = SLT_SR_BE | SLT_SR_ST; /* clear status */
/* initialize and enable timer interrupt */
- irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0);
+ irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
/* Interrupt every ms */
- timerp->tcnt = 1000 * CFG_TIMER_PRESCALER;
+ timerp->tcnt = 1000 * CONFIG_SYS_TIMER_PRESCALER;
dtimer_intr_setup();
diff --git a/cpu/mcf547x_8x/speed.c b/cpu/mcf547x_8x/speed.c
index 28fe657..2cee488 100644
--- a/cpu/mcf547x_8x/speed.c
+++ b/cpu/mcf547x_8x/speed.c
@@ -37,7 +37,7 @@ int get_clocks(void)
{
DECLARE_GLOBAL_DATA_PTR;
- gd->bus_clk = CFG_CLK;
+ gd->bus_clk = CONFIG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_FSL_I2C
diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S
index 87355f9..94ef14b 100644
--- a/cpu/mcf547x_8x/start.S
+++ b/cpu/mcf547x_8x/start.S
@@ -22,6 +22,7 @@
*/
#include <config.h>
+#include <timestamp.h>
#include "version.h"
#ifndef CONFIG_IDENT_STRING
@@ -29,9 +30,9 @@
#endif
/* last three long word reserved for cache status */
-#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
-#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
-#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
+#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
#define _START _start
#define _FAULT _fault
@@ -132,16 +133,16 @@ _start:
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
- move.l #CFG_FLASH_BASE, %d0
+ move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR0
- move.l #(CFG_INIT_RAM1_ADDR + CFG_INIT_RAM1_CTRL), %d0
+ move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0
movec %d0, %RAMBAR1
- move.l #CFG_MBAR, %d0 /* set MBAR address */
+ move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */
move.c %d0, %MBAR
/* invalidate and disable cache */
@@ -164,7 +165,7 @@ _start:
/* set stackpointer to end of internal ram to get some stackspace for the
first c-code */
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
@@ -195,7 +196,7 @@ relocate_code:
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
- move.l #CFG_MONITOR_BASE, %a1
+ move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
@@ -210,7 +211,7 @@ relocate_code:
* initialization, now running from RAM.
*/
move.l %a0, %a1
- add.l #(in_ram - CFG_MONITOR_BASE), %a1
+ add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
@@ -220,9 +221,9 @@ clear_bss:
* Now clear BSS segment
*/
move.l %a0, %a1
- add.l #(_sbss - CFG_MONITOR_BASE),%a1
+ add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
- add.l #(_ebss - CFG_MONITOR_BASE),%d1
+ add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -232,11 +233,11 @@ clear_bss:
* fix got table in RAM
*/
move.l %a0, %a1
- add.l #(__got_start - CFG_MONITOR_BASE),%a1
+ add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
- add.l #(__got_end - CFG_MONITOR_BASE),%a2
+ add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
@@ -248,7 +249,7 @@ clear_bss:
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
- add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+ add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
@@ -281,7 +282,7 @@ _int_handler:
/* cache functions */
.globl icache_enable
icache_enable:
- move.l #(CFG_SDRAM_BASE + 0x1c000), %d0
+ move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
movec %d0, %ACR2 /* Enable cache */
move.l #0x020C8100, %d0 /* Setup cache mask */
@@ -322,7 +323,7 @@ icache_status:
dcache_enable:
bsr icache_disable
- move.l #(CFG_SDRAM_BASE + 0xc000), %d0
+ move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0
movec %d0, %ACR0 /* Enable cache */
move.l #0xA30C8100, %d0 /* Invalidate cache cmd */
@@ -357,6 +358,6 @@ dcache_status:
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
.align 4
diff --git a/cpu/microblaze/exception.c b/cpu/microblaze/exception.c
index d76b05a..0365de3 100644
--- a/cpu/microblaze/exception.c
+++ b/cpu/microblaze/exception.c
@@ -65,7 +65,7 @@ void _hw_exception_handler (void)
hang ();
}
-#ifdef CFG_USR_EXCEP
+#ifdef CONFIG_SYS_USR_EXCEP
void _exception_handler (void)
{
puts ("User vector_exception\n");
diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
index 26e88cb..a6021c9 100644
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -45,19 +45,19 @@ int disable_interrupts (void)
return 0;
}
-#ifdef CFG_INTC_0
-#ifdef CFG_TIMER_0
+#ifdef CONFIG_SYS_INTC_0
+#ifdef CONFIG_SYS_TIMER_0
extern void timer_init (void);
#endif
-#ifdef CFG_FSL_2
+#ifdef CONFIG_SYS_FSL_2
extern void fsl_init2 (void);
#endif
-static struct irq_action vecs[CFG_INTC_0_NUM];
+static struct irq_action vecs[CONFIG_SYS_INTC_0_NUM];
/* mapping structure to interrupt controller */
-microblaze_intc_t *intc = (microblaze_intc_t *) (CFG_INTC_0_ADDR);
+microblaze_intc_t *intc = (microblaze_intc_t *) (CONFIG_SYS_INTC_0_ADDR);
/* default handler */
void def_hdlr (void)
@@ -100,7 +100,7 @@ void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg)
{
struct irq_action *act;
/* irq out of range */
- if ((irq < 0) || (irq > CFG_INTC_0_NUM)) {
+ if ((irq < 0) || (irq > CONFIG_SYS_INTC_0_NUM)) {
puts ("IRQ out of range\n");
return;
}
@@ -135,17 +135,17 @@ int interrupts_init (void)
{
int i;
/* initialize irq list */
- for (i = 0; i < CFG_INTC_0_NUM; i++) {
+ for (i = 0; i < CONFIG_SYS_INTC_0_NUM; i++) {
vecs[i].handler = (interrupt_handler_t *) def_hdlr;
vecs[i].arg = (void *)i;
vecs[i].count = 0;
}
/* initialize intc controller */
intc_init ();
-#ifdef CFG_TIMER_0
+#ifdef CONFIG_SYS_TIMER_0
timer_init ();
#endif
-#ifdef CFG_FSL_2
+#ifdef CONFIG_SYS_FSL_2
fsl_init2 ();
#endif
enable_interrupts ();
@@ -191,7 +191,7 @@ void interrupt_handler (void)
#endif
#if defined(CONFIG_CMD_IRQ)
-#ifdef CFG_INTC_0
+#ifdef CONFIG_SYS_INTC_0
int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int i;
@@ -201,7 +201,7 @@ int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
"Nr Routine Arg Count\n"
"-----------------------------\n");
- for (i = 0; i < CFG_INTC_0_NUM; i++) {
+ for (i = 0; i < CONFIG_SYS_INTC_0_NUM; i++) {
if (act->handler != (interrupt_handler_t*) def_hdlr) {
printf ("%02d %08x %08x %d\n", i,
(int)act->handler, (int)act->arg, act->count);
diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S
index 8740284..2e9a08d 100644
--- a/cpu/microblaze/start.S
+++ b/cpu/microblaze/start.S
@@ -30,7 +30,7 @@
.global _start
_start:
mts rmsr, r0 /* disable cache */
- addi r1, r0, CFG_INIT_SP_OFFSET
+ addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
addi r1, r1, -4 /* Decrement SP to top of memory */
/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
@@ -45,9 +45,9 @@ _start:
swi r6, r0, 0x14 /* interrupt */
swi r6, r0, 0x24 /* hardware exception */
-#ifdef CFG_RESET_ADDRESS
+#ifdef CONFIG_SYS_RESET_ADDRESS
/* reset address */
- addik r6, r0, CFG_RESET_ADDRESS
+ addik r6, r0, CONFIG_SYS_RESET_ADDRESS
sw r6, r1, r0
lhu r7, r1, r0
shi r7, r0, 0x2
@@ -56,11 +56,11 @@ _start:
* Copy U-Boot code to TEXT_BASE
* solve problem with sbrk_base
*/
-#if (CFG_RESET_ADDRESS != TEXT_BASE)
+#if (CONFIG_SYS_RESET_ADDRESS != TEXT_BASE)
addi r4, r0, __end
addi r5, r0, __text_start
rsub r4, r5, r4 /* size = __end - __text_start */
- addi r6, r0, CFG_RESET_ADDRESS /* source address */
+ addi r6, r0, CONFIG_SYS_RESET_ADDRESS /* source address */
addi r7, r0, 0 /* counter */
4:
lw r8, r6, r7
@@ -71,7 +71,7 @@ _start:
#endif
#endif
-#ifdef CFG_USR_EXCEP
+#ifdef CONFIG_SYS_USR_EXCEP
/* user_vector_exception */
addik r6, r0, _exception_handler
sw r6, r1, r0
@@ -80,7 +80,7 @@ _start:
shi r6, r0, 0xe
#endif
-#ifdef CFG_INTC_0
+#ifdef CONFIG_SYS_INTC_0
/* interrupt_handler */
addik r6, r0, _interrupt_handler
sw r6, r1, r0
diff --git a/cpu/microblaze/timer.c b/cpu/microblaze/timer.c
index b350453..a91eabc 100644
--- a/cpu/microblaze/timer.c
+++ b/cpu/microblaze/timer.c
@@ -33,7 +33,7 @@ void reset_timer (void)
timestamp = 0;
}
-#ifdef CFG_TIMER_0
+#ifdef CONFIG_SYS_TIMER_0
ulong get_timer (ulong base)
{
return (timestamp - base);
@@ -50,9 +50,9 @@ void set_timer (ulong t)
timestamp = t;
}
-#ifdef CFG_INTC_0
-#ifdef CFG_TIMER_0
-microblaze_timer_t *tmr = (microblaze_timer_t *) (CFG_TIMER_0_ADDR);
+#ifdef CONFIG_SYS_INTC_0
+#ifdef CONFIG_SYS_TIMER_0
+microblaze_timer_t *tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
void timer_isr (void *arg)
{
@@ -62,12 +62,12 @@ void timer_isr (void *arg)
void timer_init (void)
{
- tmr->loadreg = CFG_TIMER_0_PRELOAD;
+ tmr->loadreg = CONFIG_SYS_TIMER_0_PRELOAD;
tmr->control = TIMER_INTERRUPT | TIMER_RESET;
tmr->control =
TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT;
reset_timer ();
- install_interrupt_handler (CFG_TIMER_0_IRQ, timer_isr, (void *)tmr);
+ install_interrupt_handler (CONFIG_SYS_TIMER_0_IRQ, timer_isr, (void *)tmr);
}
#endif
#endif
diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c
index d0cf8e0..6272a3a 100644
--- a/cpu/mips/au1x00_eth.c
+++ b/cpu/mips/au1x00_eth.c
@@ -23,7 +23,7 @@
*/
#include <config.h>
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
#error "PHY not supported yet"
/* We just assume that we are running 100FD for now */
/* We all use switches, right? ;-) */
@@ -283,7 +283,7 @@ int au1x00_enet_initialize(bd_t *bis){
if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
puts ("malloc failed\n");
- return 0;
+ return -1;
}
memset(dev, 0, sizeof *dev);
diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c
index e8baab5..c25ba5a 100644
--- a/cpu/mips/au1x00_serial.c
+++ b/cpu/mips/au1x00_serial.c
@@ -76,7 +76,7 @@ void serial_setbrg (void)
sd = (*sys_powerctrl & 0x03) + 2;
/* calulate 2x baudrate and round */
- divisorx2 = ((CFG_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
+ divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
if (divisorx2 & 0x01)
divisorx2 = divisorx2 + 1;
diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c
index 1ca8aaf..17489da 100644
--- a/cpu/mips/au1x00_usb_ohci.c
+++ b/cpu/mips/au1x00_usb_ohci.c
@@ -654,7 +654,8 @@ static void td_fill (ohci_t *ohci, unsigned int info,
td->index = index;
td->data = (__u32)data;
#ifdef OHCI_FILL_TRACE
- if (1 || ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe))) {
+ if (1 || (usb_pipebulk(urb_priv->pipe) &&
+ usb_pipeout(urb_priv->pipe))) {
for (i = 0; i < len; i++)
printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
}
@@ -758,7 +759,7 @@ static void dl_transfer_length(td_t * td)
tdCBP = m32_swap (td->hwCBP);
- if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
+ if (!(usb_pipecontrol(lurb_priv->pipe) &&
((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
if (tdBE != 0) {
if (td->hwCBP == 0)
@@ -1015,7 +1016,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
#else
wait_ms(1);
#endif
- if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+ if (usb_pipeint(pipe)) {
info("Root-Hub submit IRQ: NOT implemented");
return 0;
}
@@ -1249,7 +1250,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
/* allow more time for a BULK device to react - some are slow */
#define BULK_TO 5000 /* timeout in milliseconds */
- if (usb_pipetype (pipe) == PIPE_BULK)
+ if (usb_pipebulk(pipe))
timeout = BULK_TO;
else
timeout = 100;
diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index ee5d411..ff4f11c 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -208,9 +208,9 @@ LEAF(mips_init_dcache)
*/
NESTED(mips_cache_reset, 0, ra)
move RA, ra
- li t2, CFG_ICACHE_SIZE
- li t3, CFG_DCACHE_SIZE
- li t4, CFG_CACHELINE_SIZE
+ li t2, CONFIG_SYS_ICACHE_SIZE
+ li t3, CONFIG_SYS_DCACHE_SIZE
+ li t4, CONFIG_SYS_CACHELINE_SIZE
move t5, t4
li v0, MIPS_MAX_CACHE_SIZE
@@ -302,7 +302,7 @@ LEAF(dcache_enable)
jr ra
END(dcache_enable)
-#ifdef CFG_INIT_RAM_LOCK_MIPS
+#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
/*******************************************************************************
*
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
@@ -311,9 +311,9 @@ LEAF(dcache_enable)
*
*/
#if defined(CONFIG_PURPLE)
-# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
+# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2)
#else
-# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
+# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
#endif
.globl mips_cache_lock
.ent mips_cache_lock
@@ -321,11 +321,11 @@ mips_cache_lock:
li a1, CKSEG0 - CACHE_LOCK_SIZE
addu a0, a1
li a2, CACHE_LOCK_SIZE
- li a3, CFG_CACHELINE_SIZE
+ li a3, CONFIG_SYS_CACHELINE_SIZE
move a1, a2
icacheop(a0,a1,a2,a3,0x1d)
jr ra
.end mips_cache_lock
-#endif /* CFG_INIT_RAM_LOCK_MIPS */
+#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index 0f58d25..b7180b0 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -23,6 +23,7 @@
#include <common.h>
#include <command.h>
+#include <netdev.h>
#include <asm/mipsregs.h>
#include <asm/cacheops.h>
#include <asm/reboot.h>
@@ -51,7 +52,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
void flush_cache(ulong start_addr, ulong size)
{
- unsigned long lsize = CFG_CACHELINE_SIZE;
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
@@ -73,3 +74,11 @@ void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
write_c0_index(index);
tlb_write_indexed();
}
+
+int cpu_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SOC_AU1X00
+ au1x00_enet_initialize(bis);
+#endif
+ return 0;
+}
diff --git a/cpu/mips/incaip_clock.c b/cpu/mips/incaip_clock.c
index d0515ca..fc2c621 100644
--- a/cpu/mips/incaip_clock.c
+++ b/cpu/mips/incaip_clock.c
@@ -33,8 +33,8 @@
*
* RETURNS:
* 150.000.000 for 150 MHz
-* 133.333.333 for 133 Mhz (= 400MHz/3)
-* 100.000.000 for 100 Mhz (= 400MHz/4)
+* 133.333.333 for 133 MHz (= 400MHz/3)
+* 100.000.000 for 100 MHz (= 400MHz/4)
* NOTE:
* This functions should be used by the hardware driver to get the correct
* frequency of the CPU. Don't use the macros, which are set to init the CPU
diff --git a/cpu/mips/start.S b/cpu/mips/start.S
index 09e4aab..57db589 100644
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -243,9 +243,11 @@ reset:
mtc0 zero, CP0_COUNT
mtc0 zero, CP0_COMPARE
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
/* CONFIG0 register */
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
/* Initialize $gp.
*/
@@ -255,6 +257,7 @@ reset:
1:
lw gp, 0(ra)
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
/* Initialize any external memory.
*/
la t9, lowlevel_init
@@ -271,17 +274,18 @@ reset:
*/
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
/* Set up temporary stack.
*/
-#ifdef CFG_INIT_RAM_LOCK_MIPS
- li a0, CFG_INIT_SP_OFFSET
+#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
+ li a0, CONFIG_SYS_INIT_SP_OFFSET
la t9, mips_cache_lock
jalr t9
nop
#endif
- li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
+ li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
la sp, 0(t0)
la t9, board_init_f
@@ -303,26 +307,35 @@ reset:
relocate_code:
move sp, a0 /* Set new stack pointer */
- li t0, CFG_MONITOR_BASE
+ li t0, CONFIG_SYS_MONITOR_BASE
la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */
move t1, a2
+ move s2, a2 /* s2 <-- destination address */
/*
* Fix $gp:
*
- * New $gp = (Old $gp - CFG_MONITOR_BASE) + Destination Address
+ * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
*/
move t6, gp
- sub gp, CFG_MONITOR_BASE
+ sub gp, CONFIG_SYS_MONITOR_BASE
add gp, a2 /* gp now adjusted */
- sub t6, gp, t6 /* t6 <-- relocation offset */
+ sub s1, gp, t6 /* s1 <-- relocation offset */
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
+
+ /*
+ * Save destination address and size for later usage in flush_cache()
+ */
+ move s0, a1 /* save gd in s0 */
+ move a0, t1 /* a0 <-- destination addr */
+ sub a1, t2, t0 /* a1 <-- size */
+
/* On the purple board we copy the code earlier in a special way
* in order to solve flash problems
*/
@@ -338,9 +351,14 @@ relocate_code:
/* If caches were enabled, we would have to flush them here.
*/
+ /* a0 & a1 are already set up for flush_cache(start, size) */
+ la t9, flush_cache
+ jalr t9
+ nop
+
/* Jump to where we've relocated ourselves.
*/
- addi t0, a2, in_ram - _start
+ addi t0, s2, in_ram - _start
jr t0
nop
@@ -367,7 +385,7 @@ in_ram:
1:
lw t1, 0(t4)
beqz t1, 2f
- add t1, t6
+ add t1, s1
sw t1, 0(t4)
2:
addi t2, 1
@@ -378,8 +396,8 @@ in_ram:
*/
lw t1, -12(t0) /* t1 <-- uboot_end_data */
lw t2, -8(t0) /* t2 <-- uboot_end */
- add t1, t6 /* adjust pointers */
- add t2, t6
+ add t1, s1 /* adjust pointers */
+ add t2, s1
sub t1, 4
1:
@@ -387,10 +405,10 @@ in_ram:
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
- move a0, a1
+ move a0, s0 /* a0 <-- gd */
la t9, board_init_r
jr t9
- move a1, a2 /* delay slot */
+ move a1, s2 /* delay slot */
.end relocate_code
diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c
index 1f39ac4..b9069b0 100644
--- a/cpu/mpc512x/cpu.c
+++ b/cpu/mpc512x/cpu.c
@@ -30,6 +30,7 @@
#include <common.h>
#include <command.h>
#include <mpc512x.h>
+#include <netdev.h>
#include <asm/processor.h>
#if defined(CONFIG_OF_LIBFDT)
@@ -40,11 +41,11 @@ DECLARE_GLOBAL_DATA_PTR;
int checkcpu (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
ulong clock = gd->cpu_clk;
u32 pvr = get_pvr ();
u32 spridr = immr->sysconf.spridr;
- char buf[32];
+ char buf1[32], buf2[32];
puts ("CPU: ");
@@ -64,8 +65,9 @@ int checkcpu (void)
default:
puts ("unknown ");
}
- printf ("at %s MHz, CSB at %3d MHz\n", strmhz(buf, clock),
- gd->csb_clk / 1000000);
+ printf ("at %s MHz, CSB at %s MHz\n",
+ strmhz(buf1, clock),
+ strmhz(buf2, gd->csb_clk) );
return 0;
}
@@ -74,7 +76,7 @@ int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong msr;
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
/* Interrupts and MMU off */
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
@@ -121,7 +123,7 @@ void watchdog_reset (void)
int re_enable = disable_interrupts ();
/* Reset watchdog */
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
immr->wdt.swsrr = 0x556c;
immr->wdt.swsrr = 0xaa39;
@@ -195,3 +197,15 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#endif
}
#endif
+
+#ifdef CONFIG_MPC512x_FEC
+/* Default initializations for FEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+int cpu_eth_init(bd_t *bis)
+{
+ return mpc512x_fec_initialize(bis);
+}
+#endif
diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c
index d6949f6..fa753c8 100644
--- a/cpu/mpc512x/cpu_init.c
+++ b/cpu/mpc512x/cpu_init.c
@@ -37,23 +37,23 @@ void cpu_init_f (volatile immap_t * im)
u32 ips_div;
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
/* system performance tweaking */
-#ifdef CFG_ACR_PIPE_DEP
+#ifdef CONFIG_SYS_ACR_PIPE_DEP
/* Arbiter pipeline depth */
im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
- (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+ (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
#endif
-#ifdef CFG_ACR_RPTCNT
+#ifdef CONFIG_SYS_ACR_RPTCNT
/* Arbiter repeat count */
im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) |
- (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
+ (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
#endif
/* RSR - Reset Status Register - clear all status */
diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c
index 56ba443..4f6bc86 100644
--- a/cpu/mpc512x/i2c.c
+++ b/cpu/mpc512x/i2c.c
@@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
#include <mpc512x.h>
#include <i2c.h>
-#define immr ((immap_t *)CFG_IMMR)
+#define immr ((immap_t *)CONFIG_SYS_IMMR)
/* by default set I2C bus 0 active */
static unsigned int bus_num = 0;
@@ -382,23 +382,6 @@ Done:
return ret;
}
-uchar i2c_reg_read (uchar chip, uchar reg)
-{
- uchar buf;
-
- i2c_read (chip, reg, 1, &buf, 1);
-
- return buf;
-}
-
-void i2c_reg_write (uchar chip, uchar reg, uchar val)
-{
- i2c_write (chip, reg, 1, &val, 1);
-
- return;
-}
-
-
int i2c_set_bus_num (unsigned int bus)
{
if (bus >= I2C_BUS_CNT) {
@@ -422,7 +405,7 @@ unsigned int i2c_get_bus_speed (void)
int i2c_set_bus_speed (unsigned int speed)
{
- if (speed != CFG_I2C_SPEED)
+ if (speed != CONFIG_SYS_I2C_SPEED)
return -1;
return 0;
diff --git a/cpu/mpc512x/interrupts.c b/cpu/mpc512x/interrupts.c
index 8cc241c..ef7c773 100644
--- a/cpu/mpc512x/interrupts.c
+++ b/cpu/mpc512x/interrupts.c
@@ -37,7 +37,7 @@ struct irq_action {
int interrupt_init_cpu (unsigned *decrementer_count)
{
- *decrementer_count = get_tbclk () / CFG_HZ;
+ *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
return 0;
}
diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c
index 3d7042d..78f4fa1e 100644
--- a/cpu/mpc512x/iopin.c
+++ b/cpu/mpc512x/iopin.c
@@ -29,7 +29,7 @@ void iopin_initialize(iopin_t *ioregs_init, int len)
{
short i, j, p;
u_long *reg;
- immap_t *im = (immap_t *)CFG_IMMR;
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
reg = (u_long *)&(im->io_ctrl.regs[0]);
diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c
index 8a21404..7db87a8 100644
--- a/cpu/mpc512x/serial.c
+++ b/cpu/mpc512x/serial.c
@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
static void fifo_init (volatile psc512x_t *psc)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
/* reset Rx & Tx fifo slice */
psc->rfcmd = PSC_FIFO_RESET_SLICE;
@@ -60,7 +60,7 @@ static void fifo_init (volatile psc512x_t *psc)
int serial_init(void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
unsigned long baseclk;
int div;
@@ -106,7 +106,7 @@ int serial_init(void)
void serial_putc (const char c)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
if (c == '\n')
@@ -121,7 +121,7 @@ void serial_putc (const char c)
void serial_putc_raw (const char c)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
/* Wait for last character to go. */
@@ -141,7 +141,7 @@ void serial_puts (const char *s)
int serial_getc (void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
/* Wait for a character to arrive. */
@@ -153,7 +153,7 @@ int serial_getc (void)
int serial_tstc (void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
return !(psc->rfstat & PSC_FIFO_EMPTY);
@@ -161,7 +161,7 @@ int serial_tstc (void)
void serial_setbrg (void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
unsigned long baseclk, div;
@@ -174,7 +174,7 @@ void serial_setbrg (void)
void serial_setrts(int s)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
if (s) {
@@ -189,7 +189,7 @@ void serial_setrts(int s)
int serial_getcts(void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
return (psc->ip & 0x1) ? 0 : 1;
diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c
index e62477b..542bf21 100644
--- a/cpu/mpc512x/speed.c
+++ b/cpu/mpc512x/speed.c
@@ -62,13 +62,13 @@ static int sys_dividors[][2] = {
int get_clocks (void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u8 spmf;
u8 cpmf;
u8 sys_div;
u8 ips_div;
u8 pci_div;
- u32 ref_clk = CFG_MPC512X_CLKIN;
+ u32 ref_clk = CONFIG_SYS_MPC512X_CLKIN;
u32 spll;
u32 sys_clk;
u32 core_clk;
@@ -125,12 +125,14 @@ ulong get_bus_freq (ulong dummy)
int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
+ char buf[32];
+
printf("Clock configuration:\n");
- printf(" CPU: %4ld MHz\n", gd->cpu_clk / 1000000);
- printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
- printf(" IPS Bus: %4d MHz\n", gd->ips_clk / 1000000);
- printf(" PCI: %4d MHz\n", gd->pci_clk / 1000000);
- printf(" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000);
+ printf(" CPU: %-4s MHz\n", strmhz(buf, gd->cpu_clk));
+ printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
+ printf(" IPS Bus: %-4s MHz\n", strmhz(buf, gd->ips_clk));
+ printf(" PCI: %-4s MHz\n", strmhz(buf, gd->pci_clk));
+ printf(" DDR: %-4s MHz\n", strmhz(buf, 2*gd->csb_clk));
return 0;
}
diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S
index fb8acb5..360682d 100644
--- a/cpu/mpc512x/start.S
+++ b/cpu/mpc512x/start.S
@@ -31,6 +31,7 @@
#include <config.h>
#include <mpc512x.h>
+#include <timestamp.h>
#include <version.h>
#define CONFIG_521X 1 /* needed for Linux kernel header files*/
@@ -85,7 +86,7 @@
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii " ", CONFIG_IDENT_STRING, "\0"
/*
@@ -192,8 +193,8 @@ boot_cold:
/* Set IMMR area to our preferred location */
lis r4, CONFIG_DEFAULT_IMMR@h
- lis r3, CFG_IMMR@h
- ori r3, r3, CFG_IMMR@l
+ lis r3, CONFIG_SYS_IMMR@h
+ ori r3, r3, CONFIG_SYS_IMMR@l
stw r3, IMMRBAR(r4)
mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
@@ -208,18 +209,18 @@ boot_cold:
*/
/* Boot CS/CS0 window range */
- lis r3, CFG_IMMR@h
- ori r3, r3, CFG_IMMR@l
+ lis r3, CONFIG_SYS_IMMR@h
+ ori r3, r3, CONFIG_SYS_IMMR@l
- lis r4, START_REG(CFG_FLASH_BASE)
- ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE)
+ lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
+ ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
stw r4, LPCS0AW(r3)
/*
* The SRAM window has a fixed size (256K), so only the start address
* is necessary
*/
- lis r4, START_REG(CFG_SRAM_BASE) & 0xff00
+ lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
stw r4, SRAMBAR(r3)
/*
@@ -234,11 +235,11 @@ boot_cold:
* Set configuration of the Boot/CS0, the SRAM window does not have a
* config register so no params can be set for it
*/
- lis r3, (CFG_IMMR + LPC_OFFSET)@h
- ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l
+ lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
+ ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
- lis r4, CFG_CS0_CFG@h
- ori r4, r4, CFG_CS0_CFG@l
+ lis r4, CONFIG_SYS_CS0_CFG@h
+ ori r4, r4, CONFIG_SYS_CS0_CFG@l
stw r4, CS0_CONFIG(r3)
/* Master enable all CS's */
@@ -246,15 +247,15 @@ boot_cold:
ori r4, r4, CS_CTRL_ME@l
stw r4, CS_CTRL(r3)
- lis r4, (CFG_MONITOR_BASE)@h
- ori r4, r4, (CFG_MONITOR_BASE)@l
+ lis r4, (CONFIG_SYS_MONITOR_BASE)@h
+ ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r5
blr
in_flash:
- lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
- ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+ lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
+ ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
@@ -268,7 +269,7 @@ in_flash:
GET_GOT /* initialize GOT access */
/* r3: IMMR */
- lis r3, CFG_IMMR@h
+ lis r3, CONFIG_SYS_IMMR@h
/* run low-level CPU init code (in Flash) */
bl cpu_init_f
@@ -353,12 +354,12 @@ cpu_early_init:
SYNC
mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
- lis r3, CFG_IMMR@h
+ lis r3, CONFIG_SYS_IMMR@h
#if defined(CONFIG_WATCHDOG)
/* Initialise the watchdog and reset it */
/*--------------------------------------*/
- lis r4, CFG_WATCHDOG_VALUE
+ lis r4, CONFIG_SYS_WATCHDOG_VALUE
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
stw r4, SWCRR(r3)
@@ -386,18 +387,18 @@ cpu_early_init:
/* Initialize the Hardware Implementation-dependent Registers */
/* HID0 also contains cache control */
/*------------------------------------------------------*/
- lis r3, CFG_HID0_INIT@h
- ori r3, r3, CFG_HID0_INIT@l
+ lis r3, CONFIG_SYS_HID0_INIT@h
+ ori r3, r3, CONFIG_SYS_HID0_INIT@l
SYNC
mtspr HID0, r3
- lis r3, CFG_HID0_FINAL@h
- ori r3, r3, CFG_HID0_FINAL@l
+ lis r3, CONFIG_SYS_HID0_FINAL@h
+ ori r3, r3, CONFIG_SYS_HID0_FINAL@l
SYNC
mtspr HID0, r3
- lis r3, CFG_HID2@h
- ori r3, r3, CFG_HID2@l
+ lis r3, CONFIG_SYS_HID2@h
+ ori r3, r3, CONFIG_SYS_HID2@l
SYNC
mtspr HID2, r3
sync
@@ -499,16 +500,16 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE)
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
* + Destination Address
*
* Offset:
diff --git a/cpu/mpc5xx/cpu.c b/cpu/mpc5xx/cpu.c
index 4bef90c..7fffebc 100644
--- a/cpu/mpc5xx/cpu.c
+++ b/cpu/mpc5xx/cpu.c
@@ -80,7 +80,7 @@ void watchdog_reset (void)
{
int re_enable = disable_interrupts ();
- reset_5xx_watchdog ((immap_t *) CFG_IMMR);
+ reset_5xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
if (re_enable)
enable_interrupts ();
}
@@ -103,14 +103,14 @@ void reset_5xx_watchdog (volatile immap_t * immr)
*/
unsigned long get_tbclk (void)
{
- volatile immap_t *immr = (volatile immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *) CONFIG_SYS_IMMR;
ulong oscclk, factor;
if (immr->im_clkrst.car_sccr & SCCR_TBS) {
return (gd->cpu_clk / 16);
}
- factor = (((CFG_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1;
+ factor = (((CONFIG_SYS_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1;
oscclk = gd->cpu_clk / factor;
@@ -141,7 +141,7 @@ int dcache_status (void)
int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_PATI)
- volatile ulong *addr = (ulong *) CFG_RESET_ADDRESS;
+ volatile ulong *addr = (ulong *) CONFIG_SYS_RESET_ADDRESS;
*addr = 1;
#else
ulong addr;
@@ -155,15 +155,15 @@ int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
-#ifdef CFG_RESET_ADDRESS
- addr = CFG_RESET_ADDRESS;
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
- * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address
- * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
+ * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address
+ * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
* "(ulong)-1" used to be a good choice for many systems...
*/
- addr = CFG_MONITOR_BASE - sizeof (ulong);
+ addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
((void (*) (void)) addr) ();
#endif /* #if defined(CONFIG_PATI) */
diff --git a/cpu/mpc5xx/cpu_init.c b/cpu/mpc5xx/cpu_init.c
index 5bbb798..cb4bf84 100644
--- a/cpu/mpc5xx/cpu_init.c
+++ b/cpu/mpc5xx/cpu_init.c
@@ -41,74 +41,74 @@ void cpu_init_f (volatile immap_t * immr)
/* SYPCR - contains watchdog control. This will enable watchdog */
/* if CONFIG_WATCHDOG is set */
- immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
+ immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
#if defined(CONFIG_WATCHDOG)
reset_5xx_watchdog (immr);
#endif
/* SIUMCR - contains debug pin configuration */
- immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
+ immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
/* Initialize timebase. Unlock TBSCRK */
immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
- immr->im_sit.sit_tbscr = CFG_TBSCR;
+ immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
/* Full IMB bus speed */
- immr->im_uimb.uimb_umcr = CFG_UMCR;
+ immr->im_uimb.uimb_umcr = CONFIG_SYS_UMCR;
/* Time base and decrementer will be enables (TBE) */
/* in init_timebase() in time.c called from board_init_f(). */
/* Initialize the PIT. Unlock PISCRK */
immr->im_sitk.sitk_piscrk = KAPWR_KEY;
- immr->im_sit.sit_piscr = CFG_PISCR;
+ immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
#if !defined(CONFIG_PATI)
/* PATI sest PLL in start.S */
/* PLL (CPU clock) settings */
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
- /* If CFG_PLPRCR (set in the various *_config.h files) tries to
- * set the MF field, then just copy CFG_PLPRCR over car_plprcr,
- * otherwise OR in CFG_PLPRCR so we do not change the currentMF
+ /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
+ * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
+ * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the currentMF
* field value.
*/
-#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0)
- reg = CFG_PLPRCR; /* reset control bits */
+#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0)
+ reg = CONFIG_SYS_PLPRCR; /* reset control bits */
#else
reg = immr->im_clkrst.car_plprcr;
reg &= PLPRCR_MF_MSK; /* isolate MF field */
- reg |= CFG_PLPRCR; /* reset control bits */
+ reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
#endif
immr->im_clkrst.car_plprcr = reg;
#endif /* !defined(CONFIG_PATI) */
- /* System integration timers. CFG_MASK has EBDF configuration */
+ /* System integration timers. CONFIG_SYS_MASK has EBDF configuration */
immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
reg = immr->im_clkrst.car_sccr;
reg &= SCCR_MASK;
- reg |= CFG_SCCR;
+ reg |= CONFIG_SYS_SCCR;
immr->im_clkrst.car_sccr = reg;
/* Memory Controller */
- memctl->memc_br0 = CFG_BR0_PRELIM;
- memctl->memc_or0 = CFG_OR0_PRELIM;
+ memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
+ memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
-#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
- memctl->memc_or1 = CFG_OR1_PRELIM;
- memctl->memc_br1 = CFG_BR1_PRELIM;
+#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
+ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+ memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
#endif
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
- memctl->memc_or2 = CFG_OR2_PRELIM;
- memctl->memc_br2 = CFG_BR2_PRELIM;
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+ memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+ memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
#endif
-#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
- memctl->memc_or3 = CFG_OR3_PRELIM;
- memctl->memc_br3 = CFG_BR3_PRELIM;
+#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+ memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
#endif
}
diff --git a/cpu/mpc5xx/interrupts.c b/cpu/mpc5xx/interrupts.c
index a4f47c7..167543f 100644
--- a/cpu/mpc5xx/interrupts.c
+++ b/cpu/mpc5xx/interrupts.c
@@ -52,11 +52,11 @@ static struct interrupt_action irq_vecs[NR_IRQS];
int interrupt_init_cpu (ulong *decrementer_count)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int vec;
/* Decrementer used here for status led */
- *decrementer_count = get_tbclk () / CFG_HZ;
+ *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
/* Disable all interrupts */
immr->im_siu_conf.sc_simask = 0;
@@ -74,7 +74,7 @@ int interrupt_init_cpu (ulong *decrementer_count)
*/
void external_interrupt (struct pt_regs *regs)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int irq;
ulong simask, newmask;
ulong vec, v_bit;
@@ -130,7 +130,7 @@ void external_interrupt (struct pt_regs *regs)
void irq_install_handler (int vec, interrupt_handler_t * handler,
void *arg)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
/* SIU interrupt */
if (irq_vecs[vec].handler != NULL) {
printf ("SIU interrupt %d 0x%x\n",
@@ -148,7 +148,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler,
void irq_free_handler (int vec)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
/* SIU interrupt */
#if 0
printf ("Free CPM interrupt for vector %d\n",
@@ -165,7 +165,7 @@ void irq_free_handler (int vec)
*/
void timer_interrupt_cpu (struct pt_regs *regs)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
#if 0
printf ("*** Timer Interrupt *** ");
diff --git a/cpu/mpc5xx/serial.c b/cpu/mpc5xx/serial.c
index 39f57a1..88c6db8 100644
--- a/cpu/mpc5xx/serial.c
+++ b/cpu/mpc5xx/serial.c
@@ -48,7 +48,7 @@ static int ready_to_send(void);
int serial_init (void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
serial_setbrg();
@@ -65,7 +65,7 @@ int serial_init (void)
void serial_putc(const char c)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
/* Test for completition */
if(ready_to_send()) {
@@ -87,7 +87,7 @@ void serial_putc(const char c)
int serial_getc(void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile short status;
unsigned char tmp;
@@ -115,7 +115,7 @@ int serial_getc(void)
int serial_tstc()
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
short status;
/* New data character ? */
@@ -129,7 +129,7 @@ int serial_tstc()
void serial_setbrg (void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
short scxbr;
/* Set baudrate */
@@ -151,7 +151,7 @@ void serial_puts (const char *s)
int ready_to_send(void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile short status;
do {
diff --git a/cpu/mpc5xx/speed.c b/cpu/mpc5xx/speed.c
index 7b7c5b9..ea5c1de 100644
--- a/cpu/mpc5xx/speed.c
+++ b/cpu/mpc5xx/speed.c
@@ -38,14 +38,14 @@ DECLARE_GLOBAL_DATA_PTR;
*/
int get_clocks (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
#ifndef CONFIG_5xx_GCLK_FREQ
uint divf = (immr->im_clkrst.car_plprcr & PLPRCR_DIVF_MSK);
uint mf = ((immr->im_clkrst.car_plprcr & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT);
ulong vcoout;
- vcoout = (CFG_OSC_CLK / (divf + 1)) * (mf + 1) * 2;
+ vcoout = (CONFIG_SYS_OSC_CLK / (divf + 1)) * (mf + 1) * 2;
if(immr->im_clkrst.car_plprcr & PLPRCR_CSRC_MSK) {
gd->cpu_clk = vcoout / (2^(((immr->im_clkrst.car_sccr & SCCR_DFNL_MSK) >> SCCR_DFNL_SHIFT) + 1));
} else {
diff --git a/cpu/mpc5xx/spi.c b/cpu/mpc5xx/spi.c
index 3c187be..3ca15ea 100644
--- a/cpu/mpc5xx/spi.c
+++ b/cpu/mpc5xx/spi.c
@@ -111,7 +111,7 @@ void spi_init_f (void)
volatile immap_t *immr;
volatile qsmcm5xx_t *qsmcm;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
qsmcm->qsmcm_qsmcr = 0; /* all accesses enabled */
@@ -128,7 +128,7 @@ void spi_init_f (void)
* PQSPAR[06] = 1 [0x0200] -> PERI: (SPIMOSI)
* PQSPAR[07] = 1 [0x0100] -> PERI: (SPIMISO)
* -------------------------------------------- */
- qsmcm->qsmcm_pqspar = 0x3 | (CFG_SPI_CS_USED << 3);
+ qsmcm->qsmcm_pqspar = 0x3 | (CONFIG_SYS_SPI_CS_USED << 3);
/* --------------------------------------------
* DDRQS[00] = 0 reserved
@@ -160,7 +160,7 @@ void spi_init_f (void)
* PORTQS[14] = 0 [0x0002] -> SPIMOSI Output
* PORTQS[15] = 0 [0x0001] -> SPIMISO Input
* -------------------------------------------- */
- qsmcm->qsmcm_portqs |= (CFG_SPI_CS_BASE << 3);
+ qsmcm->qsmcm_portqs |= (CONFIG_SYS_SPI_CS_BASE << 3);
/* --------------------------------------------
* Controll Register 0
* SPCR0[00] = 1 (0x8000) Master
@@ -235,7 +235,7 @@ ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len)
volatile immap_t *immr;
volatile qsmcm5xx_t *qsmcm;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
for(i=0;i<32;i++) {
qsmcm->qsmcm_recram[i]=0x0000;
@@ -308,7 +308,7 @@ ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len)
volatile immap_t *immr;
volatile qsmcm5xx_t *qsmcm;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
for(i=0;i<32;i++) {
@@ -364,15 +364,15 @@ ssize_t spi_xfer (size_t count)
int i;
int tm;
ushort status;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
DPRINT (("*** spi_xfer entered count %d***\n",count));
/* Set CS for device */
for(i=0;i<(count-1);i++)
- qsmcm->qsmcm_comdram[i] = 0x80 | CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */
+ qsmcm->qsmcm_comdram[i] = 0x80 | CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */
- qsmcm->qsmcm_comdram[i] = CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */
+ qsmcm->qsmcm_comdram[i] = CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */
qsmcm->qsmcm_spcr2=((count-1)&0x1F)<<8;
DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", count));
diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S
index 0637003..106935c 100644
--- a/cpu/mpc5xx/start.S
+++ b/cpu/mpc5xx/start.S
@@ -32,6 +32,7 @@
#include <config.h>
#include <mpc5xx.h>
+#include <timestamp.h>
#include <version.h>
#define CONFIG_5xx 1 /* needed for Linux kernel header files */
@@ -80,14 +81,14 @@
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
_start:
mfspr r3, 638
- li r4, CFG_ISB /* Set ISB bit */
+ li r4, CONFIG_SYS_ISB /* Set ISB bit */
or r3, r3, r4
mtspr 638, r3
li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
@@ -121,12 +122,12 @@ boot_warm:
/* the external flash access on PATI fails if programming the PLL to 40MHz.
* Copy the PLL programming code to the internal RAM and execute it
*----------------------------------------------------------------------*/
- lis r3, CFG_MONITOR_BASE@h
- ori r3, r3, CFG_MONITOR_BASE@l
+ lis r3, CONFIG_SYS_MONITOR_BASE@h
+ ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET
- lis r4, CFG_INIT_RAM_ADDR@h
- ori r4, r4, CFG_INIT_RAM_ADDR@l
+ lis r4, CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
mtlr r4
addis r5,0,0x0
ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2)
@@ -144,8 +145,8 @@ boot_warm:
* Calculate absolute address in FLASH and jump there
*----------------------------------------------------------------------*/
- lis r3, CFG_MONITOR_BASE@h
- ori r3, r3, CFG_MONITOR_BASE@l
+ lis r3, CONFIG_SYS_MONITOR_BASE@h
+ ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
@@ -155,9 +156,9 @@ in_flash:
/* Initialize some SPRs that are hard to access from C */
/*----------------------------------------------------------------------*/
- lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
- lis r2, CFG_INIT_SP_ADDR@h
- ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
+ lis r3, CONFIG_SYS_IMMR@h /* Pass IMMR as arg1 to C routine */
+ lis r2, CONFIG_SYS_INIT_SP_ADDR@h
+ ori r1, r2, CONFIG_SYS_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
/* Note: R0 is still 0 here */
stwu r0, -4(r1) /* Clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
@@ -173,8 +174,8 @@ in_flash:
/* Set up debug mode entry */
- lis r2, CFG_DER@h
- ori r2, r2, CFG_DER@l
+ lis r2, CONFIG_SYS_DER@h
+ ori r2, r2, CONFIG_SYS_DER@l
mtspr DER, r2
/* Let the C-code set up the rest */
@@ -385,15 +386,15 @@ relocate_code:
mr r10, r5 /* Save copy of monitor destination Address in SRAM */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
@@ -581,15 +582,15 @@ trap_reloc:
#if defined(CONFIG_PATI)
/* Program the PLL */
pll_prog_code_start:
- lis r4, (CFG_IMMR + 0x002fc384)@h
- ori r4, r4, (CFG_IMMR + 0x002fc384)@l
+ lis r4, (CONFIG_SYS_IMMR + 0x002fc384)@h
+ ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l
lis r3, (0x55ccaa33)@h
ori r3, r3, (0x55ccaa33)@l
stw r3, 0(r4)
- lis r4, (CFG_IMMR + 0x002fc284)@h
- ori r4, r4, (CFG_IMMR + 0x002fc284)@l
- lis r3, CFG_PLPRCR@h
- ori r3, r3, CFG_PLPRCR@l
+ lis r4, (CONFIG_SYS_IMMR + 0x002fc284)@h
+ ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l
+ lis r3, CONFIG_SYS_PLPRCR@h
+ ori r3, r3, CONFIG_SYS_PLPRCR@l
stw r3, 0(r4)
addis r3,0,0x0
ori r3,r3,0xA000
diff --git a/cpu/mpc5xx/u-boot.lds b/cpu/mpc5xx/u-boot.lds
index 7434e3f..bf52179 100644
--- a/cpu/mpc5xx/u-boot.lds
+++ b/cpu/mpc5xx/u-boot.lds
@@ -126,6 +126,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
@@ -133,7 +134,7 @@ SECTIONS
/* . = env_start;
.ppcenv :
{
- common/environment.o (.ppcenv)
+ common/env_embedded.o (.ppcenv)
}
*/
}
diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index 0ed2899..9c6ab76 100644
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -29,6 +29,7 @@
#include <watchdog.h>
#include <command.h>
#include <mpc5xxx.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
@@ -117,7 +118,7 @@ unsigned long get_tbclk (void)
#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
void ft_cpu_setup(void *blob, bd_t *bd)
{
- int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4;
+ int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4;
char * cpu_path = "/cpus/" OF_CPU;
#ifdef CONFIG_MPC5xxx_FEC
char * eth_path = "/" OF_SOC "/ethernet@3000";
@@ -155,3 +156,15 @@ ulong bootcount_load (void)
return (*save_addr & 0x0000ffff);
}
#endif /* CONFIG_BOOTCOUNT_LIMIT */
+
+#ifdef CONFIG_MPC5xxx_FEC
+/* Default initializations for FEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+int cpu_eth_init(bd_t *bis)
+{
+ return mpc5xxx_fec_initialize(bis);
+}
+#endif
diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index bc6201e..14bd417 100644
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -35,11 +35,11 @@ DECLARE_GLOBAL_DATA_PTR;
void cpu_init_f (void)
{
unsigned long addecr = (1 << 25); /* Boot_CS */
-#if defined(CFG_RAMBOOT) && defined(CONFIG_MGT5100)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100)
addecr |= (1 << 22); /* SDRAM enable */
#endif
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
@@ -47,95 +47,95 @@ void cpu_init_f (void)
/*
* Memory Controller: configure chip selects and enable them
*/
-#if defined(CFG_BOOTCS_START) && defined(CFG_BOOTCS_SIZE)
- *(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CFG_BOOTCS_START);
- *(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CFG_BOOTCS_START,
- CFG_BOOTCS_SIZE);
+#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
+ *(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CONFIG_SYS_BOOTCS_START);
+ *(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CONFIG_SYS_BOOTCS_START,
+ CONFIG_SYS_BOOTCS_SIZE);
#endif
-#if defined(CFG_BOOTCS_CFG)
- *(vu_long *)MPC5XXX_BOOTCS_CFG = CFG_BOOTCS_CFG;
+#if defined(CONFIG_SYS_BOOTCS_CFG)
+ *(vu_long *)MPC5XXX_BOOTCS_CFG = CONFIG_SYS_BOOTCS_CFG;
#endif
-#if defined(CFG_CS0_START) && defined(CFG_CS0_SIZE)
- *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_CS0_START);
- *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_CS0_START, CFG_CS0_SIZE);
+#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
+ *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_CS0_START);
+ *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE);
/* CS0 and BOOT_CS cannot be enabled at once. */
/* addecr |= (1 << 16); */
#endif
-#if defined(CFG_CS0_CFG)
- *(vu_long *)MPC5XXX_CS0_CFG = CFG_CS0_CFG;
+#if defined(CONFIG_SYS_CS0_CFG)
+ *(vu_long *)MPC5XXX_CS0_CFG = CONFIG_SYS_CS0_CFG;
#endif
-#if defined(CFG_CS1_START) && defined(CFG_CS1_SIZE)
- *(vu_long *)MPC5XXX_CS1_START = START_REG(CFG_CS1_START);
- *(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CFG_CS1_START, CFG_CS1_SIZE);
+#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
+ *(vu_long *)MPC5XXX_CS1_START = START_REG(CONFIG_SYS_CS1_START);
+ *(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE);
addecr |= (1 << 17);
#endif
-#if defined(CFG_CS1_CFG)
- *(vu_long *)MPC5XXX_CS1_CFG = CFG_CS1_CFG;
+#if defined(CONFIG_SYS_CS1_CFG)
+ *(vu_long *)MPC5XXX_CS1_CFG = CONFIG_SYS_CS1_CFG;
#endif
-#if defined(CFG_CS2_START) && defined(CFG_CS2_SIZE)
- *(vu_long *)MPC5XXX_CS2_START = START_REG(CFG_CS2_START);
- *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, CFG_CS2_SIZE);
+#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
+ *(vu_long *)MPC5XXX_CS2_START = START_REG(CONFIG_SYS_CS2_START);
+ *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE);
addecr |= (1 << 18);
#endif
-#if defined(CFG_CS2_CFG)
- *(vu_long *)MPC5XXX_CS2_CFG = CFG_CS2_CFG;
+#if defined(CONFIG_SYS_CS2_CFG)
+ *(vu_long *)MPC5XXX_CS2_CFG = CONFIG_SYS_CS2_CFG;
#endif
-#if defined(CFG_CS3_START) && defined(CFG_CS3_SIZE)
- *(vu_long *)MPC5XXX_CS3_START = START_REG(CFG_CS3_START);
- *(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CFG_CS3_START, CFG_CS3_SIZE);
+#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
+ *(vu_long *)MPC5XXX_CS3_START = START_REG(CONFIG_SYS_CS3_START);
+ *(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE);
addecr |= (1 << 19);
#endif
-#if defined(CFG_CS3_CFG)
- *(vu_long *)MPC5XXX_CS3_CFG = CFG_CS3_CFG;
+#if defined(CONFIG_SYS_CS3_CFG)
+ *(vu_long *)MPC5XXX_CS3_CFG = CONFIG_SYS_CS3_CFG;
#endif
-#if defined(CFG_CS4_START) && defined(CFG_CS4_SIZE)
- *(vu_long *)MPC5XXX_CS4_START = START_REG(CFG_CS4_START);
- *(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CFG_CS4_START, CFG_CS4_SIZE);
+#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
+ *(vu_long *)MPC5XXX_CS4_START = START_REG(CONFIG_SYS_CS4_START);
+ *(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE);
addecr |= (1 << 20);
#endif
-#if defined(CFG_CS4_CFG)
- *(vu_long *)MPC5XXX_CS4_CFG = CFG_CS4_CFG;
+#if defined(CONFIG_SYS_CS4_CFG)
+ *(vu_long *)MPC5XXX_CS4_CFG = CONFIG_SYS_CS4_CFG;
#endif
-#if defined(CFG_CS5_START) && defined(CFG_CS5_SIZE)
- *(vu_long *)MPC5XXX_CS5_START = START_REG(CFG_CS5_START);
- *(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CFG_CS5_START, CFG_CS5_SIZE);
+#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
+ *(vu_long *)MPC5XXX_CS5_START = START_REG(CONFIG_SYS_CS5_START);
+ *(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE);
addecr |= (1 << 21);
#endif
-#if defined(CFG_CS5_CFG)
- *(vu_long *)MPC5XXX_CS5_CFG = CFG_CS5_CFG;
+#if defined(CONFIG_SYS_CS5_CFG)
+ *(vu_long *)MPC5XXX_CS5_CFG = CONFIG_SYS_CS5_CFG;
#endif
#if defined(CONFIG_MPC5200)
addecr |= 1;
-#if defined(CFG_CS6_START) && defined(CFG_CS6_SIZE)
- *(vu_long *)MPC5XXX_CS6_START = START_REG(CFG_CS6_START);
- *(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CFG_CS6_START, CFG_CS6_SIZE);
+#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
+ *(vu_long *)MPC5XXX_CS6_START = START_REG(CONFIG_SYS_CS6_START);
+ *(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE);
addecr |= (1 << 26);
#endif
-#if defined(CFG_CS6_CFG)
- *(vu_long *)MPC5XXX_CS6_CFG = CFG_CS6_CFG;
+#if defined(CONFIG_SYS_CS6_CFG)
+ *(vu_long *)MPC5XXX_CS6_CFG = CONFIG_SYS_CS6_CFG;
#endif
-#if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
- *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START);
- *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
+#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
+ *(vu_long *)MPC5XXX_CS7_START = START_REG(CONFIG_SYS_CS7_START);
+ *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE);
addecr |= (1 << 27);
#endif
-#if defined(CFG_CS7_CFG)
- *(vu_long *)MPC5XXX_CS7_CFG = CFG_CS7_CFG;
+#if defined(CONFIG_SYS_CS7_CFG)
+ *(vu_long *)MPC5XXX_CS7_CFG = CONFIG_SYS_CS7_CFG;
#endif
-#if defined(CFG_CS_BURST)
- *(vu_long *)MPC5XXX_CS_BURST = CFG_CS_BURST;
+#if defined(CONFIG_SYS_CS_BURST)
+ *(vu_long *)MPC5XXX_CS_BURST = CONFIG_SYS_CS_BURST;
#endif
-#if defined(CFG_CS_DEADCYCLE)
- *(vu_long *)MPC5XXX_CS_DEADCYCLE = CFG_CS_DEADCYCLE;
+#if defined(CONFIG_SYS_CS_DEADCYCLE)
+ *(vu_long *)MPC5XXX_CS_DEADCYCLE = CONFIG_SYS_CS_DEADCYCLE;
#endif
#endif /* CONFIG_MPC5200 */
@@ -144,8 +144,8 @@ void cpu_init_f (void)
*(vu_long *)MPC5XXX_CS_CTRL = (1 << 24);
/* Setup pin multiplexing */
-#if defined(CFG_GPS_PORT_CONFIG)
- *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CFG_GPS_PORT_CONFIG;
+#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
+ *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CONFIG_SYS_GPS_PORT_CONFIG;
#endif
#if defined(CONFIG_MPC5200)
@@ -154,28 +154,28 @@ void cpu_init_f (void)
/* Enable snooping for RAM */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
- *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
+ *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_SYS_SDRAM_BASE | 0x1d;
-# if defined(CFG_IPBCLK_EQUALS_XLBCLK)
+# if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
/* Motorola reports IPB should better run at 133 MHz. */
*(vu_long *)MPC5XXX_ADDECR |= 1;
/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
addecr = *(vu_long *)MPC5XXX_CDM_CFG;
addecr &= ~0x103;
-# if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2)
+# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
addecr |= 0x01;
# else
/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
addecr |= 0x02;
-# endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */
+# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
*(vu_long *)MPC5XXX_CDM_CFG = addecr;
-# endif /* CFG_IPBCLK_EQUALS_XLBCLK */
+# endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
/* Configure the XLB Arbiter */
*(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
*(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;
-# if defined(CFG_XLB_PIPELINING)
+# if defined(CONFIG_SYS_XLB_PIPELINING)
/* Enable piplining */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
# endif
diff --git a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
index a07c776..d140c7e 100644
--- a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
+++ b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
@@ -23,7 +23,7 @@ scEthernetRecv_Entry: /* Task 0 */
.long 0x00000000
.long 0x00000000
.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */
-.long CFG_MBAR
+.long CONFIG_SYS_MBAR
.globl scEthernetXmit_Entry
scEthernetXmit_Entry: /* Task 1 */
.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */
@@ -33,7 +33,7 @@ scEthernetXmit_Entry: /* Task 1 */
.long 0x00000000
.long 0x00000000
.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */
-.long CFG_MBAR
+.long CONFIG_SYS_MBAR
.globl scEthernetRecv_TDT
@@ -151,7 +151,7 @@ scEthernetRecv_VarTab: /* Task 0 Variable Table */
.long 0x00000000 /* var[6] */
.long 0x00000000 /* var[7] */
.long 0x00000000 /* var[8] */
-.long (CFG_MBAR + 0x8800) /* var[9] */
+.long (CONFIG_SYS_MBAR + 0x8800) /* var[9] */
.long 0x00000008 /* var[10] */
.long 0x0000000c /* var[11] */
.long 0x80000000 /* var[12] */
@@ -190,7 +190,7 @@ scEthernetXmit_VarTab: /* Task 1 Variable Table */
.long 0x00000000 /* var[8] */
.long 0x00000000 /* var[9] */
.long 0x00000000 /* var[10] */
-.long (CFG_MBAR + 0x8800) /* var[11] */
+.long (CONFIG_SYS_MBAR + 0x8800) /* var[11] */
.long 0x00000000 /* var[12] */
.long 0x80000000 /* var[13] */
.long 0x10000000 /* var[14] */
diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c
index 0f02e78..7d76274 100644
--- a/cpu/mpc5xxx/i2c.c
+++ b/cpu/mpc5xxx/i2c.c
@@ -30,12 +30,12 @@ DECLARE_GLOBAL_DATA_PTR;
#include <mpc5xxx.h>
#include <i2c.h>
-#if (CFG_I2C_MODULE == 2)
+#if (CONFIG_SYS_I2C_MODULE == 2)
#define I2C_BASE MPC5XXX_I2C2
-#elif (CFG_I2C_MODULE == 1)
+#elif (CONFIG_SYS_I2C_MODULE == 1)
#define I2C_BASE MPC5XXX_I2C1
#else
-#error CFG_I2C_MODULE is not properly configured
+#error CONFIG_SYS_I2C_MODULE is not properly configured
#endif
#define I2C_TIMEOUT 100
@@ -380,20 +380,4 @@ Done:
return ret;
}
-uchar i2c_reg_read(uchar chip, uchar reg)
-{
- uchar buf;
-
- i2c_read(chip, reg, 1, &buf, 1);
-
- return buf;
-}
-
-void i2c_reg_write(uchar chip, uchar reg, uchar val)
-{
- i2c_write(chip, reg, 1, &val, 1);
-
- return;
-}
-
#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c
index 8816dd1..6035771 100644
--- a/cpu/mpc5xxx/interrupts.c
+++ b/cpu/mpc5xxx/interrupts.c
@@ -229,7 +229,7 @@ int mpc5xxx_get_irq(struct pt_regs *regs)
int interrupt_init_cpu(ulong * decrementer_count)
{
- *decrementer_count = get_tbclk() / CFG_HZ;
+ *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
mpc5xxx_init_irq();
diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index 2f01d5c..a3251ab 100644
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -31,8 +31,8 @@
#include <mpc5xxx.h>
/* System RAM mapped over PCI */
-#define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE
-#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE
+#define CONFIG_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
/* PCIIWCR bit fields */
@@ -125,11 +125,11 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
/* Set cache line size */
*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
- (CFG_CACHELINE_SIZE / 4);
+ (CONFIG_SYS_CACHELINE_SIZE / 4);
/* Map MBAR to PCI space */
- *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
- *(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1;
+ *(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR;
+ *(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1;
/* Map RAM to PCI space */
*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c
index 430d63f..a8a384a 100644
--- a/cpu/mpc5xxx/serial.c
+++ b/cpu/mpc5xxx/serial.c
@@ -106,7 +106,7 @@ int serial_init (void)
/* select clock sources */
#if defined(CONFIG_MGT5100)
psc->psc_clock_select = 0xdd00;
- baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
+ baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
#elif defined(CONFIG_MPC5200)
psc->psc_clock_select = 0;
baseclk = (gd->ipb_clk + 16) / 32;
@@ -247,7 +247,7 @@ void serial_setbrg(void)
unsigned long baseclk, div;
#if defined(CONFIG_MGT5100)
- baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
+ baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
#elif defined(CONFIG_MPC5200)
baseclk = (gd->ipb_clk + 16) / 32;
#endif
diff --git a/cpu/mpc5xxx/speed.c b/cpu/mpc5xxx/speed.c
index 7847adc..8027d3e 100644
--- a/cpu/mpc5xxx/speed.c
+++ b/cpu/mpc5xxx/speed.c
@@ -47,15 +47,15 @@ int get_clocks (void)
{
ulong val, vco;
-#if !defined(CFG_MPC5XXX_CLKIN)
-#error clock measuring not implemented yet - define CFG_MPC5XXX_CLKIN
+#if !defined(CONFIG_SYS_MPC5XXX_CLKIN)
+#error clock measuring not implemented yet - define CONFIG_SYS_MPC5XXX_CLKIN
#endif
val = *(vu_long *)MPC5XXX_CDM_PORCFG;
if (val & (1 << 6)) {
- vco = CFG_MPC5XXX_CLKIN * 12;
+ vco = CONFIG_SYS_MPC5XXX_CLKIN * 12;
} else {
- vco = CFG_MPC5XXX_CLKIN * 16;
+ vco = CONFIG_SYS_MPC5XXX_CLKIN * 16;
}
if (val & (1 << 5)) {
gd->bus_clk = vco / 8;
@@ -81,10 +81,13 @@ int get_clocks (void)
int prt_mpc5xxx_clks (void)
{
- printf(" Bus %ld MHz, IPB %ld MHz, PCI %ld MHz\n",
- gd->bus_clk / 1000000, gd->ipb_clk / 1000000,
- gd->pci_clk / 1000000);
+ char buf1[32], buf2[32], buf3[32];
+ printf (" Bus %s MHz, IPB %s MHz, PCI %s MHz\n",
+ strmhz(buf1, gd->bus_clk),
+ strmhz(buf2, gd->ipb_clk),
+ strmhz(buf3, gd->pci_clk)
+ );
return (0);
}
diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index 9b1bd48..6b1162a 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -27,6 +27,7 @@
*/
#include <config.h>
#include <mpc5xxx.h>
+#include <timestamp.h>
#include <version.h>
#define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */
@@ -78,7 +79,7 @@
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
/*
@@ -106,19 +107,19 @@ boot_warm:
/* Move CSBoot and adjust instruction pointer */
/*--------------------------------------------------------------*/
-#if defined(CFG_LOWBOOT)
-# if defined(CFG_RAMBOOT)
-# error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
-# endif /* CFG_RAMBOOT */
+#if defined(CONFIG_SYS_LOWBOOT)
+# if defined(CONFIG_SYS_RAMBOOT)
+# error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
+# endif /* CONFIG_SYS_RAMBOOT */
# if defined(CONFIG_MGT5100)
-# error CFG_LOWBOOT is incompatible with MGT5100
+# error CONFIG_SYS_LOWBOOT is incompatible with MGT5100
# endif /* CONFIG_MGT5100 */
- lis r4, CFG_DEFAULT_MBAR@h
- lis r3, START_REG(CFG_BOOTCS_START)@h
- ori r3, r3, START_REG(CFG_BOOTCS_START)@l
+ lis r4, CONFIG_SYS_DEFAULT_MBAR@h
+ lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
+ ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
stw r3, 0x4(r4) /* CS0 start */
- lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
- ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
+ lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
+ ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
stw r3, 0x8(r4) /* CS0 stop */
lis r3, 0x02010000@h
ori r3, r3, 0x02010000@l
@@ -130,20 +131,20 @@ boot_warm:
blr
lowboot_reentry:
- lis r3, START_REG(CFG_BOOTCS_START)@h
- ori r3, r3, START_REG(CFG_BOOTCS_START)@l
+ lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
+ ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
stw r3, 0x4c(r4) /* Boot start */
- lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
- ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
+ lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
+ ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
stw r3, 0x50(r4) /* Boot stop */
lis r3, 0x02000001@h
ori r3, r3, 0x02000001@l
stw r3, 0x54(r4) /* Boot enable, CS0 disable */
-#endif /* CFG_LOWBOOT */
+#endif /* CONFIG_SYS_LOWBOOT */
-#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
- lis r3, CFG_MBAR@h
- ori r3, r3, CFG_MBAR@l
+#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
+ lis r3, CONFIG_SYS_MBAR@h
+ ori r3, r3, CONFIG_SYS_MBAR@l
#if defined(CONFIG_MPC5200)
/* MBAR is mirrored into the MBAR SPR */
mtspr MBAR,r3
@@ -152,9 +153,9 @@ lowboot_reentry:
#if defined(CONFIG_MGT5100)
rlwinm r3, r3, 17, 15, 31
#endif
- lis r4, CFG_DEFAULT_MBAR@h
+ lis r4, CONFIG_SYS_DEFAULT_MBAR@h
stw r3, 0(r4)
-#endif /* CFG_DEFAULT_MBAR */
+#endif /* CONFIG_SYS_DEFAULT_MBAR */
/* Initialise the MPC5xxx processor core */
/*--------------------------------------------------------------*/
@@ -165,9 +166,9 @@ lowboot_reentry:
/*--------------------------------------------------------------*/
/* set up stack in on-chip SRAM */
- lis r3, CFG_INIT_RAM_ADDR@h
- ori r3, r3, CFG_INIT_RAM_ADDR@l
- ori r1, r3, CFG_INIT_SP_OFFSET
+ lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
+ ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
@@ -400,13 +401,13 @@ init_5xxx_core:
/* HID0 also contains cache control */
/*--------------------------------------------------------------*/
- lis r3, CFG_HID0_INIT@h
- ori r3, r3, CFG_HID0_INIT@l
+ lis r3, CONFIG_SYS_HID0_INIT@h
+ ori r3, r3, CONFIG_SYS_HID0_INIT@l
SYNC
mtspr HID0, r3
- lis r3, CFG_HID0_FINAL@h
- ori r3, r3, CFG_HID0_FINAL@l
+ lis r3, CONFIG_SYS_HID0_FINAL@h
+ ori r3, r3, CONFIG_SYS_HID0_FINAL@l
SYNC
mtspr HID0, r3
@@ -582,16 +583,16 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
diff --git a/cpu/mpc5xxx/u-boot-customlayout.lds b/cpu/mpc5xxx/u-boot-customlayout.lds
index 3847860..f6bb858 100644
--- a/cpu/mpc5xxx/u-boot-customlayout.lds
+++ b/cpu/mpc5xxx/u-boot-customlayout.lds
@@ -62,7 +62,7 @@ SECTIONS
lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.ppcenv)
+ common/env_embedded.o (.ppcenv)
*(.text)
*(.fixup)
@@ -129,6 +129,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/cpu/mpc5xxx/u-boot.lds b/cpu/mpc5xxx/u-boot.lds
index 13fffb8..8d1fa60 100644
--- a/cpu/mpc5xxx/u-boot.lds
+++ b/cpu/mpc5xxx/u-boot.lds
@@ -118,6 +118,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/cpu/mpc5xxx/usb.c b/cpu/mpc5xxx/usb.c
index ed467ab..8f2b66a 100644
--- a/cpu/mpc5xxx/usb.c
+++ b/cpu/mpc5xxx/usb.c
@@ -23,7 +23,7 @@
#include <common.h>
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
#include <mpc5xxx.h>
@@ -51,4 +51,4 @@ int usb_cpu_init_fail(void)
return 0;
}
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/cpu/mpc5xxx/usb_ohci.c b/cpu/mpc5xxx/usb_ohci.c
index 2ad12b2..4bf659d 100644
--- a/cpu/mpc5xxx/usb_ohci.c
+++ b/cpu/mpc5xxx/usb_ohci.c
@@ -660,7 +660,7 @@ static void td_fill (ohci_t *ohci, unsigned int info,
td->index = index;
td->data = (__u32)data;
#ifdef OHCI_FILL_TRACE
- if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
+ if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
for (i = 0; i < len; i++)
printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
printf("\n");
@@ -761,7 +761,7 @@ static void dl_transfer_length(td_t * td)
tdCBP = ohci_cpu_to_le32 (td->hwCBP);
- if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
+ if (!(usb_pipecontrol(lurb_priv->pipe) &&
((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
if (tdBE != 0) {
if (td->hwCBP == 0)
@@ -1023,7 +1023,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
urb_priv.actual_length = 0;
pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
#endif
- if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+ if (usb_pipeint(pipe)) {
info("Root-Hub submit IRQ: NOT implemented");
return 0;
}
@@ -1248,7 +1248,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
/* allow more time for a BULK device to react - some are slow */
#define BULK_TO 5000 /* timeout in milliseconds */
- if (usb_pipetype (pipe) == PIPE_BULK)
+ if (usb_pipebulk(pipe))
timeout = BULK_TO;
else
timeout = 100;
diff --git a/cpu/mpc8220/cpu.c b/cpu/mpc8220/cpu.c
index be274cd..563cfe0 100644
--- a/cpu/mpc8220/cpu.c
+++ b/cpu/mpc8220/cpu.c
@@ -29,6 +29,7 @@
#include <watchdog.h>
#include <command.h>
#include <mpc8220.h>
+#include <netdev.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -42,7 +43,7 @@ int checkcpu (void)
printf (CPU_ID_STR);
- printf (" (JTAG ID %08lx)", *(vu_long *) (CFG_MBAR + 0x50));
+ printf (" (JTAG ID %08lx)", *(vu_long *) (CONFIG_SYS_MBAR + 0x50));
printf (" at %s MHz\n", strmhz (buf, clock));
@@ -89,3 +90,15 @@ unsigned long get_tbclk (void)
}
/* ------------------------------------------------------------------------- */
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_MPC8220_FEC)
+ mpc8220_fec_initialize(bis);
+#endif
+ return 0;
+}
diff --git a/cpu/mpc8220/cpu_init.c b/cpu/mpc8220/cpu_init.c
index 0daac5b..8f52c7d 100644
--- a/cpu/mpc8220/cpu_init.c
+++ b/cpu/mpc8220/cpu_init.c
@@ -39,7 +39,7 @@ void cpu_init_f (void)
volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB;
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
@@ -49,54 +49,54 @@ void cpu_init_f (void)
portcfg->pcfg1 = 0;
portcfg->pcfg2 = 0;
portcfg->pcfg3 = 0;
- portcfg->pcfg2 = CFG_GP1_PORT2_CONFIG;
- portcfg->pcfg3 = CFG_PCI_PORT3_CONFIG | CFG_GP2_PORT3_CONFIG;
+ portcfg->pcfg2 = CONFIG_SYS_GP1_PORT2_CONFIG;
+ portcfg->pcfg3 = CONFIG_SYS_PCI_PORT3_CONFIG | CONFIG_SYS_GP2_PORT3_CONFIG;
/*
* Flexbus Controller: configure chip selects and enable them
*/
-#if defined (CFG_CS0_BASE)
- flexbus->csar0 = CFG_CS0_BASE;
+#if defined (CONFIG_SYS_CS0_BASE)
+ flexbus->csar0 = CONFIG_SYS_CS0_BASE;
/* Sorcery-C can hang-up after CTRL reg initialization */
-#if defined (CFG_CS0_CTRL)
- flexbus->cscr0 = CFG_CS0_CTRL;
+#if defined (CONFIG_SYS_CS0_CTRL)
+ flexbus->cscr0 = CONFIG_SYS_CS0_CTRL;
#endif
- flexbus->csmr0 = ((CFG_CS0_MASK - 1) & 0xffff0000) | 1;
+ flexbus->csmr0 = ((CONFIG_SYS_CS0_MASK - 1) & 0xffff0000) | 1;
__asm__ volatile ("sync");
#endif
-#if defined (CFG_CS1_BASE)
- flexbus->csar1 = CFG_CS1_BASE;
- flexbus->cscr1 = CFG_CS1_CTRL;
- flexbus->csmr1 = ((CFG_CS1_MASK - 1) & 0xffff0000) | 1;
+#if defined (CONFIG_SYS_CS1_BASE)
+ flexbus->csar1 = CONFIG_SYS_CS1_BASE;
+ flexbus->cscr1 = CONFIG_SYS_CS1_CTRL;
+ flexbus->csmr1 = ((CONFIG_SYS_CS1_MASK - 1) & 0xffff0000) | 1;
__asm__ volatile ("sync");
#endif
-#if defined (CFG_CS2_BASE)
- flexbus->csar2 = CFG_CS2_BASE;
- flexbus->cscr2 = CFG_CS2_CTRL;
- flexbus->csmr2 = ((CFG_CS2_MASK - 1) & 0xffff0000) | 1;
- portcfg->pcfg3 |= CFG_CS2_PORT3_CONFIG;
+#if defined (CONFIG_SYS_CS2_BASE)
+ flexbus->csar2 = CONFIG_SYS_CS2_BASE;
+ flexbus->cscr2 = CONFIG_SYS_CS2_CTRL;
+ flexbus->csmr2 = ((CONFIG_SYS_CS2_MASK - 1) & 0xffff0000) | 1;
+ portcfg->pcfg3 |= CONFIG_SYS_CS2_PORT3_CONFIG;
__asm__ volatile ("sync");
#endif
-#if defined (CFG_CS3_BASE)
- flexbus->csar3 = CFG_CS3_BASE;
- flexbus->cscr3 = CFG_CS3_CTRL;
- flexbus->csmr3 = ((CFG_CS3_MASK - 1) & 0xffff0000) | 1;
- portcfg->pcfg3 |= CFG_CS3_PORT3_CONFIG;
+#if defined (CONFIG_SYS_CS3_BASE)
+ flexbus->csar3 = CONFIG_SYS_CS3_BASE;
+ flexbus->cscr3 = CONFIG_SYS_CS3_CTRL;
+ flexbus->csmr3 = ((CONFIG_SYS_CS3_MASK - 1) & 0xffff0000) | 1;
+ portcfg->pcfg3 |= CONFIG_SYS_CS3_PORT3_CONFIG;
__asm__ volatile ("sync");
#endif
-#if defined (CFG_CS4_BASE)
- flexbus->csar4 = CFG_CS4_BASE;
- flexbus->cscr4 = CFG_CS4_CTRL;
- flexbus->csmr4 = ((CFG_CS4_MASK - 1) & 0xffff0000) | 1;
- portcfg->pcfg3 |= CFG_CS4_PORT3_CONFIG;
+#if defined (CONFIG_SYS_CS4_BASE)
+ flexbus->csar4 = CONFIG_SYS_CS4_BASE;
+ flexbus->cscr4 = CONFIG_SYS_CS4_CTRL;
+ flexbus->csmr4 = ((CONFIG_SYS_CS4_MASK - 1) & 0xffff0000) | 1;
+ portcfg->pcfg3 |= CONFIG_SYS_CS4_PORT3_CONFIG;
__asm__ volatile ("sync");
#endif
-#if defined (CFG_CS5_BASE)
- flexbus->csar5 = CFG_CS5_BASE;
- flexbus->cscr5 = CFG_CS5_CTRL;
- flexbus->csmr5 = ((CFG_CS5_MASK - 1) & 0xffff0000) | 1;
- portcfg->pcfg3 |= CFG_CS5_PORT3_CONFIG;
+#if defined (CONFIG_SYS_CS5_BASE)
+ flexbus->csar5 = CONFIG_SYS_CS5_BASE;
+ flexbus->cscr5 = CONFIG_SYS_CS5_CTRL;
+ flexbus->csmr5 = ((CONFIG_SYS_CS5_MASK - 1) & 0xffff0000) | 1;
+ portcfg->pcfg3 |= CONFIG_SYS_CS5_PORT3_CONFIG;
__asm__ volatile ("sync");
#endif
diff --git a/cpu/mpc8220/dramSetup.c b/cpu/mpc8220/dramSetup.c
index 08e3172..52cf133 100644
--- a/cpu/mpc8220/dramSetup.c
+++ b/cpu/mpc8220/dramSetup.c
@@ -34,9 +34,9 @@ characteristics to initialize the dram on MPC8220
DECLARE_GLOBAL_DATA_PTR;
-#define SPD_SIZE CFG_SDRAM_SPD_SIZE
-#define DRAM_SPD (CFG_SDRAM_SPD_I2C_ADDR)<<1 /* on Board SPD eeprom */
-#define TOTAL_BANK CFG_SDRAM_TOTAL_BANKS
+#define SPD_SIZE CONFIG_SYS_SDRAM_SPD_SIZE
+#define DRAM_SPD (CONFIG_SYS_SDRAM_SPD_I2C_ADDR)<<1 /* on Board SPD eeprom */
+#define TOTAL_BANK CONFIG_SYS_SDRAM_TOTAL_BANKS
int spd_status (volatile i2c8220_t * pi2c, u8 sta_bit, u8 truefalse)
{
@@ -103,7 +103,7 @@ int readSpdData (u8 * spdData)
/* Enable Port Configuration for SDA and SDL signals */
pcfg = (volatile pcfg8220_t *) (MMAP_PCFG);
__asm__ ("sync");
- pcfg->pcfg3 &= ~CFG_I2C_PORT3_CONFIG;
+ pcfg->pcfg3 &= ~CONFIG_SYS_I2C_PORT3_CONFIG;
__asm__ ("sync");
/* Points the structure to I2c mbar memory offset */
@@ -144,7 +144,7 @@ int readSpdData (u8 * spdData)
break;
}
- pi2cReg->adr = CFG_I2C_SLAVE<<1;
+ pi2cReg->adr = CONFIG_SYS_I2C_SLAVE<<1;
pi2cReg->cr = I2C_CTL_EN; /* Set Enable */
@@ -541,7 +541,7 @@ u32 dramSetup (void)
}
/* Set up the Drive Strength register */
- sysconf->sdramds = CFG_SDRAM_DRIVE_STRENGTH;
+ sysconf->sdramds = CONFIG_SYS_SDRAM_DRIVE_STRENGTH;
/* ********************** Cfg 1 ************************* */
@@ -679,7 +679,7 @@ u32 dramSetup (void)
/* Set up mode value for CAS latency */
-#if (CFG_SDRAM_CAS_LATENCY==5) /* CL=2.5 */
+#if (CONFIG_SYS_SDRAM_CAS_LATENCY==5) /* CL=2.5 */
mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) |
MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2p5) | MODE_CMD);
#else
diff --git a/cpu/mpc8220/i2c.c b/cpu/mpc8220/i2c.c
index d67936d..76ecdf1 100644
--- a/cpu/mpc8220/i2c.c
+++ b/cpu/mpc8220/i2c.c
@@ -387,20 +387,4 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buf, int len)
return ret;
}
-uchar i2c_reg_read (uchar chip, uchar reg)
-{
- uchar buf;
-
- i2c_read (chip, reg, 1, &buf, 1);
-
- return buf;
-}
-
-void i2c_reg_write (uchar chip, uchar reg, uchar val)
-{
- i2c_write (chip, reg, 1, &val, 1);
-
- return;
-}
-
#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/mpc8220/i2cCore.c b/cpu/mpc8220/i2cCore.c
index accf43c..b89ad03 100644
--- a/cpu/mpc8220/i2cCore.c
+++ b/cpu/mpc8220/i2cCore.c
@@ -440,7 +440,7 @@ STATUS i2c_write2byte (SI2C * pi2c, UINT16 * writeb)
return OK;
}
-/* FDR table base on 33Mhz - more detail please refer to Odini2c_dividers.xls
+/* FDR table base on 33MHz - more detail please refer to Odini2c_dividers.xls
FDR FDR scl sda scl2tap2
510 432 tap tap tap tap scl_per sda_hold I2C Freq 0 1 2 3 4 5
000 000 9 3 4 1 28 Clocks 9 Clocks 1190 KHz 0 0 0 0 0 0
diff --git a/cpu/mpc8220/interrupts.c b/cpu/mpc8220/interrupts.c
index 036378c..78e9917 100644
--- a/cpu/mpc8220/interrupts.c
+++ b/cpu/mpc8220/interrupts.c
@@ -34,7 +34,7 @@
int interrupt_init_cpu (ulong * decrementer_count)
{
- *decrementer_count = get_tbclk () / CFG_HZ;
+ *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
return (0);
}
diff --git a/cpu/mpc8220/pci.c b/cpu/mpc8220/pci.c
index 4ef214e..a78a828 100644
--- a/cpu/mpc8220/pci.c
+++ b/cpu/mpc8220/pci.c
@@ -33,8 +33,8 @@
#if defined(CONFIG_PCI)
/* System RAM mapped over PCI */
-#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
#define cfg_read(val, addr, type, op) *val = op((type)(addr));
diff --git a/cpu/mpc8220/speed.c b/cpu/mpc8220/speed.c
index 200a762..62ac845 100644
--- a/cpu/mpc8220/speed.c
+++ b/cpu/mpc8220/speed.c
@@ -67,25 +67,25 @@ int get_clocks (void)
u32 hid1;
int i, size, pci2bus;
-#if !defined(CFG_MPC8220_CLKIN)
-#error clock measuring not implemented yet - define CFG_MPC8220_CLKIN
+#if !defined(CONFIG_SYS_MPC8220_CLKIN)
+#error clock measuring not implemented yet - define CONFIG_SYS_MPC8220_CLKIN
#endif
- gd->inp_clk = CFG_MPC8220_CLKIN;
+ gd->inp_clk = CONFIG_SYS_MPC8220_CLKIN;
/* Read XLB to PCI(INP) clock multiplier */
pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) &
PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK)>>PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT;
/* XLB bus clock */
- gd->bus_clk = CFG_MPC8220_CLKIN * pci2bus;
+ gd->bus_clk = CONFIG_SYS_MPC8220_CLKIN * pci2bus;
/* PCI clock is same as input clock */
- gd->pci_clk = CFG_MPC8220_CLKIN;
+ gd->pci_clk = CONFIG_SYS_MPC8220_CLKIN;
/* FlexBus is temporary set as the same as input clock */
/* will do dynamic in the future */
- gd->flb_clk = CFG_MPC8220_CLKIN;
+ gd->flb_clk = CONFIG_SYS_MPC8220_CLKIN;
/* CPU Clock - Read HID1 */
asm volatile ("mfspr %0, 1009":"=r" (hid1):);
@@ -97,7 +97,7 @@ int get_clocks (void)
for (i = 0; i < size; i++)
if (hid1 == bus2core[i].hid1) {
gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1;
- gd->vco_clk = CFG_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2;
+ gd->vco_clk = CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2;
break;
}
@@ -109,10 +109,14 @@ int get_clocks (void)
int prt_mpc8220_clks (void)
{
- printf (" Bus %ld MHz, CPU %ld MHz, PCI %ld MHz, VCO %ld MHz\n",
- gd->bus_clk / 1000000, gd->cpu_clk / 1000000,
- gd->pci_clk / 1000000, gd->vco_clk / 1000000);
-
+ char buf1[32], buf2[32], buf3[32], buf4[32];
+
+ printf (" Bus %s MHz, CPU %s MHz, PCI %s MHz, VCO %s MHz\n",
+ strmhz(buf1, gd->bus_clk),
+ strmhz(buf2, gd->cpu_clk),
+ strmhz(buf3, gd->pci_clk),
+ strmhz(buf4, gd->vco_clk)
+ );
return (0);
}
diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S
index b5145ca..3abc619 100644
--- a/cpu/mpc8220/start.S
+++ b/cpu/mpc8220/start.S
@@ -27,6 +27,7 @@
*/
#include <config.h>
#include <mpc8220.h>
+#include <timestamp.h>
#include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
@@ -77,7 +78,7 @@
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
/*
@@ -105,16 +106,16 @@ boot_warm:
/* replace default MBAR base address from 0x80000000
to 0xf0000000 */
-#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
- lis r3, CFG_MBAR@h
- ori r3, r3, CFG_MBAR@l
+#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
+ lis r3, CONFIG_SYS_MBAR@h
+ ori r3, r3, CONFIG_SYS_MBAR@l
/* MBAR is mirrored into the MBAR SPR */
mtspr MBAR,r3
mtspr SPRN_SPRG7W,r3
- lis r4, CFG_DEFAULT_MBAR@h
+ lis r4, CONFIG_SYS_DEFAULT_MBAR@h
stw r3, 0(r4)
-#endif /* CFG_DEFAULT_MBAR */
+#endif /* CONFIG_SYS_DEFAULT_MBAR */
/* Initialise the MPC8220 processor core */
/*--------------------------------------------------------------*/
@@ -125,9 +126,9 @@ boot_warm:
/*--------------------------------------------------------------*/
/* set up stack in on-chip SRAM */
- lis r3, CFG_INIT_RAM_ADDR@h
- ori r3, r3, CFG_INIT_RAM_ADDR@l
- ori r1, r3, CFG_INIT_SP_OFFSET
+ lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
+ ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
@@ -361,13 +362,13 @@ init_8220_core:
/* HID0 also contains cache control */
/*--------------------------------------------------------------*/
- lis r3, CFG_HID0_INIT@h
- ori r3, r3, CFG_HID0_INIT@l
+ lis r3, CONFIG_SYS_HID0_INIT@h
+ ori r3, r3, CONFIG_SYS_HID0_INIT@l
SYNC
mtspr HID0, r3
- lis r3, CFG_HID0_FINAL@h
- ori r3, r3, CFG_HID0_FINAL@l
+ lis r3, CONFIG_SYS_HID0_FINAL@h
+ ori r3, r3, CONFIG_SYS_HID0_FINAL@l
SYNC
mtspr HID0, r3
@@ -458,7 +459,7 @@ init_8220_core:
.globl icache_enable
icache_enable:
lis r4, 0
- ori r4, r4, CFG_HID0_INIT /* set ICE & ICFI bit */
+ ori r4, r4, CONFIG_SYS_HID0_INIT /* set ICE & ICFI bit */
rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
/*
@@ -547,16 +548,16 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
diff --git a/cpu/mpc8220/u-boot.lds b/cpu/mpc8220/u-boot.lds
index e34a9d4..2a12a69 100644
--- a/cpu/mpc8220/u-boot.lds
+++ b/cpu/mpc8220/u-boot.lds
@@ -118,6 +118,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/cpu/mpc824x/cpu.c b/cpu/mpc824x/cpu.c
index 0a45cc8..08f6a94 100644
--- a/cpu/mpc824x/cpu.c
+++ b/cpu/mpc824x/cpu.c
@@ -109,17 +109,17 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
-#ifdef CFG_RESET_ADDRESS
- addr = CFG_RESET_ADDRESS;
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
- * note: when CFG_MONITOR_BASE points to a RAM address,
- * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
+ * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
+ * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
* address. Better pick an address known to be invalid on
- * your system and assign it to CFG_RESET_ADDRESS.
+ * your system and assign it to CONFIG_SYS_RESET_ADDRESS.
* "(ulong)-1" used to be a good choice for many systems...
*/
- addr = CFG_MONITOR_BASE - sizeof (ulong);
+ addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
((void (*)(void)) addr) ();
return 1;
diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c
index 7871031..395f776 100644
--- a/cpu/mpc824x/cpu_init.c
+++ b/cpu/mpc824x/cpu_init.c
@@ -25,32 +25,32 @@
#include <asm/processor.h>
#include <mpc824x.h>
-#ifndef CFG_BANK0_ROW
-#define CFG_BANK0_ROW 0
+#ifndef CONFIG_SYS_BANK0_ROW
+#define CONFIG_SYS_BANK0_ROW 0
#endif
-#ifndef CFG_BANK1_ROW
-#define CFG_BANK1_ROW 0
+#ifndef CONFIG_SYS_BANK1_ROW
+#define CONFIG_SYS_BANK1_ROW 0
#endif
-#ifndef CFG_BANK2_ROW
-#define CFG_BANK2_ROW 0
+#ifndef CONFIG_SYS_BANK2_ROW
+#define CONFIG_SYS_BANK2_ROW 0
#endif
-#ifndef CFG_BANK3_ROW
-#define CFG_BANK3_ROW 0
+#ifndef CONFIG_SYS_BANK3_ROW
+#define CONFIG_SYS_BANK3_ROW 0
#endif
-#ifndef CFG_BANK4_ROW
-#define CFG_BANK4_ROW 0
+#ifndef CONFIG_SYS_BANK4_ROW
+#define CONFIG_SYS_BANK4_ROW 0
#endif
-#ifndef CFG_BANK5_ROW
-#define CFG_BANK5_ROW 0
+#ifndef CONFIG_SYS_BANK5_ROW
+#define CONFIG_SYS_BANK5_ROW 0
#endif
-#ifndef CFG_BANK6_ROW
-#define CFG_BANK6_ROW 0
+#ifndef CONFIG_SYS_BANK6_ROW
+#define CONFIG_SYS_BANK6_ROW 0
#endif
-#ifndef CFG_BANK7_ROW
-#define CFG_BANK7_ROW 0
+#ifndef CONFIG_SYS_BANK7_ROW
+#define CONFIG_SYS_BANK7_ROW 0
#endif
-#ifndef CFG_DBUS_SIZE2
-#define CFG_DBUS_SIZE2 0
+#ifndef CONFIG_SYS_DBUS_SIZE2
+#define CONFIG_SYS_DBUS_SIZE2 0
#endif
/*
@@ -163,150 +163,150 @@ cpu_init_f (void)
#endif
CONFIG_WRITE_WORD(PICR2, val);
- CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR);
-#ifndef CFG_RAMBOOT
- CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) |
- (CFG_BANK0_ROW) |
- (CFG_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
- (CFG_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
- (CFG_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
- (CFG_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
- (CFG_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
- (CFG_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
- (CFG_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
- (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT));
+ CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
+#ifndef CONFIG_SYS_RAMBOOT
+ CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) |
+ (CONFIG_SYS_BANK0_ROW) |
+ (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
+ (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
+ (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
+ (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
+ (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
+ (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
+ (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
+ (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
#endif
-#if defined(CFG_ASRISE) && defined(CFG_ASFALL)
- CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT |
- CFG_ASRISE << MCCR2_ASRISE_SHIFT |
- CFG_ASFALL << MCCR2_ASFALL_SHIFT);
+#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
+ CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT |
+ CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT |
+ CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
#else
- CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT);
+ CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
#endif
#if defined(CONFIG_MPC8240)
CONFIG_WRITE_WORD(MCCR3,
- (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
- (CFG_REFREC << MCCR3_REFREC_SHIFT) |
- (CFG_RDLAT << MCCR3_RDLAT_SHIFT));
+ (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
+ (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) |
+ (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT));
#elif defined(CONFIG_MPC8245)
CONFIG_WRITE_WORD(MCCR3,
- (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
- (CFG_REFREC << MCCR3_REFREC_SHIFT));
+ (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
+ (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
/* this is gross. We think these should all be the same, and various boards
- * should define CFG_ACTORW to 0 if they don't want to set it, or even, if
+ * should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
* its not set, we define it to zero in this file
*/
#if defined(CONFIG_CU824) || defined(CONFIG_PN62)
CONFIG_WRITE_WORD(MCCR4,
- (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
- (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
+ (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
+ (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
MCCR4_BIT21 |
- (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
- ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
- (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
- CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
- (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
- (((CFG_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
+ (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
+ ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
+ (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
+ CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
+ (CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
+ (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
#elif defined(CONFIG_MPC8240)
CONFIG_WRITE_WORD(MCCR4,
- (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
- (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
+ (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
+ (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
MCCR4_BIT21 |
- (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
- ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
- (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
- (CFG_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
- (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
+ (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
+ ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
+ (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
+ (CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
+ (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#elif defined(CONFIG_MPC8245)
CONFIG_READ_WORD(MCCR1, val);
val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */
CONFIG_WRITE_WORD(MCCR4,
- (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
- (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
- (CFG_EXTROM ? MCCR4_EXTROM : 0) |
- (CFG_REGDIMM ? MCCR4_REGDIMM : 0) |
- (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
- ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
- (CFG_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
- (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
+ (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
+ (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
+ (CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) |
+ (CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) |
+ (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
+ ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
+ (CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
+ (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
(val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) |
- (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
- (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
+ (CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
+ (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
CONFIG_WRITE_WORD(MSAR1,
- ( (CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
- (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
- (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
+ ( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+ (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
+ (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
+ (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(EMSAR1,
- ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
- (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
- (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
+ ( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+ (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
+ (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
+ (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(MSAR2,
- ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
- (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
- (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
+ ( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+ (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
+ (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
+ (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(EMSAR2,
- ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
- (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
- (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
+ ( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+ (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
+ (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
+ (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(MEAR1,
- ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
- (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
- (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
+ ( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+ (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
+ (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
+ (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(EMEAR1,
- ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
- (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
- (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
+ ( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+ (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
+ (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
+ (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(MEAR2,
- ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
- (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
- (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
+ ( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+ (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
+ (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
+ (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
CONFIG_WRITE_WORD(EMEAR2,
- ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
- (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
- (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
-
- CONFIG_WRITE_BYTE(ODCR, CFG_ODCR);
-#ifdef CFG_DLL_MAX_DELAY
- CONFIG_WRITE_BYTE(MIOCR1, CFG_DLL_MAX_DELAY); /* needed to make DLL lock */
+ ( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+ (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
+ (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
+ (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
+
+ CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
+#ifdef CONFIG_SYS_DLL_MAX_DELAY
+ CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY); /* needed to make DLL lock */
#endif
-#if defined(CFG_DLL_EXTEND) && defined(CFG_PCI_HOLD_DEL)
- CONFIG_WRITE_BYTE(PMCR2, CFG_DLL_EXTEND | CFG_PCI_HOLD_DEL);
+#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
+ CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL);
#endif
-#if defined(MIOCR2) && defined(CFG_SDRAM_DSCD)
- CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD); /* change memory input */
+#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
+ CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD); /* change memory input */
#endif /* setup & hold time */
CONFIG_WRITE_BYTE(MBER,
- CFG_BANK0_ENABLE |
- (CFG_BANK1_ENABLE << 1) |
- (CFG_BANK2_ENABLE << 2) |
- (CFG_BANK3_ENABLE << 3) |
- (CFG_BANK4_ENABLE << 4) |
- (CFG_BANK5_ENABLE << 5) |
- (CFG_BANK6_ENABLE << 6) |
- (CFG_BANK7_ENABLE << 7));
-
-#ifdef CFG_PGMAX
- CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX);
+ CONFIG_SYS_BANK0_ENABLE |
+ (CONFIG_SYS_BANK1_ENABLE << 1) |
+ (CONFIG_SYS_BANK2_ENABLE << 2) |
+ (CONFIG_SYS_BANK3_ENABLE << 3) |
+ (CONFIG_SYS_BANK4_ENABLE << 4) |
+ (CONFIG_SYS_BANK5_ENABLE << 5) |
+ (CONFIG_SYS_BANK6_ENABLE << 6) |
+ (CONFIG_SYS_BANK7_ENABLE << 7));
+
+#ifdef CONFIG_SYS_PGMAX
+ CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
#endif
/* ! Wait 200us before initialize other registers */
diff --git a/cpu/mpc824x/drivers/epic/epic1.c b/cpu/mpc824x/drivers/epic/epic1.c
index f89deed..ecbb42d 100644
--- a/cpu/mpc824x/drivers/epic/epic1.c
+++ b/cpu/mpc824x/drivers/epic/epic1.c
@@ -311,7 +311,7 @@ ULONG sysEUMBBARRead
{
ULONG temp;
- temp = *(ULONG *) (CFG_EUMB_ADDR + regNum);
+ temp = *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum);
return ( LONGSWAP(temp));
}
@@ -331,7 +331,7 @@ void sysEUMBBARWrite
)
{
- *(ULONG *) (CFG_EUMB_ADDR + regNum) = LONGSWAP(regVal);
+ *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum) = LONGSWAP(regVal);
return ;
}
diff --git a/cpu/mpc824x/drivers/i2c/i2c.c b/cpu/mpc824x/drivers/i2c/i2c.c
index 3add687..637ae4c 100644
--- a/cpu/mpc824x/drivers/i2c/i2c.c
+++ b/cpu/mpc824x/drivers/i2c/i2c.c
@@ -31,9 +31,9 @@
#ifdef CONFIG_HARD_I2C
#include <i2c.h>
-#define TIMEOUT (CFG_HZ/4)
+#define TIMEOUT (CONFIG_SYS_HZ/4)
-#define I2C_Addr ((unsigned *)(CFG_EUMB_ADDR + 0x3000))
+#define I2C_Addr ((unsigned *)(CONFIG_SYS_EUMB_ADDR + 0x3000))
#define I2CADR &I2C_Addr[0]
#define I2CFDR &I2C_Addr[1]
@@ -267,18 +267,4 @@ int i2c_probe (uchar chip)
return i2c_read (chip, 0, 1, (uchar *) &tmp, 1);
}
-uchar i2c_reg_read (uchar i2c_addr, uchar reg)
-{
- uchar buf[1];
-
- i2c_read (i2c_addr, reg, 1, buf, 1);
-
- return (buf[0]);
-}
-
-void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
-{
- i2c_write (i2c_addr, reg, 1, &val, 1);
-}
-
#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/mpc824x/interrupts.c b/cpu/mpc824x/interrupts.c
index 4359ecc..139c52c 100644
--- a/cpu/mpc824x/interrupts.c
+++ b/cpu/mpc824x/interrupts.c
@@ -31,7 +31,7 @@
int interrupt_init_cpu (unsigned *decrementer_count)
{
- *decrementer_count = (get_bus_freq (0) / 4) / CFG_HZ;
+ *decrementer_count = (get_bus_freq (0) / 4) / CONFIG_SYS_HZ;
/*
* It's all broken at the moment and I currently don't need
@@ -57,7 +57,7 @@ void external_interrupt (struct pt_regs *regs)
{
register unsigned long temp;
- pci_readl (CFG_EUMB_ADDR + EPIC_PROC_INT_ACK_REG, temp);
+ pci_readl (CONFIG_SYS_EUMB_ADDR + EPIC_PROC_INT_ACK_REG, temp);
sync (); /* i'm not convinced this is needed, but dink source has it */
temp &= 0xff; /*get vector */
diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S
index 784edc3..39325cd 100644
--- a/cpu/mpc824x/start.S
+++ b/cpu/mpc824x/start.S
@@ -39,6 +39,7 @@
*/
#include <config.h>
#include <mpc824x.h>
+#include <timestamp.h>
#include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
@@ -90,7 +91,7 @@
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
. = EXC_OFF_SYS_RESET
@@ -157,8 +158,8 @@ in_flash:
/* Allocate Initial RAM in data cache.
*/
- lis r3, CFG_INIT_RAM_ADDR@h
- ori r3, r3, CFG_INIT_RAM_ADDR@l
+ lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
li r2, 128
mtctr r2
1:
@@ -180,8 +181,8 @@ in_flash:
* Thisk the stack pointer *somewhere* sensible. Doesnt
* matter much where as we'll move it when we relocate
*/
- lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
- ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+ lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
+ ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
@@ -475,21 +476,21 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
-#ifdef CFG_RAMBOOT
- lis r4, CFG_SDRAM_BASE@h /* Source Address */
- ori r4, r4, CFG_SDRAM_BASE@l
+#ifdef CONFIG_SYS_RAMBOOT
+ lis r4, CONFIG_SYS_SDRAM_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_SDRAM_BASE@l
#else
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
#endif
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
@@ -531,8 +532,8 @@ relocate_code:
/* Unlock the data cache and invalidate locked area */
xor r0, r0, r0
mtspr 1011, r0
- lis r4, CFG_INIT_RAM_ADDR@h
- ori r4, r4, CFG_INIT_RAM_ADDR@l
+ lis r4, CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
li r0, 128
mtctr r0
41:
@@ -709,66 +710,66 @@ trap_reloc:
/* Setup the BAT registers.
*/
setup_bats:
- lis r4, CFG_IBAT0L@h
- ori r4, r4, CFG_IBAT0L@l
- lis r3, CFG_IBAT0U@h
- ori r3, r3, CFG_IBAT0U@l
+ lis r4, CONFIG_SYS_IBAT0L@h
+ ori r4, r4, CONFIG_SYS_IBAT0L@l
+ lis r3, CONFIG_SYS_IBAT0U@h
+ ori r3, r3, CONFIG_SYS_IBAT0U@l
mtspr IBAT0L, r4
mtspr IBAT0U, r3
isync
- lis r4, CFG_DBAT0L@h
- ori r4, r4, CFG_DBAT0L@l
- lis r3, CFG_DBAT0U@h
- ori r3, r3, CFG_DBAT0U@l
+ lis r4, CONFIG_SYS_DBAT0L@h
+ ori r4, r4, CONFIG_SYS_DBAT0L@l
+ lis r3, CONFIG_SYS_DBAT0U@h
+ ori r3, r3, CONFIG_SYS_DBAT0U@l
mtspr DBAT0L, r4
mtspr DBAT0U, r3
isync
- lis r4, CFG_IBAT1L@h
- ori r4, r4, CFG_IBAT1L@l
- lis r3, CFG_IBAT1U@h
- ori r3, r3, CFG_IBAT1U@l
+ lis r4, CONFIG_SYS_IBAT1L@h
+ ori r4, r4, CONFIG_SYS_IBAT1L@l
+ lis r3, CONFIG_SYS_IBAT1U@h
+ ori r3, r3, CONFIG_SYS_IBAT1U@l
mtspr IBAT1L, r4
mtspr IBAT1U, r3
isync
- lis r4, CFG_DBAT1L@h
- ori r4, r4, CFG_DBAT1L@l
- lis r3, CFG_DBAT1U@h
- ori r3, r3, CFG_DBAT1U@l
+ lis r4, CONFIG_SYS_DBAT1L@h
+ ori r4, r4, CONFIG_SYS_DBAT1L@l
+ lis r3, CONFIG_SYS_DBAT1U@h
+ ori r3, r3, CONFIG_SYS_DBAT1U@l
mtspr DBAT1L, r4
mtspr DBAT1U, r3
isync
- lis r4, CFG_IBAT2L@h
- ori r4, r4, CFG_IBAT2L@l
- lis r3, CFG_IBAT2U@h
- ori r3, r3, CFG_IBAT2U@l
+ lis r4, CONFIG_SYS_IBAT2L@h
+ ori r4, r4, CONFIG_SYS_IBAT2L@l
+ lis r3, CONFIG_SYS_IBAT2U@h
+ ori r3, r3, CONFIG_SYS_IBAT2U@l
mtspr IBAT2L, r4
mtspr IBAT2U, r3
isync
- lis r4, CFG_DBAT2L@h
- ori r4, r4, CFG_DBAT2L@l
- lis r3, CFG_DBAT2U@h
- ori r3, r3, CFG_DBAT2U@l
+ lis r4, CONFIG_SYS_DBAT2L@h
+ ori r4, r4, CONFIG_SYS_DBAT2L@l
+ lis r3, CONFIG_SYS_DBAT2U@h
+ ori r3, r3, CONFIG_SYS_DBAT2U@l
mtspr DBAT2L, r4
mtspr DBAT2U, r3
isync
- lis r4, CFG_IBAT3L@h
- ori r4, r4, CFG_IBAT3L@l
- lis r3, CFG_IBAT3U@h
- ori r3, r3, CFG_IBAT3U@l
+ lis r4, CONFIG_SYS_IBAT3L@h
+ ori r4, r4, CONFIG_SYS_IBAT3L@l
+ lis r3, CONFIG_SYS_IBAT3U@h
+ ori r3, r3, CONFIG_SYS_IBAT3U@l
mtspr IBAT3L, r4
mtspr IBAT3U, r3
isync
- lis r4, CFG_DBAT3L@h
- ori r4, r4, CFG_DBAT3L@l
- lis r3, CFG_DBAT3U@h
- ori r3, r3, CFG_DBAT3U@l
+ lis r4, CONFIG_SYS_DBAT3L@h
+ ori r4, r4, CONFIG_SYS_DBAT3L@l
+ lis r3, CONFIG_SYS_DBAT3U@h
+ ori r3, r3, CONFIG_SYS_DBAT3U@l
mtspr DBAT3L, r4
mtspr DBAT3U, r3
isync
diff --git a/cpu/mpc824x/u-boot.lds b/cpu/mpc824x/u-boot.lds
index aa3050d..8c7e135 100644
--- a/cpu/mpc824x/u-boot.lds
+++ b/cpu/mpc824x/u-boot.lds
@@ -118,6 +118,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/cpu/mpc8260/commproc.c b/cpu/mpc8260/commproc.c
index 8777e77..94f6bc2 100644
--- a/cpu/mpc8260/commproc.c
+++ b/cpu/mpc8260/commproc.c
@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
void
m8260_cpm_reset(void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile ulong count;
/* Reclaim the DP memory for our use.
@@ -54,7 +54,7 @@ m8260_cpm_reset(void)
uint
m8260_cpm_dpalloc(uint size, uint align)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
uint retloc;
uint align_mask, off;
uint savebase;
@@ -110,7 +110,7 @@ m8260_cpm_hostalloc(uint size, uint align)
void
m8260_cpm_setbrg(uint brg, uint rate)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile uint *bp;
uint cd = BRG_UART_CLK / rate;
@@ -133,7 +133,7 @@ m8260_cpm_setbrg(uint brg, uint rate)
void
m8260_cpm_fastbrg(uint brg, uint rate, int div16)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
@@ -158,7 +158,7 @@ m8260_cpm_fastbrg(uint brg, uint rate, int div16)
void
m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile uint *bp;
if (brg < 4) {
@@ -181,7 +181,7 @@ m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
void post_word_store (ulong a)
{
volatile ulong *save_addr =
- (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
+ (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
*save_addr = a;
}
@@ -189,7 +189,7 @@ void post_word_store (ulong a)
ulong post_word_load (void)
{
volatile ulong *save_addr =
- (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
+ (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
return *save_addr;
}
@@ -201,7 +201,7 @@ ulong post_word_load (void)
void bootcount_store (ulong a)
{
volatile ulong *save_addr =
- (volatile ulong *)(CFG_IMMR + CPM_BOOTCOUNT_ADDR);
+ (volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR);
save_addr[0] = a;
save_addr[1] = BOOTCOUNT_MAGIC;
@@ -210,7 +210,7 @@ void bootcount_store (ulong a)
ulong bootcount_load (void)
{
volatile ulong *save_addr =
- (volatile ulong *)(CFG_IMMR + CPM_BOOTCOUNT_ADDR);
+ (volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR);
if (save_addr[1] != BOOTCOUNT_MAGIC)
return 0;
diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c
index efb8ed6..b9e748a 100644
--- a/cpu/mpc8260/cpu.c
+++ b/cpu/mpc8260/cpu.c
@@ -44,6 +44,7 @@
#include <watchdog.h>
#include <command.h>
#include <mpc8260.h>
+#include <netdev.h>
#include <asm/processor.h>
#include <asm/cpm_8260.h>
@@ -61,7 +62,7 @@ extern int get_cpu_str_f (char *buf);
int checkcpu (void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
ulong clock = gd->cpu_clk;
uint pvr = get_pvr ();
uint immr, rev, m, k;
@@ -88,7 +89,7 @@ int checkcpu (void)
rev = pvr & 0xff;
immr = immap->im_memctl.memc_immr;
- if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
+ if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR)
return -1; /* whoops! someone moved the IMMR */
#if defined(CONFIG_GET_CPU_STR_F)
@@ -178,7 +179,7 @@ int checkcpu (void)
void upmconfig (uint upm, uint * table, uint size)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */
uint i;
@@ -241,7 +242,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong msr, addr;
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */
@@ -255,15 +256,15 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
-#ifdef CFG_RESET_ADDRESS
- addr = CFG_RESET_ADDRESS;
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
- * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
+ * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
* - sizeof (ulong) is usually a valid address. Better pick an address
- * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
+ * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
*/
- addr = CFG_MONITOR_BASE - sizeof (ulong);
+ addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
((void (*)(void)) addr) ();
return 1;
@@ -293,7 +294,7 @@ void watchdog_reset (void)
{
int re_enable = disable_interrupts ();
- reset_8260_watchdog ((immap_t *) CFG_IMMR);
+ reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR);
if (re_enable)
enable_interrupts ();
}
@@ -315,3 +316,15 @@ void ft_cpu_setup (void *blob, bd_t *bd)
do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
}
#endif /* CONFIG_OF_LIBFDT */
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_ETHER_ON_FCC)
+ fec_initialize(bis);
+#endif
+ return 0;
+}
diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c
index 36fc1eb..1d52773 100644
--- a/cpu/mpc8260/cpu_init.c
+++ b/cpu/mpc8260/cpu_init.c
@@ -114,7 +114,7 @@ void cpu_init_f (volatile immap_t * immr)
extern void m8260_cpm_reset (void);
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
@@ -124,45 +124,45 @@ void cpu_init_f (volatile immap_t * immr)
immr->im_clkrst.car_rsr = RSR_ALLBITS;
/* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
- immr->im_clkrst.car_rmr = CFG_RMR;
+ immr->im_clkrst.car_rmr = CONFIG_SYS_RMR;
/* BCR - Bus Configuration Register (4-25) */
-#if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE)
+#if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE)
if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
- immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_60x, 0x80000010);
+ immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010);
} else {
- immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_SINGLE, 0x80000010);
+ immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010);
}
#else
- immr->im_siu_conf.sc_bcr = CFG_BCR;
+ immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR;
#endif
/* SIUMCR - contains debug pin configuration (4-31) */
-#if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH)
+#if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH)
cpu_clk = board_get_cpu_clk_f ();
if (cpu_clk >= 100000000) {
- immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_HIGH, 0x9f3cc000);
+ immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000);
} else {
- immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_LOW, 0x9f3cc000);
+ immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000);
}
#else
- immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
+ immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
#endif
config_8260_ioports (immr);
/* initialize time counter status and control register (4-40) */
- immr->im_sit.sit_tmcntsc = CFG_TMCNTSC;
+ immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC;
/* initialize the PIT (4-42) */
- immr->im_sit.sit_piscr = CFG_PISCR;
+ immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
/* System clock control register (9-8) */
sccr = immr->im_clkrst.car_sccr &
(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
immr->im_clkrst.car_sccr = sccr |
- (CFG_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
+ (CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
#endif /* !CONFIG_COGENT */
/*
@@ -174,71 +174,71 @@ void cpu_init_f (volatile immap_t * immr)
* has been determined
*/
-#if defined(CFG_OR0_REMAP)
- memctl->memc_or0 = CFG_OR0_REMAP;
+#if defined(CONFIG_SYS_OR0_REMAP)
+ memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
#endif
-#if defined(CFG_OR1_REMAP)
- memctl->memc_or1 = CFG_OR1_REMAP;
+#if defined(CONFIG_SYS_OR1_REMAP)
+ memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
#endif
/* now restrict to preliminary range */
/* the PS came from the HRCW, don´t change it */
- memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK);
- memctl->memc_or0 = CFG_OR0_PRELIM;
+ memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CONFIG_SYS_BR0_PRELIM, BRx_PS_MSK);
+ memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
-#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
- memctl->memc_or1 = CFG_OR1_PRELIM;
- memctl->memc_br1 = CFG_BR1_PRELIM;
+#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
+ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+ memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
#endif
-#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
- memctl->memc_or2 = CFG_OR2_PRELIM;
- memctl->memc_br2 = CFG_BR2_PRELIM;
+#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
+ memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+ memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
#endif
-#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
- memctl->memc_or3 = CFG_OR3_PRELIM;
- memctl->memc_br3 = CFG_BR3_PRELIM;
+#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
+ memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
#endif
-#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
- memctl->memc_or4 = CFG_OR4_PRELIM;
- memctl->memc_br4 = CFG_BR4_PRELIM;
+#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
+ memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+ memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
#endif
-#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
- memctl->memc_or5 = CFG_OR5_PRELIM;
- memctl->memc_br5 = CFG_BR5_PRELIM;
+#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
+ memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
+ memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
#endif
-#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
- memctl->memc_or6 = CFG_OR6_PRELIM;
- memctl->memc_br6 = CFG_BR6_PRELIM;
+#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
+ memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
+ memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
#endif
-#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
- memctl->memc_or7 = CFG_OR7_PRELIM;
- memctl->memc_br7 = CFG_BR7_PRELIM;
+#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
+ memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
+ memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
#endif
-#if defined(CFG_BR8_PRELIM) && defined(CFG_OR8_PRELIM)
- memctl->memc_or8 = CFG_OR8_PRELIM;
- memctl->memc_br8 = CFG_BR8_PRELIM;
+#if defined(CONFIG_SYS_BR8_PRELIM) && defined(CONFIG_SYS_OR8_PRELIM)
+ memctl->memc_or8 = CONFIG_SYS_OR8_PRELIM;
+ memctl->memc_br8 = CONFIG_SYS_BR8_PRELIM;
#endif
-#if defined(CFG_BR9_PRELIM) && defined(CFG_OR9_PRELIM)
- memctl->memc_or9 = CFG_OR9_PRELIM;
- memctl->memc_br9 = CFG_BR9_PRELIM;
+#if defined(CONFIG_SYS_BR9_PRELIM) && defined(CONFIG_SYS_OR9_PRELIM)
+ memctl->memc_or9 = CONFIG_SYS_OR9_PRELIM;
+ memctl->memc_br9 = CONFIG_SYS_BR9_PRELIM;
#endif
-#if defined(CFG_BR10_PRELIM) && defined(CFG_OR10_PRELIM)
- memctl->memc_or10 = CFG_OR10_PRELIM;
- memctl->memc_br10 = CFG_BR10_PRELIM;
+#if defined(CONFIG_SYS_BR10_PRELIM) && defined(CONFIG_SYS_OR10_PRELIM)
+ memctl->memc_or10 = CONFIG_SYS_OR10_PRELIM;
+ memctl->memc_br10 = CONFIG_SYS_BR10_PRELIM;
#endif
-#if defined(CFG_BR11_PRELIM) && defined(CFG_OR11_PRELIM)
- memctl->memc_or11 = CFG_OR11_PRELIM;
- memctl->memc_br11 = CFG_BR11_PRELIM;
+#if defined(CONFIG_SYS_BR11_PRELIM) && defined(CONFIG_SYS_OR11_PRELIM)
+ memctl->memc_or11 = CONFIG_SYS_OR11_PRELIM;
+ memctl->memc_br11 = CONFIG_SYS_BR11_PRELIM;
#endif
m8260_cpm_reset ();
@@ -251,7 +251,7 @@ int cpu_init_r (void)
{
volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base;
- immr->im_cpm.cp_rccr = CFG_RCCR;
+ immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
return (0);
}
diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c
index 37bf445..3ab57eb 100644
--- a/cpu/mpc8260/ether_fcc.c
+++ b/cpu/mpc8260/ether_fcc.c
@@ -73,8 +73,8 @@ static struct ether_fcc_info_s
PROFF_FCC1,
CPM_CR_FCC1_SBLOCK,
CPM_CR_FCC1_PAGE,
- CFG_CMXFCR_MASK1,
- CFG_CMXFCR_VALUE1
+ CONFIG_SYS_CMXFCR_MASK1,
+ CONFIG_SYS_CMXFCR_VALUE1
},
#endif
@@ -84,8 +84,8 @@ static struct ether_fcc_info_s
PROFF_FCC2,
CPM_CR_FCC2_SBLOCK,
CPM_CR_FCC2_PAGE,
- CFG_CMXFCR_MASK2,
- CFG_CMXFCR_VALUE2
+ CONFIG_SYS_CMXFCR_MASK2,
+ CONFIG_SYS_CMXFCR_VALUE2
},
#endif
@@ -95,8 +95,8 @@ static struct ether_fcc_info_s
PROFF_FCC3,
CPM_CR_FCC3_SBLOCK,
CPM_CR_FCC3_PAGE,
- CFG_CMXFCR_MASK3,
- CFG_CMXFCR_VALUE3
+ CONFIG_SYS_CMXFCR_MASK3,
+ CONFIG_SYS_CMXFCR_VALUE3
},
#endif
};
@@ -225,7 +225,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
{
struct ether_fcc_info_s * info = dev->priv;
int i;
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8260_t *cp = &(immr->im_cpm);
fcc_enet_t *pram_ptr;
unsigned long mem_addr;
@@ -246,7 +246,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
/* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
- immr->im_fcc[info->ether_index].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ immr->im_fcc[info->ether_index].fcc_fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
/* 28.9 - (6): FDSR: Ethernet Syn */
immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555;
@@ -296,10 +296,10 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
*/
pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
- CFG_CPMFCR_RAMTYPE) << 24;
+ CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
- CFG_CPMFCR_RAMTYPE) << 24;
+ CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
/* protocol-specific area */
@@ -366,7 +366,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
static void fec_halt(struct eth_device* dev)
{
struct ether_fcc_info_s * info = dev->priv;
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
/* write GFMR: disable tx/rx */
immr->im_fcc[info->ether_index].fcc_gfmr &=
@@ -646,7 +646,7 @@ swap16 (unsigned short x)
void
eth_loopback_test (void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8260_t *cp = &(immr->im_cpm);
int c, nclosed;
ulong runtime, nmsec;
diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c
index 633d053..c65f0e0 100644
--- a/cpu/mpc8260/ether_scc.c
+++ b/cpu/mpc8260/ether_scc.c
@@ -77,8 +77,8 @@
#define TX_BUF_CNT 2
-#if !defined(CFG_SCC_TOUT_LOOP)
- #define CFG_SCC_TOUT_LOOP 1000000
+#if !defined(CONFIG_SYS_SCC_TOUT_LOOP)
+ #define CONFIG_SYS_SCC_TOUT_LOOP 1000000
#endif
static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ];
@@ -111,7 +111,7 @@ int eth_send(volatile void *packet, int length)
}
for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
- if (i >= CFG_SCC_TOUT_LOOP) {
+ if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
puts ("scc: tx buffer not ready\n");
goto out;
}
@@ -123,7 +123,7 @@ int eth_send(volatile void *packet, int length)
BD_ENET_TX_WRAP);
for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
- if (i >= CFG_SCC_TOUT_LOOP) {
+ if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
puts ("scc: tx error\n");
goto out;
}
@@ -187,7 +187,7 @@ int eth_rx(void)
int eth_init(bd_t *bis)
{
int i;
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
scc_enet_t *pram_ptr;
uint dpaddr;
@@ -203,7 +203,7 @@ int eth_init(bd_t *bis)
/* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */
immr->im_cpmux.cmx_uar = 0;
immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) |
- CFG_CMXSCR_VALUE);
+ CONFIG_SYS_CMXSCR_VALUE);
/* 24.21 (6) write RBASE and TBASE to parameter RAM */
@@ -340,7 +340,7 @@ int eth_init(bd_t *bis)
void eth_halt(void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR |
SCC_GSMRL_ENT);
}
@@ -348,7 +348,7 @@ void eth_halt(void)
#if 0
void restart(void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
SCC_GSMRL_ENT);
}
diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c
index c3af7b6..35cf8f1 100644
--- a/cpu/mpc8260/i2c.c
+++ b/cpu/mpc8260/i2c.c
@@ -36,6 +36,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_I2C_MULTI_BUS)
+static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
+#endif /* CONFIG_I2C_MULTI_BUS */
+
/* uSec to wait between polls of the i2c */
#define DELAY_US 100
/* uSec to wait for the CPM to start processing the buffer */
@@ -50,12 +54,12 @@ DECLARE_GLOBAL_DATA_PTR;
/*-----------------------------------------------------------------------
* Set default values
*/
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED 50000
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED 50000
#endif
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE 0xFE
+#ifndef CONFIG_SYS_I2C_SLAVE
+#define CONFIG_SYS_I2C_SLAVE 0xFE
#endif
/*-----------------------------------------------------------------------
*/
@@ -172,7 +176,7 @@ i2c_roundrate(int hz, int speed, int filter, int modval,
*/
static int i2c_setrate(int hz, int speed)
{
- immap_t *immap = (immap_t *)CFG_IMMR ;
+ immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
int brgval,
modval, /* 0-3 */
@@ -215,7 +219,7 @@ static int i2c_setrate(int hz, int speed)
void i2c_init(int speed, int slaveadd)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
volatile iic_t *iip;
@@ -223,7 +227,7 @@ void i2c_init(int speed, int slaveadd)
volatile I2C_BD *rxbd, *txbd;
uint dpaddr;
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
/* call board specific i2c bus reset routine before accessing the */
/* environment, which might be in a chip on that bus. For details */
/* about this problem see doc/I2C_Edge_Conditions. */
@@ -266,7 +270,7 @@ void i2c_init(int speed, int slaveadd)
* divide BRGCLK by 1)
*/
PRINTD(("[I2C] Setting rate...\n"));
- i2c_setrate (gd->brg_clk, CFG_I2C_SPEED) ;
+ i2c_setrate (gd->brg_clk, CONFIG_SYS_I2C_SPEED) ;
/* Set I2C controller in master mode */
i2c->i2c_i2com = 0x01;
@@ -305,7 +309,7 @@ void i2c_init(int speed, int slaveadd)
static
void i2c_newio(i2c_state_t *state)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile iic_t *iip;
uint dpaddr;
@@ -490,7 +494,7 @@ int i2c_receive(i2c_state_t *state,
static
int i2c_doio(i2c_state_t *state)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile iic_t *iip;
volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
volatile I2C_BD *txbd, *rxbd;
@@ -663,7 +667,7 @@ i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
@@ -675,7 +679,7 @@ i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
* be one byte because the extra address bits are hidden in the
* chip address.
*/
- chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
i2c_newio(&state);
@@ -712,7 +716,7 @@ i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
@@ -724,7 +728,7 @@ i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
* be one byte because the extra address bits are hidden in the
* chip address.
*/
- chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
i2c_newio(&state);
@@ -749,20 +753,49 @@ i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
return 0;
}
-uchar
-i2c_reg_read(uchar chip, uchar reg)
+#if defined(CONFIG_I2C_MULTI_BUS)
+/*
+ * Functions for multiple I2C bus handling
+ */
+unsigned int i2c_get_bus_num(void)
{
- uchar buf;
-
- i2c_read(chip, reg, 1, &buf, 1);
+ return i2c_bus_num;
+}
- return (buf);
+int i2c_set_bus_num(unsigned int bus)
+{
+#if defined(CONFIG_I2C_MUX)
+ if (bus < CONFIG_SYS_MAX_I2C_BUS) {
+ i2c_bus_num = bus;
+ } else {
+ int ret;
+
+ ret = i2x_mux_select_mux(bus);
+ if (ret == 0)
+ i2c_bus_num = bus;
+ else
+ return ret;
+ }
+#else
+ if (bus >= CONFIG_SYS_MAX_I2C_BUS)
+ return -1;
+ i2c_bus_num = bus;
+#endif
+ return 0;
+}
+/* TODO: add 100/400k switching */
+unsigned int i2c_get_bus_speed(void)
+{
+ return CONFIG_SYS_I2C_SPEED;
}
-void
-i2c_reg_write(uchar chip, uchar reg, uchar val)
+int i2c_set_bus_speed(unsigned int speed)
{
- i2c_write(chip, reg, 1, &val, 1);
+ if (speed != CONFIG_SYS_I2C_SPEED)
+ return -1;
+
+ return 0;
}
+#endif /* CONFIG_I2C_MULTI_BUS */
#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/mpc8260/interrupts.c b/cpu/mpc8260/interrupts.c
index bf0d4d0..a7700c4 100644
--- a/cpu/mpc8260/interrupts.c
+++ b/cpu/mpc8260/interrupts.c
@@ -82,7 +82,7 @@ static u_char irq_to_siubit[] = {
static void m8260_mask_irq (unsigned int irq_nr)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int bit, word;
volatile uint *simr;
@@ -96,7 +96,7 @@ static void m8260_mask_irq (unsigned int irq_nr)
static void m8260_unmask_irq (unsigned int irq_nr)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int bit, word;
volatile uint *simr;
@@ -110,7 +110,7 @@ static void m8260_unmask_irq (unsigned int irq_nr)
static void m8260_mask_and_ack (unsigned int irq_nr)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int bit, word;
volatile uint *simr, *sipnr;
@@ -126,7 +126,7 @@ static void m8260_mask_and_ack (unsigned int irq_nr)
static int m8260_get_irq (struct pt_regs *regs)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int irq;
unsigned long bits;
@@ -142,9 +142,9 @@ static int m8260_get_irq (struct pt_regs *regs)
int interrupt_init_cpu (unsigned *decrementer_count)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- *decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
+ *decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ;
/* Initialize the default interrupt mapping priorities */
immr->im_intctl.ic_sicr = 0;
diff --git a/cpu/mpc8260/kgdb.S b/cpu/mpc8260/kgdb.S
index dae87bb..c5936c7 100644
--- a/cpu/mpc8260/kgdb.S
+++ b/cpu/mpc8260/kgdb.S
@@ -50,21 +50,21 @@ kgdb_flush_cache_all:
.globl kgdb_flush_cache_range
kgdb_flush_cache_range:
- li r5,CFG_CACHELINE_SIZE-1
+ li r5,CONFIG_SYS_CACHELINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
- srwi. r4,r4,CFG_CACHELINE_SHIFT
+ srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
beqlr
mtctr r4
mr r6,r3
1: dcbst 0,r3
- addi r3,r3,CFG_CACHELINE_SIZE
+ addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
sync /* wait for dcbst's to get to ram */
mtctr r4
2: icbi 0,r6
- addi r6,r6,CFG_CACHELINE_SIZE
+ addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
bdnz 2b
SYNC
blr
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index 8230364..378d6c5 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -70,23 +70,23 @@ DECLARE_GLOBAL_DATA_PTR;
* This window is set up using the first set of Inbound ATU registers
*/
-#ifndef CFG_PCI_SLV_MEM_LOCAL
-#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
+#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL
+#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
#else
-#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
+#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL
#endif
-#ifndef CFG_PCI_SLV_MEM_BUS
+#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS
#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
#else
-#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
+#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS
#endif
-#ifndef CFG_PICMR0_MASK_ATTRIB
+#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB
#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
PICMR_PREFETCH_EN)
#else
-#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
+#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB
#endif
/*
@@ -97,29 +97,29 @@ DECLARE_GLOBAL_DATA_PTR;
*/
/* PCIBR0 */
-#ifndef CFG_PCI_MSTR0_LOCAL
+#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL
#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
#else
-#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
+#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL
#endif
-#ifndef CFG_PCIMSK0_MASK
+#ifndef CONFIG_SYS_PCIMSK0_MASK
#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
#else
-#define PCIMSK0_MASK CFG_PCIMSK0_MASK
+#define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK
#endif
/* PCIBR1 */
-#ifndef CFG_PCI_MSTR1_LOCAL
+#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL
#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
#else
-#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL
+#define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL
#endif
-#ifndef CFG_PCIMSK1_MASK
+#ifndef CONFIG_SYS_PCIMSK1_MASK
#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
#else
-#define PCIMSK1_MASK CFG_PCIMSK1_MASK
+#define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK
#endif
/*
@@ -128,34 +128,34 @@ DECLARE_GLOBAL_DATA_PTR;
* in the bridge.
*/
-#ifndef CFG_PCI_MSTR_MEM_LOCAL
+#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL
#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
#else
-#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
+#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
#endif
-#ifndef CFG_PCI_MSTR_MEM_BUS
+#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS
#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
#else
-#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
+#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS
#endif
-#ifndef CFG_CPU_PCI_MEM_START
+#ifndef CONFIG_SYS_CPU_PCI_MEM_START
#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
#else
-#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
+#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START
#endif
-#ifndef CFG_PCI_MSTR_MEM_SIZE
+#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE
#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
#else
-#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
+#define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE
#endif
-#ifndef CFG_POCMR0_MASK_ATTRIB
+#ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB
#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
#else
-#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
+#define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB
#endif
/*
@@ -164,34 +164,34 @@ DECLARE_GLOBAL_DATA_PTR;
* in the bridge.
*/
-#ifndef CFG_PCI_MSTR_MEMIO_LOCAL
+#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
#else
-#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
+#define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
#endif
-#ifndef CFG_PCI_MSTR_MEMIO_BUS
+#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS
#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
#else
-#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
+#define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS
#endif
-#ifndef CFG_CPU_PCI_MEMIO_START
+#ifndef CONFIG_SYS_CPU_PCI_MEMIO_START
#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
#else
-#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
+#define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START
#endif
-#ifndef CFG_PCI_MSTR_MEMIO_SIZE
+#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
#else
-#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
+#define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
#endif
-#ifndef CFG_POCMR1_MASK_ATTRIB
+#ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB
#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
#else
-#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
+#define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB
#endif
/*
@@ -200,34 +200,34 @@ DECLARE_GLOBAL_DATA_PTR;
* in the bridge.
*/
-#ifndef CFG_PCI_MSTR_IO_LOCAL
+#ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL
#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
#else
-#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
+#define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL
#endif
-#ifndef CFG_PCI_MSTR_IO_BUS
+#ifndef CONFIG_SYS_PCI_MSTR_IO_BUS
#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
#else
-#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
+#define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS
#endif
-#ifndef CFG_CPU_PCI_IO_START
+#ifndef CONFIG_SYS_CPU_PCI_IO_START
#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
#else
-#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
+#define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START
#endif
-#ifndef CFG_PCI_MSTR_IO_SIZE
+#ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE
#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
#else
-#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
+#define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE
#endif
-#ifndef CFG_POCMR2_MASK_ATTRIB
+#ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB
#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
#else
-#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
+#define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB
#endif
/* PCI bus configuration registers.
@@ -245,11 +245,11 @@ void pci_mpc8250_init (struct pci_controller *hose)
{
u16 tempShort;
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
pci_dev_t host_devno = PCI_BDF (0, 0, 0);
- pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
- CFG_IMMR + PCI_CFG_DATA_REG);
+ pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG,
+ CONFIG_SYS_IMMR + PCI_CFG_DATA_REG);
/*
* Setting required to enable local bus for PCI (SIUMCR [LBPC]).
@@ -413,8 +413,8 @@ void pci_mpc8250_init (struct pci_controller *hose)
gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
#else
pci_set_region (hose->regions + 0,
- CFG_SDRAM_BASE,
- CFG_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_BASE,
0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
#endif
diff --git a/cpu/mpc8260/serial_scc.c b/cpu/mpc8260/serial_scc.c
index 3a6eaf0..4ab6a28 100644
--- a/cpu/mpc8260/serial_scc.c
+++ b/cpu/mpc8260/serial_scc.c
@@ -84,7 +84,7 @@ DECLARE_GLOBAL_DATA_PTR;
int serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -201,7 +201,7 @@ serial_putc(const char c)
if (c == '\n')
serial_putc ('\r');
- im = (immap_t *)CFG_IMMR;
+ im = (immap_t *)CONFIG_SYS_IMMR;
up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
@@ -233,7 +233,7 @@ serial_getc(void)
volatile immap_t *im;
unsigned char c;
- im = (immap_t *)CFG_IMMR;
+ im = (immap_t *)CONFIG_SYS_IMMR;
up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
@@ -257,7 +257,7 @@ serial_tstc()
volatile scc_uart_t *up;
volatile immap_t *im;
- im = (immap_t *)CFG_IMMR;
+ im = (immap_t *)CONFIG_SYS_IMMR;
up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
@@ -321,7 +321,7 @@ serial_tstc()
void
kgdb_serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -440,7 +440,7 @@ putDebugChar(const char c)
if (c == '\n')
putDebugChar ('\r');
- im = (immap_t *)CFG_IMMR;
+ im = (immap_t *)CONFIG_SYS_IMMR;
up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
@@ -472,7 +472,7 @@ getDebugChar(void)
volatile immap_t *im;
unsigned char c;
- im = (immap_t *)CFG_IMMR;
+ im = (immap_t *)CONFIG_SYS_IMMR;
up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
diff --git a/cpu/mpc8260/serial_smc.c b/cpu/mpc8260/serial_smc.c
index f3dffeb..a6efa66 100644
--- a/cpu/mpc8260/serial_smc.c
+++ b/cpu/mpc8260/serial_smc.c
@@ -76,7 +76,7 @@ static unsigned char brg_map[] = {
int serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile smc_t *sp;
volatile smc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -186,7 +186,7 @@ serial_putc(const char c)
volatile cbd_t *tbdf;
volatile char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
if (c == '\n')
serial_putc ('\r');
@@ -220,7 +220,7 @@ serial_getc(void)
volatile cbd_t *rbdf;
volatile unsigned char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
unsigned char c;
up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
@@ -243,7 +243,7 @@ serial_tstc()
{
volatile cbd_t *rbdf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
@@ -289,7 +289,7 @@ serial_tstc()
void
kgdb_serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile smc_t *sp;
volatile smc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -401,7 +401,7 @@ putDebugChar(const char c)
volatile cbd_t *tbdf;
volatile char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
if (c == '\n')
putDebugChar ('\r');
@@ -435,7 +435,7 @@ getDebugChar(void)
volatile cbd_t *rbdf;
volatile unsigned char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
unsigned char c;
up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c
index 8d280fb..0e1c2b0 100644
--- a/cpu/mpc8260/speed.c
+++ b/cpu/mpc8260/speed.c
@@ -107,7 +107,7 @@ corecnf_t corecnf_tab[] = {
int get_clocks (void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
ulong clkin;
ulong sccr, dfbrg;
ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
@@ -191,7 +191,7 @@ int get_clocks (void)
int prt_8260_clks (void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
ulong sccr, dfbrg;
ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf;
corecnf_t *cp;
diff --git a/cpu/mpc8260/spi.c b/cpu/mpc8260/spi.c
index c1a607c..f5d2ac3 100644
--- a/cpu/mpc8260/spi.c
+++ b/cpu/mpc8260/spi.c
@@ -63,8 +63,8 @@
* The value 0x2000 makes it far enough from the start of the data
* area (as well as from the stack pointer).
* --------------------------------------------------------------- */
-#ifndef CFG_SPI_INIT_OFFSET
-#define CFG_SPI_INIT_OFFSET 0x2000
+#ifndef CONFIG_SYS_SPI_INIT_OFFSET
+#define CONFIG_SYS_SPI_INIT_OFFSET 0x2000
#endif
#define CPM_SPI_BASE 0x100
@@ -119,11 +119,11 @@ ssize_t spi_xfer (size_t);
* Initially we place the RX and TX buffers at a fixed location in DPRAM!
* ---------------------------------------------------------------------- */
static uchar *rxbuf =
- (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase
- [CFG_SPI_INIT_OFFSET];
+ (uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase
+ [CONFIG_SYS_SPI_INIT_OFFSET];
static uchar *txbuf =
- (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase
- [CFG_SPI_INIT_OFFSET+MAX_BUFFER];
+ (uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase
+ [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
/* **************************************************************************
*
@@ -143,7 +143,7 @@ void spi_init_f (void)
volatile cpm8260_t *cp;
volatile cbd_t *tbdf, *rbdf;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
cp = (cpm8260_t *) &immr->im_cpm;
*(ushort *)(&immr->im_dprambase[PROFF_SPI_BASE]) = PROFF_SPI;
@@ -200,7 +200,7 @@ void spi_init_f (void)
/* Allocate space for one transmit and one receive buffer
* descriptor in the DP ram
*/
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = m8260_cpm_dpalloc (sizeof(cbd_t)*2, 8);
#else
dpaddr = CPM_SPI_BASE;
@@ -279,7 +279,7 @@ void spi_init_r (void)
volatile cpm8260_t *cp;
volatile cbd_t *tbdf, *rbdf;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
cp = (cpm8260_t *) &immr->im_cpm;
spi = (spi_t *)&immr->im_dprambase[PROFF_SPI];
@@ -365,7 +365,7 @@ ssize_t spi_xfer (size_t count)
DPRINT (("*** spi_xfer entered ***\n"));
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
cp = (cpm8260_t *) &immr->im_cpm;
spi = (spi_t *)&immr->im_dprambase[PROFF_SPI];
diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S
index 7f5dc81..379f2fb 100644
--- a/cpu/mpc8260/start.S
+++ b/cpu/mpc8260/start.S
@@ -27,6 +27,7 @@
*/
#include <config.h>
#include <mpc8260.h>
+#include <timestamp.h>
#include <version.h>
#define CONFIG_8260 1 /* needed for Linux kernel header files */
@@ -85,7 +86,7 @@
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
/*
@@ -127,14 +128,14 @@ version_string:
.text
.globl _hrcw_table
_hrcw_table:
- _HRCW_TABLE_ENTRY(CFG_HRCW_MASTER)
- _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE1)
- _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE2)
- _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE3)
- _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE4)
- _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE5)
- _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE6)
- _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE7)
+ _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_MASTER)
+ _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE1)
+ _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE2)
+ _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE3)
+ _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE4)
+ _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE5)
+ _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE6)
+ _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE7)
/*
* After configuration, a system reset exception is executed using the
* vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP]
@@ -172,8 +173,8 @@ _start_warm:
b boot_warm
boot_cold:
-#if defined(CONFIG_MPC8260ADS) && defined(CFG_DEFAULT_IMMR)
- lis r3, CFG_DEFAULT_IMMR@h
+#if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR)
+ lis r3, CONFIG_SYS_DEFAULT_IMMR@h
nop
lwz r4, 0(r3)
nop
@@ -183,7 +184,7 @@ boot_cold:
nop
stw r4, 0(r3)
nop
-#endif /* CONFIG_MPC8260ADS && CFG_DEFAULT_IMMR */
+#endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */
boot_warm:
mfmsr r5 /* save msr contents */
@@ -195,24 +196,24 @@ boot_warm:
bl cogent_init_8260
#endif /* CONFIG_COGENT */
-#if defined(CFG_DEFAULT_IMMR)
- lis r3, CFG_IMMR@h
- ori r3, r3, CFG_IMMR@l
- lis r4, CFG_DEFAULT_IMMR@h
+#if defined(CONFIG_SYS_DEFAULT_IMMR)
+ lis r3, CONFIG_SYS_IMMR@h
+ ori r3, r3, CONFIG_SYS_IMMR@l
+ lis r4, CONFIG_SYS_DEFAULT_IMMR@h
stw r3, 0x1A8(r4)
-#endif /* CFG_DEFAULT_IMMR */
+#endif /* CONFIG_SYS_DEFAULT_IMMR */
/* Initialise the MPC8260 processor core */
/*--------------------------------------------------------------*/
bl init_8260_core
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
/* When booting from ROM (Flash or EPROM), clear the */
/* Address Mask in OR0 so ROM appears everywhere */
/*--------------------------------------------------------------*/
- lis r3, (CFG_IMMR+IM_REGBASE)@h
+ lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
lwz r4, IM_OR0@l(r3)
li r5, 0x7fff
and r4, r4, r5
@@ -221,20 +222,20 @@ boot_warm:
/* Calculate absolute address in FLASH and jump there */
/*--------------------------------------------------------------*/
- lis r3, CFG_MONITOR_BASE@h
- ori r3, r3, CFG_MONITOR_BASE@l
+ lis r3, CONFIG_SYS_MONITOR_BASE@h
+ ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
in_flash:
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
/* initialize some things that are hard to access from C */
/*--------------------------------------------------------------*/
- lis r3, CFG_IMMR@h /* set up stack in internal DPRAM */
- ori r1, r3, CFG_INIT_SP_OFFSET
+ lis r3, CONFIG_SYS_IMMR@h /* set up stack in internal DPRAM */
+ ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
@@ -458,18 +459,18 @@ cogent_init_8260:
/* Taken from page 14 of CMA282 manual */
/*--------------------------------------------------------------*/
- lis r4, (CFG_IMMR+IM_REGBASE)@h
- lis r3, CFG_IMMR@h
+ lis r4, (CONFIG_SYS_IMMR+IM_REGBASE)@h
+ lis r3, CONFIG_SYS_IMMR@h
stw r3, IM_IMMR@l(r4)
lwz r3, IM_IMMR@l(r4)
stw r3, 0(r0)
- lis r3, CFG_SYPCR@h
- ori r3, r3, CFG_SYPCR@l
+ lis r3, CONFIG_SYS_SYPCR@h
+ ori r3, r3, CONFIG_SYS_SYPCR@l
stw r3, IM_SYPCR@l(r4)
lwz r3, IM_SYPCR@l(r4)
stw r3, 4(r0)
- lis r3, CFG_SCCR@h
- ori r3, r3, CFG_SCCR@l
+ lis r3, CONFIG_SYS_SCCR@h
+ ori r3, r3, CONFIG_SYS_SCCR@l
stw r3, IM_SCCR@l(r4)
lwz r3, IM_SCCR@l(r4)
stw r3, 8(r0)
@@ -521,10 +522,10 @@ init_8260_core:
/* Initialise the SYPCR early, and reset the watchdog (if req) */
/*--------------------------------------------------------------*/
- lis r3, (CFG_IMMR+IM_REGBASE)@h
+ lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
#if !defined(CONFIG_COGENT)
- lis r4, CFG_SYPCR@h
- ori r4, r4, CFG_SYPCR@l
+ lis r4, CONFIG_SYS_SYPCR@h
+ ori r4, r4, CONFIG_SYS_SYPCR@l
stw r4, IM_SYPCR@l(r3)
#endif /* !CONFIG_COGENT */
#if defined(CONFIG_WATCHDOG)
@@ -538,18 +539,18 @@ init_8260_core:
/* HID0 also contains cache control */
/*--------------------------------------------------------------*/
- lis r3, CFG_HID0_INIT@h
- ori r3, r3, CFG_HID0_INIT@l
+ lis r3, CONFIG_SYS_HID0_INIT@h
+ ori r3, r3, CONFIG_SYS_HID0_INIT@l
SYNC
mtspr HID0, r3
- lis r3, CFG_HID0_FINAL@h
- ori r3, r3, CFG_HID0_FINAL@l
+ lis r3, CONFIG_SYS_HID0_FINAL@h
+ ori r3, r3, CONFIG_SYS_HID0_FINAL@l
SYNC
mtspr HID0, r3
- lis r3, CFG_HID2@h
- ori r3, r3, CFG_HID2@l
+ lis r3, CONFIG_SYS_HID2@h
+ ori r3, r3, CONFIG_SYS_HID2@l
mtspr HID2, r3
/* clear all BAT's */
@@ -619,29 +620,29 @@ init_8260_core:
.globl init_debug
init_debug:
- lis r3, (CFG_IMMR+IM_REGBASE)@h
+ lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
/* Quick and dirty hack to enable the RAM and copy the */
/* vectors so that we can take exceptions. */
/*--------------------------------------------------------------*/
/* write Memory Refresh Prescaler */
- li r4, CFG_MPTPR
+ li r4, CONFIG_SYS_MPTPR
sth r4, IM_MPTPR@l(r3)
/* write 60x Refresh Timer */
- li r4, CFG_PSRT
+ li r4, CONFIG_SYS_PSRT
stb r4, IM_PSRT@l(r3)
/* init the 60x SDRAM Mode Register */
- lis r4, (CFG_PSDMR|PSDMR_OP_NORM)@h
- ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM)@l
+ lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@h
+ ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@l
stw r4, IM_PSDMR@l(r3)
/* write Precharge All Banks command */
- lis r4, (CFG_PSDMR|PSDMR_OP_PREA)@h
- ori r4, r4, (CFG_PSDMR|PSDMR_OP_PREA)@l
+ lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@h
+ ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@l
stw r4, IM_PSDMR@l(r3)
stb r0, 0(0)
/* write eight CBR Refresh commands */
- lis r4, (CFG_PSDMR|PSDMR_OP_CBRR)@h
- ori r4, r4, (CFG_PSDMR|PSDMR_OP_CBRR)@l
+ lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@h
+ ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@l
stw r4, IM_PSDMR@l(r3)
stb r0, 0(0)
stb r0, 0(0)
@@ -652,13 +653,13 @@ init_debug:
stb r0, 0(0)
stb r0, 0(0)
/* write Mode Register Write command */
- lis r4, (CFG_PSDMR|PSDMR_OP_MRW)@h
- ori r4, r4, (CFG_PSDMR|PSDMR_OP_MRW)@l
+ lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@h
+ ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@l
stw r4, IM_PSDMR@l(r3)
stb r0, 0(0)
/* write Normal Operation command and enable Refresh */
- lis r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h
- ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l
+ lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h
+ ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l
stw r4, IM_PSDMR@l(r3)
stb r0, 0(0)
/* RAM should now be operational */
@@ -687,7 +688,7 @@ init_debug:
/* an exception is generated (before the instruction at that */
/* location completes). The vector for this exception is 0x1300 */
/*--------------------------------------------------------------*/
- lis r3, CFG_IMMR@h
+ lis r3, CONFIG_SYS_IMMR@h
lwz r3, 0(r3)
mtspr IABR, r3
@@ -695,9 +696,9 @@ init_debug:
/* resides) to a known value - makes it easier to see where */
/* the stack has been written */
/*--------------------------------------------------------------*/
- lis r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@h
- ori r3, r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@l
- li r4, ((CFG_INIT_SP_OFFSET - 4) / 4)
+ lis r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@h
+ ori r3, r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@l
+ li r4, ((CONFIG_SYS_INIT_SP_OFFSET - 4) / 4)
mtctr r4
lis r4, 0xdeadbeaf@h
ori r4, r4, 0xdeadbeaf@l
@@ -807,16 +808,16 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
diff --git a/cpu/mpc8260/traps.c b/cpu/mpc8260/traps.c
index b5d416c..6624544 100644
--- a/cpu/mpc8260/traps.c
+++ b/cpu/mpc8260/traps.c
@@ -111,7 +111,7 @@ _exception(int signr, struct pt_regs *regs)
void dump_pci (void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
printf ("PCI: err status %x err mask %x err ctrl %x\n",
le32_to_cpu (immap->im_pci.pci_esr),
@@ -135,7 +135,7 @@ MachineCheckException(struct pt_regs *regs)
* the PCI exception handler.
*/
#ifdef CONFIG_PCI
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
#ifdef DEBUG
dump_pci();
#endif
diff --git a/cpu/mpc8260/u-boot.lds b/cpu/mpc8260/u-boot.lds
index 39f2ce9..d65a939 100644
--- a/cpu/mpc8260/u-boot.lds
+++ b/cpu/mpc8260/u-boot.lds
@@ -118,6 +118,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 52e4476..587fca3 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -32,6 +32,8 @@
#include <mpc83xx.h>
#include <asm/processor.h>
#include <libfdt.h>
+#include <tsec.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -66,7 +68,7 @@ int checkcpu(void)
CPU_TYPE_ENTRY(8379),
};
- immr = (immap_t *)CFG_IMMR;
+ immr = (immap_t *)CONFIG_SYS_IMMR;
puts("CPU: ");
@@ -123,8 +125,8 @@ int checkcpu(void)
* The 'dummy' variable is used to increment the MAD. 'dummy' is
* supposed to be a pointer to the memory of the device being
* programmed by the UPM. The data in the MDR is written into
- * memory and the MAD is incremented every time there's a read
- * from 'dummy'. Unfortunately, the current prototype for this
+ * memory and the MAD is incremented every time there's a write
+ * to 'dummy'. Unfortunately, the current prototype for this
* function doesn't allow for passing the address of this
* device, and changing the prototype will break a number lots
* of other code, so we need to use a round-about way of finding
@@ -146,9 +148,8 @@ int checkcpu(void)
*/
void upmconfig (uint upm, uint *table, uint size)
{
-#if defined(CONFIG_MPC834X)
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile lbus83xx_t *lbus = &immap->lbus;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ volatile fsl_lbus_t *lbus = &immap->lbus;
volatile uchar *dummy = NULL;
const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
@@ -173,16 +174,13 @@ void upmconfig (uint upm, uint *table, uint size)
for (i = 0; i < size; i++) {
lbus->mdr = table[i];
__asm__ __volatile__ ("sync");
- *dummy; /* Write the value to memory and increment MAD */
+ *dummy = 0; /* Write the value to memory and increment MAD */
__asm__ __volatile__ ("sync");
+ while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
}
/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
*mxmr &= 0xCFFFFFC0;
-#else
- printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
- hang();
-#endif
}
@@ -194,7 +192,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
ulong addr;
#endif
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#ifdef MPC83xx_RESET
/* Interrupts and MMU off */
@@ -233,7 +231,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
- addr = CFG_RESET_ADDRESS;
+ addr = CONFIG_SYS_RESET_ADDRESS;
printf("resetting the board.");
printf("\n");
@@ -264,7 +262,7 @@ void watchdog_reset (void)
int re_enable = disable_interrupts();
/* Reset the 83xx watchdog */
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
immr->wdt.swsrr = 0x556c;
immr->wdt.swsrr = 0xaa39;
@@ -276,7 +274,7 @@ void watchdog_reset (void)
#if defined(CONFIG_DDR_ECC)
void dma_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile dma83xx_t *dma = &immap->dma;
volatile u32 status = swab32(dma->dmasr0);
volatile u32 dmamr0 = swab32(dma->dmamr0);
@@ -307,7 +305,7 @@ void dma_init(void)
uint dma_check(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile dma83xx_t *dma = &immap->dma;
volatile u32 status = swab32(dma->dmasr0);
volatile u32 byte_count = swab32(dma->dmabcr0);
@@ -326,7 +324,7 @@ uint dma_check(void)
int dma_xfer(void *dest, u32 count, void *src)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile dma83xx_t *dma = &immap->dma;
volatile u32 dmamr0;
@@ -358,22 +356,32 @@ int dma_xfer(void *dest, u32 count, void *src)
}
#endif /*CONFIG_DDR_ECC*/
-#ifdef CONFIG_TSEC_ENET
-/* Default initializations for TSEC controllers. To override,
- * create a board-specific function called:
- * int board_eth_init(bd_t *bis)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
*/
-
-extern int tsec_initialize(bd_t * bis, int index, char *devname);
-
int cpu_eth_init(bd_t *bis)
{
-#if defined(CONFIG_TSEC1)
- tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
+#if defined(CONFIG_UEC_ETH1)
+ uec_initialize(0);
+#endif
+#if defined(CONFIG_UEC_ETH2)
+ uec_initialize(1);
#endif
-#if defined(CONFIG_TSEC2)
- tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
+#if defined(CONFIG_UEC_ETH3)
+ uec_initialize(2);
+#endif
+#if defined(CONFIG_UEC_ETH4)
+ uec_initialize(3);
+#endif
+#if defined(CONFIG_UEC_ETH5)
+ uec_initialize(4);
+#endif
+#if defined(CONFIG_UEC_ETH6)
+ uec_initialize(5);
+#endif
+#if defined(CONFIG_TSEC_ENET)
+ tsec_standard_init(bis);
#endif
return 0;
}
-#endif
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 67c9e57..491c2e5 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -60,113 +60,117 @@ static void config_qe_ioports(void)
void cpu_init_f (volatile immap_t * im)
{
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
/* system performance tweaking */
-#ifdef CFG_ACR_PIPE_DEP
+#ifdef CONFIG_SYS_ACR_PIPE_DEP
/* Arbiter pipeline depth */
im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
- (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+ (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
#endif
-#ifdef CFG_ACR_RPTCNT
+#ifdef CONFIG_SYS_ACR_RPTCNT
/* Arbiter repeat count */
im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
- (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
+ (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
#endif
-#ifdef CFG_SPCR_OPT
+#ifdef CONFIG_SYS_SPCR_OPT
/* Optimize transactions between CSB and other devices */
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
- (CFG_SPCR_OPT << SPCR_OPT_SHIFT);
+ (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
#endif
-#ifdef CFG_SPCR_TSECEP
+#ifdef CONFIG_SYS_SPCR_TSECEP
/* all eTSEC's Emergency priority */
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
- (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
+ (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
#endif
-#ifdef CFG_SPCR_TSEC1EP
+#ifdef CONFIG_SYS_SPCR_TSEC1EP
/* TSEC1 Emergency priority */
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
- (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
+ (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
#endif
-#ifdef CFG_SPCR_TSEC2EP
+#ifdef CONFIG_SYS_SPCR_TSEC2EP
/* TSEC2 Emergency priority */
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
- (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
+ (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
#endif
-#ifdef CFG_SCCR_ENCCM
+#ifdef CONFIG_SYS_SCCR_ENCCM
/* Encryption clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
- (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
+ (CONFIG_SYS_SCCR_ENCCM << SCCR_PCICM_SHIFT);
#endif
-#ifdef CFG_SCCR_PCICM
+#ifdef CONFIG_SYS_SCCR_PCICM
/* PCI & DMA clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
- (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
+ (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT);
#endif
-#ifdef CFG_SCCR_TSECCM
+#ifdef CONFIG_SYS_SCCR_TSECCM
/* all TSEC's clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
- (CFG_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
+ (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
#endif
-#ifdef CFG_SCCR_TSEC1CM
+#ifdef CONFIG_SYS_SCCR_TSEC1CM
/* TSEC1 clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
- (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
+ (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
#endif
-#ifdef CFG_SCCR_TSEC2CM
+#ifdef CONFIG_SYS_SCCR_TSEC2CM
/* TSEC2 clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
- (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
+ (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
#endif
-#ifdef CFG_SCCR_TSEC1ON
+#ifdef CONFIG_SYS_SCCR_TSEC1ON
/* TSEC1 clock switch */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
- (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
+ (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
#endif
-#ifdef CFG_SCCR_TSEC2ON
+#ifdef CONFIG_SYS_SCCR_TSEC2ON
/* TSEC2 clock switch */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
- (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
+ (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
#endif
-#ifdef CFG_SCCR_USBMPHCM
+#ifdef CONFIG_SYS_SCCR_USBMPHCM
/* USB MPH clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
- (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
+ (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
#endif
-#ifdef CFG_SCCR_USBDRCM
+#ifdef CONFIG_SYS_SCCR_USBDRCM
/* USB DR clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
- (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
+ (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
#endif
-#ifdef CFG_SCCR_SATACM
+#ifdef CONFIG_SYS_SCCR_SATACM
/* SATA controller clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
- (CFG_SCCR_SATACM << SCCR_SATACM_SHIFT);
+ (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT);
#endif
/* RSR - Reset Status Register - clear all status (4.6.1.3) */
gd->reset_status = im->reset.rsr;
im->reset.rsr = ~(RSR_RES);
+ /* AER - Arbiter Event Register - store status */
+ gd->arbiter_event_attributes = im->arbiter.aeatr;
+ gd->arbiter_event_address = im->arbiter.aeadr;
+
/*
* RMR - Reset Mode Register
* contains checkstop reset enable (4.6.1.4)
@@ -174,30 +178,30 @@ void cpu_init_f (volatile immap_t * im)
im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
/* LCRR - Clock Ratio Register (10.3.1.16) */
- im->lbus.lcrr = CFG_LCRR;
+ im->lbus.lcrr = CONFIG_SYS_LCRR;
/* Enable Time Base & Decrimenter ( so we will have udelay() )*/
im->sysconf.spcr |= SPCR_TBEN;
/* System General Purpose Register */
-#ifdef CFG_SICRH
+#ifdef CONFIG_SYS_SICRH
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313)
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
- im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CFG_SICRH;
+ im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH;
#else
- im->sysconf.sicrh = CFG_SICRH;
+ im->sysconf.sicrh = CONFIG_SYS_SICRH;
#endif
#endif
-#ifdef CFG_SICRL
- im->sysconf.sicrl = CFG_SICRL;
+#ifdef CONFIG_SYS_SICRL
+ im->sysconf.sicrl = CONFIG_SYS_SICRL;
#endif
/* DDR control driver register */
-#ifdef CFG_DDRCDR
- im->sysconf.ddrcdr = CFG_DDRCDR;
+#ifdef CONFIG_SYS_DDRCDR
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
#endif
/* Output buffer impedance register */
-#ifdef CFG_OBIR
- im->sysconf.obir = CFG_OBIR;
+#ifdef CONFIG_SYS_OBIR
+ im->sysconf.obir = CONFIG_SYS_OBIR;
#endif
#ifdef CONFIG_QE
@@ -214,88 +218,88 @@ void cpu_init_f (volatile immap_t * im)
* has been determined
*/
-#if defined(CFG_BR0_PRELIM) \
- && defined(CFG_OR0_PRELIM) \
- && defined(CFG_LBLAWBAR0_PRELIM) \
- && defined(CFG_LBLAWAR0_PRELIM)
- im->lbus.bank[0].br = CFG_BR0_PRELIM;
- im->lbus.bank[0].or = CFG_OR0_PRELIM;
- im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
- im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
+#if defined(CONFIG_SYS_BR0_PRELIM) \
+ && defined(CONFIG_SYS_OR0_PRELIM) \
+ && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
+ && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
+ im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
+ im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
+ im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
+ im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
#else
-#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
+#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
#endif
-#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
- im->lbus.bank[1].br = CFG_BR1_PRELIM;
- im->lbus.bank[1].or = CFG_OR1_PRELIM;
+#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
+ im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
+ im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM)
- im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
- im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
+ im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
+ im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
#endif
-#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
- im->lbus.bank[2].br = CFG_BR2_PRELIM;
- im->lbus.bank[2].or = CFG_OR2_PRELIM;
+#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
+ im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
+ im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM)
- im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
- im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
+ im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
+ im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
#endif
-#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
- im->lbus.bank[3].br = CFG_BR3_PRELIM;
- im->lbus.bank[3].or = CFG_OR3_PRELIM;
+#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
+ im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
+ im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM)
- im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
- im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
+ im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
+ im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
#endif
-#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
- im->lbus.bank[4].br = CFG_BR4_PRELIM;
- im->lbus.bank[4].or = CFG_OR4_PRELIM;
+#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
+ im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
+ im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM)
- im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
- im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
+ im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
+ im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
#endif
-#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
- im->lbus.bank[5].br = CFG_BR5_PRELIM;
- im->lbus.bank[5].or = CFG_OR5_PRELIM;
+#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
+ im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
+ im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM)
- im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
- im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
+ im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
+ im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
#endif
-#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
- im->lbus.bank[6].br = CFG_BR6_PRELIM;
- im->lbus.bank[6].or = CFG_OR6_PRELIM;
+#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
+ im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
+ im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM)
- im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
- im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
+ im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
+ im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
#endif
-#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
- im->lbus.bank[7].br = CFG_BR7_PRELIM;
- im->lbus.bank[7].or = CFG_OR7_PRELIM;
+#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
+ im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
+ im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM)
- im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
- im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
+ im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
+ im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
#endif
-#ifdef CFG_GPIO1_PRELIM
- im->gpio[0].dir = CFG_GPIO1_DIR;
- im->gpio[0].dat = CFG_GPIO1_DAT;
+#ifdef CONFIG_SYS_GPIO1_PRELIM
+ im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
+ im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
#endif
-#ifdef CFG_GPIO2_PRELIM
- im->gpio[1].dir = CFG_GPIO2_DIR;
- im->gpio[1].dat = CFG_GPIO2_DAT;
+#ifdef CONFIG_SYS_GPIO2_PRELIM
+ im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
+ im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
}
int cpu_init_r (void)
{
#ifdef CONFIG_QE
- uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */
+ uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
qe_init(qe_base);
qe_reset();
#endif
@@ -303,6 +307,130 @@ int cpu_init_r (void)
}
/*
+ * Print out the bus arbiter event
+ */
+#if defined(CONFIG_DISPLAY_AER_FULL)
+static int print_83xx_arb_event(int force)
+{
+ static char* event[] = {
+ "Address Time Out",
+ "Data Time Out",
+ "Address Only Transfer Type",
+ "External Control Word Transfer Type",
+ "Reserved Transfer Type",
+ "Transfer Error",
+ "reserved",
+ "reserved"
+ };
+ static char* master[] = {
+ "e300 Core Data Transaction",
+ "reserved",
+ "e300 Core Instruction Fetch",
+ "reserved",
+ "TSEC1",
+ "TSEC2",
+ "USB MPH",
+ "USB DR",
+ "Encryption Core",
+ "I2C Boot Sequencer",
+ "JTAG",
+ "reserved",
+ "eSDHC",
+ "PCI1",
+ "PCI2",
+ "DMA",
+ "QUICC Engine 00",
+ "QUICC Engine 01",
+ "QUICC Engine 10",
+ "QUICC Engine 11",
+ "reserved",
+ "reserved",
+ "reserved",
+ "reserved",
+ "SATA1",
+ "SATA2",
+ "SATA3",
+ "SATA4",
+ "reserved",
+ "PCI Express 1",
+ "PCI Express 2",
+ "TDM-DMAC"
+ };
+ static char *transfer[] = {
+ "Address-only, Clean Block",
+ "Address-only, lwarx reservation set",
+ "Single-beat or Burst write",
+ "reserved",
+ "Address-only, Flush Block",
+ "reserved",
+ "Burst write",
+ "reserved",
+ "Address-only, sync",
+ "Address-only, tlbsync",
+ "Single-beat or Burst read",
+ "Single-beat or Burst read",
+ "Address-only, Kill Block",
+ "Address-only, icbi",
+ "Burst read",
+ "reserved",
+ "Address-only, eieio",
+ "reserved",
+ "Single-beat write",
+ "reserved",
+ "ecowx - Illegal single-beat write",
+ "reserved",
+ "reserved",
+ "reserved",
+ "Address-only, TLB Invalidate",
+ "reserved",
+ "Single-beat or Burst read",
+ "reserved",
+ "eciwx - Illegal single-beat read",
+ "reserved",
+ "Burst read",
+ "reserved"
+ };
+
+ int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
+ >> AEATR_EVENT_SHIFT;
+ int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
+ >> AEATR_MSTR_ID_SHIFT;
+ int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
+ >> AEATR_TBST_SHIFT;
+ int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
+ >> AEATR_TSIZE_SHIFT;
+ int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
+ >> AEATR_TTYPE_SHIFT;
+
+ if (!force && !gd->arbiter_event_address)
+ return 0;
+
+ puts("Arbiter Event Status:\n");
+ printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address);
+ printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
+ printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
+ printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
+ tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
+ printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
+
+ return gd->arbiter_event_address;
+}
+
+#elif defined(CONFIG_DISPLAY_AER_BRIEF)
+
+static int print_83xx_arb_event(int force)
+{
+ if (!force && !gd->arbiter_event_address)
+ return 0;
+
+ printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
+ gd->arbiter_event_attributes, gd->arbiter_event_address);
+
+ return gd->arbiter_event_address;
+}
+#endif /* CONFIG_DISPLAY_AER_xxxx */
+
+/*
* Figure out the cause of the reset
*/
int prt_83xx_rsr(void)
@@ -334,6 +462,12 @@ int prt_83xx_rsr(void)
printf("%s%s", sep, bits[i].desc);
sep = ", ";
}
- puts("\n\n");
+ puts("\n");
+
+#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
+ print_83xx_arb_event(rsr & RSR_BMRS);
+#endif
+ puts("\n");
+
return 0;
}
diff --git a/cpu/mpc83xx/ecc.c b/cpu/mpc83xx/ecc.c
index 5137ab6..5ab169f 100644
--- a/cpu/mpc83xx/ecc.c
+++ b/cpu/mpc83xx/ecc.c
@@ -20,7 +20,7 @@
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
void ecc_print_status(void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
printf("\nECC mode: %s\n\n",
@@ -100,7 +100,7 @@ void ecc_print_status(void)
int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
volatile u32 val;
u64 *addr;
diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c
index 39bd9dc..f890775 100644
--- a/cpu/mpc83xx/fdt.c
+++ b/cpu/mpc83xx/fdt.c
@@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
void ft_cpu_setup(void *blob, bd_t *bd)
{
- immap_t *immr = (immap_t *)CFG_IMMR;
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
int spridr = immr->sysconf.spridr;
/*
@@ -52,7 +52,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_crypto_node(blob, 0x0204);
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
- defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
+ defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
fdt_fixup_ethernet(blob);
#endif
@@ -76,9 +77,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_qe_setup(blob);
#endif
-#ifdef CFG_NS16550
+#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "ns16550",
- "clock-frequency", CFG_NS16550_CLK, 1);
+ "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c
index 98ed21c..faffbaf 100644
--- a/cpu/mpc83xx/interrupts.c
+++ b/cpu/mpc83xx/interrupts.c
@@ -38,9 +38,9 @@ struct irq_action {
int interrupt_init_cpu (unsigned *decrementer_count)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- *decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
+ *decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ;
/* Enable e300 time base */
diff --git a/cpu/mpc83xx/nand_init.c b/cpu/mpc83xx/nand_init.c
index e92f230..38e141a 100644
--- a/cpu/mpc83xx/nand_init.c
+++ b/cpu/mpc83xx/nand_init.c
@@ -37,7 +37,7 @@ void cpu_init_f (volatile immap_t * im)
int i;
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
for (i = 0; i < sizeof(gd_t); i++)
@@ -45,34 +45,34 @@ void cpu_init_f (volatile immap_t * im)
/* system performance tweaking */
-#ifdef CFG_ACR_PIPE_DEP
+#ifdef CONFIG_SYS_ACR_PIPE_DEP
/* Arbiter pipeline depth */
im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
- (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+ (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
#endif
-#ifdef CFG_ACR_RPTCNT
+#ifdef CONFIG_SYS_ACR_RPTCNT
/* Arbiter repeat count */
im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
- (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
+ (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
#endif
-#ifdef CFG_SPCR_OPT
+#ifdef CONFIG_SYS_SPCR_OPT
/* Optimize transactions between CSB and other devices */
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
- (CFG_SPCR_OPT << SPCR_OPT_SHIFT);
+ (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
#endif
/* Enable Time Base & Decrimenter (so we will have udelay()) */
im->sysconf.spcr |= SPCR_TBEN;
/* DDR control driver register */
-#ifdef CFG_DDRCDR
- im->sysconf.ddrcdr = CFG_DDRCDR;
+#ifdef CONFIG_SYS_DDRCDR
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
#endif
/* Output buffer impedance register */
-#ifdef CFG_OBIR
- im->sysconf.obir = CFG_OBIR;
+#ifdef CONFIG_SYS_OBIR
+ im->sysconf.obir = CONFIG_SYS_OBIR;
#endif
/*
@@ -84,16 +84,16 @@ void cpu_init_f (volatile immap_t * im)
* has been determined
*/
-#if defined(CFG_NAND_BR_PRELIM) \
- && defined(CFG_NAND_OR_PRELIM) \
- && defined(CFG_NAND_LBLAWBAR_PRELIM) \
- && defined(CFG_NAND_LBLAWAR_PRELIM)
- im->lbus.bank[0].br = CFG_NAND_BR_PRELIM;
- im->lbus.bank[0].or = CFG_NAND_OR_PRELIM;
- im->sysconf.lblaw[0].bar = CFG_NAND_LBLAWBAR_PRELIM;
- im->sysconf.lblaw[0].ar = CFG_NAND_LBLAWAR_PRELIM;
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) \
+ && defined(CONFIG_SYS_NAND_OR_PRELIM) \
+ && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
+ && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
+ im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM;
+ im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM;
+ im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
+ im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
#else
-#error CFG_NAND_BR_PRELIM, CFG_NAND_OR_PRELIM, CFG_NAND_LBLAWBAR_PRELIM & CFG_NAND_LBLAWAR_PRELIM must be defined
+#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
#endif
}
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
index c3ec5f8..ab0760b 100644
--- a/cpu/mpc83xx/pci.c
+++ b/cpu/mpc83xx/pci.c
@@ -42,7 +42,7 @@ static int pci_num_buses;
static void pci_init_bus(int bus, struct pci_region *reg)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile pot83xx_t *pot = immr->ios.pot;
volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
struct pci_controller *hose = &pci_hose[bus];
@@ -83,7 +83,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
pci_ctrl->pibar1 = 0;
pci_ctrl->piebar1 = 0;
pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+ PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
i = hose->region_count++;
hose->regions[i].bus_start = 0;
@@ -94,8 +94,8 @@ static void pci_init_bus(int bus, struct pci_region *reg)
hose->first_busno = 0;
hose->last_busno = 0xff;
- pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80,
- CFG_IMMR + 0x8304 + bus * 0x80);
+ pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
+ CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
pci_register_hose(hose);
@@ -133,7 +133,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
*/
void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
int i;
if (num_buses > MAX_BUSES) {
diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c
index ce91a07..db94f00 100644
--- a/cpu/mpc83xx/qe_io.c
+++ b/cpu/mpc83xx/qe_io.c
@@ -33,7 +33,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
u32 pin_2bit_assign;
u32 pin_1bit_mask;
u32 tmp_val;
- volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
/* Caculate pin location and 2bit mask and dir */
diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c
index 020c4c8..3936796 100644
--- a/cpu/mpc83xx/serdes.c
+++ b/cpu/mpc83xx/serdes.c
@@ -42,9 +42,9 @@
#define FSL_SRDSRSTCTL_RST 0x80000000
#define FSL_SRDSRSTCTL_SATA_RESET 0xf
-void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd)
+void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
{
- void *regs = (void *)CFG_IMMR + offset;
+ void *regs = (void *)CONFIG_SYS_IMMR + offset;
u32 tmp;
/* 1.0V corevdd */
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 76f2474..42a4e67 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
void board_add_ram_info(int use_default)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
char buf[32];
@@ -57,9 +57,9 @@ void board_add_ram_info(int use_default)
printf(", %s MHz)", strmhz(buf, gd->mem_clk));
-#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
+#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
puts("\nSDRAM: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
+ print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
#endif
}
@@ -71,8 +71,8 @@ extern uint dma_check(void);
extern int dma_xfer(void *dest, uint count, void *src);
#endif
-#ifndef CFG_READ_SPD
-#define CFG_READ_SPD i2c_read
+#ifndef CONFIG_SYS_READ_SPD
+#define CONFIG_SYS_READ_SPD i2c_read
#endif
/*
@@ -129,7 +129,7 @@ static void spd_debug(spd_eeprom_t *spd)
long int spd_sdram()
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
spd_eeprom_t spd;
@@ -158,7 +158,7 @@ long int spd_sdram()
unsigned int pvr = get_pvr();
/* Read SPD parameters with I2C */
- CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
+ CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
#ifdef SPD_DEBUG
spd_debug(&spd);
#endif
@@ -194,12 +194,12 @@ long int spd_sdram()
return 0;
}
-#ifdef CFG_DDRCDR_VALUE
+#ifdef CONFIG_SYS_DDRCDR_VALUE
/*
* Adjust DDR II IO voltage biasing. It just makes it work.
*/
if(spd.mem_type == SPD_MEMTYPE_DDR2) {
- immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+ immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
}
udelay(50000);
#endif
@@ -214,7 +214,7 @@ long int spd_sdram()
}
/* Setup DDR chip select register */
-#ifdef CFG_83XX_DDR_USES_CS0
+#ifdef CONFIG_SYS_83XX_DDR_USES_CS0
ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
ddr->cs_config[0] = ( 1 << 31
| (odt_rd_cfg << 20)
@@ -274,7 +274,7 @@ long int spd_sdram()
/*
* Set up LAWBAR for all of DDR.
*/
- ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+ ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
debug("DDR:bar=0x%08x\n", ecm->bar);
debug("DDR:ar=0x%08x\n", ecm->ar);
@@ -314,7 +314,7 @@ long int spd_sdram()
+ (spd.clk_cycle & 0x0f));
max_data_rate = max_bus_clk * 2;
- debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
+ debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
ddrc_clk = gd->mem_clk / 1000000;
effective_data_rate = 0;
@@ -401,7 +401,7 @@ long int spd_sdram()
}
}
- debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate);
+ debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
/*
@@ -724,8 +724,8 @@ long int spd_sdram()
debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
}
-#ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
- ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
#endif
debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
@@ -842,7 +842,7 @@ static __inline__ unsigned long get_tbms (void)
/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
void ddr_enable_ecc(unsigned int dram_size)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ddr83xx_t *ddr= &immap->ddr;
unsigned long t_start, t_end;
register u64 *p;
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 76c569d..bf9bf36 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -90,7 +90,7 @@ corecnf_t corecnf_tab[] = {
*/
int get_clocks(void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 pci_sync_in;
u8 spmf;
u8 clkin_div;
@@ -499,44 +499,46 @@ ulong get_bus_freq(ulong dummy)
int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
+ char buf[32];
+
printf("Clock configuration:\n");
- printf(" Core: %4d MHz\n", gd->core_clk / 1000000);
- printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
+ printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk));
+ printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
- printf(" QE: %4d MHz\n", gd->qe_clk / 1000000);
- printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000);
+ printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk));
+ printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk));
#endif
- printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
- printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
- printf(" DDR: %4ld MHz\n", gd->mem_clk / 1000000);
+ printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
+ printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk));
+ printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
#if defined(CONFIG_MPC8360)
- printf(" DDR Secondary: %4d MHz\n", gd->mem_sec_clk / 1000000);
+ printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
#endif
- printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
- printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
+ printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk));
+ printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
#if !defined(CONFIG_MPC832X)
- printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
+ printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
#endif
#if defined(CONFIG_MPC8315)
- printf(" TDM: %4d MHz\n", gd->tdm_clk / 1000000);
+ printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk));
#endif
#if defined(CONFIG_MPC837X)
- printf(" SDHC: %4d MHz\n", gd->sdhc_clk / 1000000);
+ printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
#endif
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
- printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
- printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
- printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000);
+ printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
+ printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
+ printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
#endif
#if defined(CONFIG_MPC834X)
- printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000);
+ printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
#endif
#if defined(CONFIG_MPC837X)
- printf(" PCIEXP1: %4d MHz\n", gd->pciexp1_clk / 1000000);
- printf(" PCIEXP2: %4d MHz\n", gd->pciexp2_clk / 1000000);
+ printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
+ printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
- printf(" SATA: %4d MHz\n", gd->sata_clk / 1000000);
+ printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk));
#endif
return 0;
}
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index 16ed494..792b2c8 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -29,6 +29,7 @@
#include <config.h>
#include <mpc83xx.h>
+#include <timestamp.h>
#include <version.h>
#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
@@ -57,8 +58,8 @@
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
#endif
-#if !defined(CONFIG_NAND_SPL) && !defined(CFG_RAMBOOT)
-#define CFG_FLASHBOOT
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_SYS_FLASHBOOT
#endif
/*
@@ -93,8 +94,8 @@
.fill 8,1,(((w)>> 8)&0xff); \
.fill 8,1,(((w) )&0xff)
- _HRCW_TABLE_ENTRY(CFG_HRCW_LOW)
- _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
+ _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
+ _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
/*
* Magic number and version string - put it after the HRCW since it
@@ -105,16 +106,16 @@
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii " ", CONFIG_IDENT_STRING, "\0"
#ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined
-#endif /* CFG_DEFAULT_IMMR */
-#ifndef CFG_IMMR
-#define CFG_IMMR CONFIG_DEFAULT_IMMR
-#endif /* CFG_IMMR */
+#endif /* CONFIG_SYS_DEFAULT_IMMR */
+#ifndef CONFIG_SYS_IMMR
+#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
+#endif /* CONFIG_SYS_IMMR */
/*
* After configuration, a system reset exception is executed using the
@@ -160,24 +161,36 @@ boot_cold: /* time t 3 */
nop
boot_warm: /* time t 5 */
mfmsr r5 /* save msr contents */
- lis r3, CFG_IMMR@h
- ori r3, r3, CFG_IMMR@l
+ lis r3, CONFIG_SYS_IMMR@h
+ ori r3, r3, CONFIG_SYS_IMMR@l
stw r3, IMMRBAR(r4)
/* Initialise the E300 processor core */
/*------------------------------------------*/
+#ifdef CONFIG_NAND_SPL
+ /* The FCM begins execution after only the first page
+ * is loaded. Wait for the rest before branching
+ * to another flash page.
+ */
+ addi r7, r3, 0x50b0
+1: dcbi 0, r7
+ lwz r6, 0(r7)
+ andi. r6, r6, 1
+ beq 1b
+#endif
+
bl init_e300_core
-#ifdef CFG_FLASHBOOT
+#ifdef CONFIG_SYS_FLASHBOOT
/* Inflate flash location so it appears everywhere, calculate */
/* the absolute address in final location of the FLASH, jump */
/* there and deflate the flash size back to minimal size */
/*------------------------------------------------------------*/
bl map_flash_by_law1
- lis r4, (CFG_MONITOR_BASE)@h
- ori r4, r4, (CFG_MONITOR_BASE)@l
+ lis r4, (CONFIG_SYS_MONITOR_BASE)@h
+ ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r5
blr
@@ -185,7 +198,7 @@ in_flash:
#if 1 /* Remapping flash with LAW0. */
bl remap_flash_by_law0
#endif
-#endif /* CFG_FLASHBOOT */
+#endif /* CONFIG_SYS_FLASHBOOT */
/* setup the bats */
bl setup_bats
@@ -208,18 +221,18 @@ in_flash:
bl enable_addr_trans
sync
- /* enable and invalidate the data cache */
+ /* enable the data cache */
bl dcache_enable
sync
-#ifdef CFG_INIT_RAM_LOCK
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
bl lock_ram_in_cache
sync
#endif
/* set up the stack pointer in our newly created
* cache-ram (r1) */
- lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
- ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+ lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
+ ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
@@ -234,7 +247,7 @@ in_flash:
GET_GOT /* initialize GOT access */
/* r3: IMMR */
- lis r3, CFG_IMMR@h
+ lis r3, CONFIG_SYS_IMMR@h
/* run low-level CPU init code (in Flash)*/
bl cpu_init_f
@@ -456,11 +469,11 @@ init_e300_core: /* time t 10 */
mtspr SRR1, r3 /* Make SRR1 match MSR */
- lis r3, CFG_IMMR@h
+ lis r3, CONFIG_SYS_IMMR@h
#if defined(CONFIG_WATCHDOG)
/* Initialise the Wathcdog values and reset it (if req) */
/*------------------------------------------------------*/
- lis r4, CFG_WATCHDOG_VALUE
+ lis r4, CONFIG_SYS_WATCHDOG_VALUE
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
stw r4, SWCRR(r3)
@@ -483,22 +496,34 @@ init_e300_core: /* time t 10 */
1:
#endif /* CONFIG_WATCHDOG */
+#if defined(CONFIG_MASK_AER_AO)
+ /* Write the Arbiter Event Enable to mask Address Only traps. */
+ /* This prevents the dcbz instruction from being trapped when */
+ /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
+ /* COHERENCY bit is set in the WIMG bits, which is often */
+ /* needed for PCI operation. */
+ lwz r4, 0x0808(r3)
+ rlwinm r0, r4, 0, ~AER_AO
+ stw r0, 0x0808(r3)
+#endif /* CONFIG_MASK_AER_AO */
+
/* Initialize the Hardware Implementation-dependent Registers */
/* HID0 also contains cache control */
+ /* - force invalidation of data and instruction caches */
/*------------------------------------------------------*/
- lis r3, CFG_HID0_INIT@h
- ori r3, r3, CFG_HID0_INIT@l
+ lis r3, CONFIG_SYS_HID0_INIT@h
+ ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
SYNC
mtspr HID0, r3
- lis r3, CFG_HID0_FINAL@h
- ori r3, r3, CFG_HID0_FINAL@l
+ lis r3, CONFIG_SYS_HID0_FINAL@h
+ ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
SYNC
mtspr HID0, r3
- lis r3, CFG_HID2@h
- ori r3, r3, CFG_HID2@l
+ lis r3, CONFIG_SYS_HID2@h
+ ori r3, r3, CONFIG_SYS_HID2@l
SYNC
mtspr HID2, r3
@@ -512,131 +537,131 @@ setup_bats:
addis r0, r0, 0x0000
/* IBAT 0 */
- addis r4, r0, CFG_IBAT0L@h
- ori r4, r4, CFG_IBAT0L@l
- addis r3, r0, CFG_IBAT0U@h
- ori r3, r3, CFG_IBAT0U@l
+ addis r4, r0, CONFIG_SYS_IBAT0L@h
+ ori r4, r4, CONFIG_SYS_IBAT0L@l
+ addis r3, r0, CONFIG_SYS_IBAT0U@h
+ ori r3, r3, CONFIG_SYS_IBAT0U@l
mtspr IBAT0L, r4
mtspr IBAT0U, r3
/* DBAT 0 */
- addis r4, r0, CFG_DBAT0L@h
- ori r4, r4, CFG_DBAT0L@l
- addis r3, r0, CFG_DBAT0U@h
- ori r3, r3, CFG_DBAT0U@l
+ addis r4, r0, CONFIG_SYS_DBAT0L@h
+ ori r4, r4, CONFIG_SYS_DBAT0L@l
+ addis r3, r0, CONFIG_SYS_DBAT0U@h
+ ori r3, r3, CONFIG_SYS_DBAT0U@l
mtspr DBAT0L, r4
mtspr DBAT0U, r3
/* IBAT 1 */
- addis r4, r0, CFG_IBAT1L@h
- ori r4, r4, CFG_IBAT1L@l
- addis r3, r0, CFG_IBAT1U@h
- ori r3, r3, CFG_IBAT1U@l
+ addis r4, r0, CONFIG_SYS_IBAT1L@h
+ ori r4, r4, CONFIG_SYS_IBAT1L@l
+ addis r3, r0, CONFIG_SYS_IBAT1U@h
+ ori r3, r3, CONFIG_SYS_IBAT1U@l
mtspr IBAT1L, r4
mtspr IBAT1U, r3
/* DBAT 1 */
- addis r4, r0, CFG_DBAT1L@h
- ori r4, r4, CFG_DBAT1L@l
- addis r3, r0, CFG_DBAT1U@h
- ori r3, r3, CFG_DBAT1U@l
+ addis r4, r0, CONFIG_SYS_DBAT1L@h
+ ori r4, r4, CONFIG_SYS_DBAT1L@l
+ addis r3, r0, CONFIG_SYS_DBAT1U@h
+ ori r3, r3, CONFIG_SYS_DBAT1U@l
mtspr DBAT1L, r4
mtspr DBAT1U, r3
/* IBAT 2 */
- addis r4, r0, CFG_IBAT2L@h
- ori r4, r4, CFG_IBAT2L@l
- addis r3, r0, CFG_IBAT2U@h
- ori r3, r3, CFG_IBAT2U@l
+ addis r4, r0, CONFIG_SYS_IBAT2L@h
+ ori r4, r4, CONFIG_SYS_IBAT2L@l
+ addis r3, r0, CONFIG_SYS_IBAT2U@h
+ ori r3, r3, CONFIG_SYS_IBAT2U@l
mtspr IBAT2L, r4
mtspr IBAT2U, r3
/* DBAT 2 */
- addis r4, r0, CFG_DBAT2L@h
- ori r4, r4, CFG_DBAT2L@l
- addis r3, r0, CFG_DBAT2U@h
- ori r3, r3, CFG_DBAT2U@l
+ addis r4, r0, CONFIG_SYS_DBAT2L@h
+ ori r4, r4, CONFIG_SYS_DBAT2L@l
+ addis r3, r0, CONFIG_SYS_DBAT2U@h
+ ori r3, r3, CONFIG_SYS_DBAT2U@l
mtspr DBAT2L, r4
mtspr DBAT2U, r3
/* IBAT 3 */
- addis r4, r0, CFG_IBAT3L@h
- ori r4, r4, CFG_IBAT3L@l
- addis r3, r0, CFG_IBAT3U@h
- ori r3, r3, CFG_IBAT3U@l
+ addis r4, r0, CONFIG_SYS_IBAT3L@h
+ ori r4, r4, CONFIG_SYS_IBAT3L@l
+ addis r3, r0, CONFIG_SYS_IBAT3U@h
+ ori r3, r3, CONFIG_SYS_IBAT3U@l
mtspr IBAT3L, r4
mtspr IBAT3U, r3
/* DBAT 3 */
- addis r4, r0, CFG_DBAT3L@h
- ori r4, r4, CFG_DBAT3L@l
- addis r3, r0, CFG_DBAT3U@h
- ori r3, r3, CFG_DBAT3U@l
+ addis r4, r0, CONFIG_SYS_DBAT3L@h
+ ori r4, r4, CONFIG_SYS_DBAT3L@l
+ addis r3, r0, CONFIG_SYS_DBAT3U@h
+ ori r3, r3, CONFIG_SYS_DBAT3U@l
mtspr DBAT3L, r4
mtspr DBAT3U, r3
#ifdef CONFIG_HIGH_BATS
/* IBAT 4 */
- addis r4, r0, CFG_IBAT4L@h
- ori r4, r4, CFG_IBAT4L@l
- addis r3, r0, CFG_IBAT4U@h
- ori r3, r3, CFG_IBAT4U@l
+ addis r4, r0, CONFIG_SYS_IBAT4L@h
+ ori r4, r4, CONFIG_SYS_IBAT4L@l
+ addis r3, r0, CONFIG_SYS_IBAT4U@h
+ ori r3, r3, CONFIG_SYS_IBAT4U@l
mtspr IBAT4L, r4
mtspr IBAT4U, r3
/* DBAT 4 */
- addis r4, r0, CFG_DBAT4L@h
- ori r4, r4, CFG_DBAT4L@l
- addis r3, r0, CFG_DBAT4U@h
- ori r3, r3, CFG_DBAT4U@l
+ addis r4, r0, CONFIG_SYS_DBAT4L@h
+ ori r4, r4, CONFIG_SYS_DBAT4L@l
+ addis r3, r0, CONFIG_SYS_DBAT4U@h
+ ori r3, r3, CONFIG_SYS_DBAT4U@l
mtspr DBAT4L, r4
mtspr DBAT4U, r3
/* IBAT 5 */
- addis r4, r0, CFG_IBAT5L@h
- ori r4, r4, CFG_IBAT5L@l
- addis r3, r0, CFG_IBAT5U@h
- ori r3, r3, CFG_IBAT5U@l
+ addis r4, r0, CONFIG_SYS_IBAT5L@h
+ ori r4, r4, CONFIG_SYS_IBAT5L@l
+ addis r3, r0, CONFIG_SYS_IBAT5U@h
+ ori r3, r3, CONFIG_SYS_IBAT5U@l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
/* DBAT 5 */
- addis r4, r0, CFG_DBAT5L@h
- ori r4, r4, CFG_DBAT5L@l
- addis r3, r0, CFG_DBAT5U@h
- ori r3, r3, CFG_DBAT5U@l
+ addis r4, r0, CONFIG_SYS_DBAT5L@h
+ ori r4, r4, CONFIG_SYS_DBAT5L@l
+ addis r3, r0, CONFIG_SYS_DBAT5U@h
+ ori r3, r3, CONFIG_SYS_DBAT5U@l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
/* IBAT 6 */
- addis r4, r0, CFG_IBAT6L@h
- ori r4, r4, CFG_IBAT6L@l
- addis r3, r0, CFG_IBAT6U@h
- ori r3, r3, CFG_IBAT6U@l
+ addis r4, r0, CONFIG_SYS_IBAT6L@h
+ ori r4, r4, CONFIG_SYS_IBAT6L@l
+ addis r3, r0, CONFIG_SYS_IBAT6U@h
+ ori r3, r3, CONFIG_SYS_IBAT6U@l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
/* DBAT 6 */
- addis r4, r0, CFG_DBAT6L@h
- ori r4, r4, CFG_DBAT6L@l
- addis r3, r0, CFG_DBAT6U@h
- ori r3, r3, CFG_DBAT6U@l
+ addis r4, r0, CONFIG_SYS_DBAT6L@h
+ ori r4, r4, CONFIG_SYS_DBAT6L@l
+ addis r3, r0, CONFIG_SYS_DBAT6U@h
+ ori r3, r3, CONFIG_SYS_DBAT6U@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
/* IBAT 7 */
- addis r4, r0, CFG_IBAT7L@h
- ori r4, r4, CFG_IBAT7L@l
- addis r3, r0, CFG_IBAT7U@h
- ori r3, r3, CFG_IBAT7U@l
+ addis r4, r0, CONFIG_SYS_IBAT7L@h
+ ori r4, r4, CONFIG_SYS_IBAT7L@l
+ addis r3, r0, CONFIG_SYS_IBAT7U@h
+ ori r3, r3, CONFIG_SYS_IBAT7U@l
mtspr IBAT7L, r4
mtspr IBAT7U, r3
/* DBAT 7 */
- addis r4, r0, CFG_DBAT7L@h
- ori r4, r4, CFG_DBAT7L@l
- addis r3, r0, CFG_DBAT7U@h
- ori r3, r3, CFG_DBAT7U@l
+ addis r4, r0, CONFIG_SYS_DBAT7L@h
+ ori r4, r4, CONFIG_SYS_DBAT7L@l
+ addis r3, r0, CONFIG_SYS_DBAT7U@h
+ ori r3, r3, CONFIG_SYS_DBAT7U@l
mtspr DBAT7L, r4
mtspr DBAT7U, r3
#endif
@@ -703,8 +728,7 @@ disable_addr_trans:
icache_enable:
mfspr r3, HID0
ori r3, r3, HID0_ICE
- lis r4, 0
- ori r4, r4, HID0_ILOCK
+ li r4, HID0_ICFI|HID0_ILOCK
andc r3, r3, r4
ori r4, r3, HID0_ICFI
isync
@@ -717,13 +741,10 @@ icache_enable:
icache_disable:
mfspr r3, HID0
lis r4, 0
- ori r4, r4, HID0_ICE|HID0_ILOCK
+ ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
andc r3, r3, r4
- ori r4, r3, HID0_ICFI
isync
- mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
- isync
- mtspr HID0, r3 /* clears invalidate */
+ mtspr HID0, r3 /* clears invalidate, enable and lock */
blr
.globl icache_status
@@ -737,25 +758,24 @@ dcache_enable:
mfspr r3, HID0
li r5, HID0_DCFI|HID0_DLOCK
andc r3, r3, r5
- mtspr HID0, r3 /* no invalidate, unlock */
ori r3, r3, HID0_DCE
- ori r5, r3, HID0_DCFI
- mtspr HID0, r5 /* enable + invalidate */
- mtspr HID0, r3 /* enable */
sync
+ mtspr HID0, r3 /* enable, no invalidate */
blr
.globl dcache_disable
dcache_disable:
+ mflr r4
+ bl flush_dcache /* uses r3 and r5 */
mfspr r3, HID0
- lis r4, 0
- ori r4, r4, HID0_DCE|HID0_DLOCK
- andc r3, r3, r4
- ori r4, r3, HID0_DCI
+ li r5, HID0_DCE|HID0_DLOCK
+ andc r3, r3, r5
+ ori r5, r3, HID0_DCFI
sync
- mtspr HID0, r4 /* sets invalidate, clears enable and lock */
+ mtspr HID0, r5 /* sets invalidate, clears enable and lock */
sync
mtspr HID0, r3 /* clears invalidate */
+ mtlr r4
blr
.globl dcache_status
@@ -764,6 +784,18 @@ dcache_status:
rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
blr
+ .globl flush_dcache
+flush_dcache:
+ lis r3, 0
+ lis r5, CONFIG_SYS_CACHELINE_SIZE
+1: cmp 0, 1, r3, r5
+ bge 2f
+ lwz r5, 0(r3)
+ lis r5, CONFIG_SYS_CACHELINE_SIZE
+ addi r3, r3, 0x4
+ b 1b
+2: blr
+
.globl get_pvr
get_pvr:
mfspr r3, PVR
@@ -801,16 +833,16 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__bss_start)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE)
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
* + Destination Address
*
* Offset:
@@ -1054,15 +1086,15 @@ trap_reloc:
blr
#endif /* !CONFIG_NAND_SPL */
-#ifdef CFG_INIT_RAM_LOCK
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
lock_ram_in_cache:
/* Allocate Initial RAM in data cache.
*/
- lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
- li r2, ((CFG_INIT_RAM_END & ~31) + \
- (CFG_INIT_RAM_ADDR & 31) + 31) / 32
- mtctr r2
+ lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+ li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r4
1:
dcbz r0, r3
addi r3, r3, 32
@@ -1070,7 +1102,7 @@ lock_ram_in_cache:
/* Lock the data cache */
mfspr r0, HID0
- ori r0, r0, 0x1000
+ ori r0, r0, HID0_DLOCK
sync
mtspr HID0, r0
sync
@@ -1080,10 +1112,11 @@ lock_ram_in_cache:
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
- lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
- li r2,512
- mtctr r2
+ lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+ li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r4
1: icbi r0, r3
dcbi r0, r3
addi r3, r3, 32
@@ -1096,19 +1129,20 @@ unlock_ram_in_cache:
li r5, HID0_DLOCK|HID0_DCFI
andc r3, r3, r5 /* no invalidate, unlock */
ori r5, r3, HID0_DCFI /* invalidate, unlock */
+ sync
mtspr HID0, r5 /* invalidate, unlock */
- mtspr HID0, r3 /* no invalidate, unlock */
sync
+ mtspr HID0, r3 /* no invalidate, unlock */
blr
#endif /* !CONFIG_NAND_SPL */
-#endif /* CFG_INIT_RAM_LOCK */
+#endif /* CONFIG_SYS_INIT_RAM_LOCK */
-#ifdef CFG_FLASHBOOT
+#ifdef CONFIG_SYS_FLASHBOOT
map_flash_by_law1:
/* When booting from ROM (Flash or EPROM), clear the */
/* Address Mask in OR0 so ROM appears everywhere */
/*----------------------------------------------------*/
- lis r3, (CFG_IMMR)@h /* r3 <= CFG_IMMR */
+ lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
lwz r4, OR0@l(r3)
li r5, 0x7fff /* r5 <= 0x00007FFFF */
and r4, r4, r5
@@ -1130,14 +1164,14 @@ map_flash_by_law1:
* LBIU Local Access Widow 0 will not cover this memory space. So, we
* need another window to map in it.
*/
- lis r4, (CFG_FLASH_BASE)@h
- ori r4, r4, (CFG_FLASH_BASE)@l
- stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */
+ lis r4, (CONFIG_SYS_FLASH_BASE)@h
+ ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
+ stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
- /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR1 */
+ /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
lis r4, (0x80000012)@h
ori r4, r4, (0x80000012)@l
- li r5, CFG_FLASH_SIZE
+ li r5, CONFIG_SYS_FLASH_SIZE
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
addi r4, r4, 1
bne 1b
@@ -1154,24 +1188,24 @@ remap_flash_by_law0:
lwz r4, BR0(r3)
li r5, 0x7FFF
and r4, r4, r5
- lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h
- ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l
+ lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
+ ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
or r5, r5, r4
- stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
+ stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
lwz r4, OR0(r3)
- lis r5, ~((CFG_FLASH_SIZE << 4) - 1)
+ lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
or r4, r4, r5
stw r4, OR0(r3)
- lis r4, (CFG_FLASH_BASE)@h
- ori r4, r4, (CFG_FLASH_BASE)@l
- stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */
+ lis r4, (CONFIG_SYS_FLASH_BASE)@h
+ ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
+ stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
- /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR0 */
+ /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
lis r4, (0x80000012)@h
ori r4, r4, (0x80000012)@l
- li r5, CFG_FLASH_SIZE
+ li r5, CONFIG_SYS_FLASH_SIZE
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
addi r4, r4, 1
bne 1b
@@ -1182,4 +1216,4 @@ remap_flash_by_law0:
stw r4, LBLAWBAR1(r3)
stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
blr
-#endif /* CFG_FLASHBOOT */
+#endif /* CONFIG_SYS_FLASHBOOT */
diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c
index dfd6c03..3b09a62 100644
--- a/cpu/mpc83xx/traps.c
+++ b/cpu/mpc83xx/traps.c
@@ -100,7 +100,7 @@ _exception(int signr, struct pt_regs *regs)
void dump_pci (void)
{
/*
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
printf ("PCI: err status %x err mask %x err ctrl %x\n",
le32_to_cpu (immap->im_pci.pci_esr),
le32_to_cpu (immap->im_pci.pci_emr),
@@ -124,7 +124,7 @@ MachineCheckException(struct pt_regs *regs)
*/
#ifdef CONFIG_PCI
#if 0
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
#ifdef DEBUG
dump_pci();
#endif
diff --git a/cpu/mpc83xx/u-boot.lds b/cpu/mpc83xx/u-boot.lds
index 99ad675..3a08f64 100644
--- a/cpu/mpc83xx/u-boot.lds
+++ b/cpu/mpc83xx/u-boot.lds
@@ -116,6 +116,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c
index b0ecd25..fff8dff 100644
--- a/cpu/mpc85xx/commproc.c
+++ b/cpu/mpc85xx/commproc.c
@@ -37,10 +37,10 @@ DECLARE_GLOBAL_DATA_PTR;
void
m8560_cpm_reset(void)
{
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
volatile ulong count;
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Reclaim the DP memory for our use.
*/
@@ -64,7 +64,7 @@ m8560_cpm_reset(void)
uint
m8560_cpm_dpalloc(uint size, uint align)
{
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
uint retloc;
uint align_mask, off;
uint savebase;
@@ -120,7 +120,7 @@ m8560_cpm_hostalloc(uint size, uint align)
void
m8560_cpm_setbrg(uint brg, uint rate)
{
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
@@ -142,7 +142,7 @@ m8560_cpm_setbrg(uint brg, uint rate)
void
m8560_cpm_fastbrg(uint brg, uint rate, int div16)
{
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
@@ -167,7 +167,7 @@ m8560_cpm_fastbrg(uint brg, uint rate, int div16)
void
m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
{
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
volatile uint *bp;
if (brg < 4) {
@@ -190,7 +190,7 @@ m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
void post_word_store (ulong a)
{
volatile ulong *save_addr =
- (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
+ (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
*save_addr = a;
}
@@ -198,7 +198,7 @@ void post_word_store (ulong a)
ulong post_word_load (void)
{
volatile ulong *save_addr =
- (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
+ (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
return *save_addr;
}
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 2fe3cea..943602f 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -25,9 +25,12 @@
* MA 02111-1307 USA
*/
+#include <config.h>
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <tsec.h>
+#include <netdev.h>
#include <asm/cache.h>
#include <asm/io.h>
@@ -81,9 +84,11 @@ int checkcpu (void)
uint ver;
uint major, minor;
struct cpu_type *cpu;
+ char buf1[32], buf2[32];
#ifdef CONFIG_DDR_CLK_FREQ
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+ >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
u32 ddr_ratio = 0;
#endif
@@ -96,7 +101,12 @@ int checkcpu (void)
#endif
minor = SVR_MIN(svr);
+#if (CONFIG_NUM_CPUS > 1)
+ volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+ printf("CPU%d: ", pic->whoami);
+#else
puts("CPU: ");
+#endif
cpu = identify_cpu(ver);
if (cpu) {
@@ -125,34 +135,41 @@ int checkcpu (void)
puts("Unknown");
break;
}
+
+ if (PVR_MEM(pvr) == 0x03)
+ puts("MC");
+
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);
puts("Clock Configuration:\n");
- printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
- printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
+ printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
+ printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
switch (ddr_ratio) {
case 0x0:
- printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
- DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
+ printf(" DDR:%-4s MHz (%s MT/s data rate), ",
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
break;
case 0x7:
- printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
- DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
+ printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
break;
default:
- printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
- DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
+ printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
break;
}
-#if defined(CFG_LBC_LCRR)
- lcrr = CFG_LBC_LCRR;
+#if defined(CONFIG_SYS_LBC_LCRR)
+ lcrr = CONFIG_SYS_LBC_LCRR;
#else
{
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
lcrr = lbc->lcrr;
}
@@ -167,14 +184,14 @@ int checkcpu (void)
*/
clkdiv *= 2;
#endif
- printf("LBC:%4lu MHz\n",
- DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
+ printf("LBC:%-4s MHz\n",
+ strmhz(buf1, sysinfo.freqSystemBus / clkdiv));
} else {
printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
}
#ifdef CONFIG_CPM2
- printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+ printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
#endif
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
@@ -197,7 +214,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
if (ver & 1){
/* e500 v2 core has reset control register */
volatile unsigned int * rstcr;
- rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
+ rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
*rstcr = 0x2; /* HRESET_REQ */
udelay(100);
}
@@ -253,7 +270,7 @@ reset_85xx_watchdog(void)
#if defined(CONFIG_DDR_ECC)
void dma_init(void) {
- volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
+ volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
dma->satr0 = 0x02c40000;
dma->datr0 = 0x02c40000;
@@ -263,7 +280,7 @@ void dma_init(void) {
}
uint dma_check(void) {
- volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
+ volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
volatile uint status = dma->sr0;
/* While the channel is busy, spin */
@@ -282,7 +299,7 @@ uint dma_check(void) {
}
int dma_xfer(void *dest, uint count, void *src) {
- volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
+ volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
dma->dar0 = (uint) dest;
dma->sar0 = (uint) src;
@@ -294,16 +311,16 @@ int dma_xfer(void *dest, uint count, void *src) {
return dma_check();
}
#endif
+
/*
- * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
- * are hardcoded as "1"."size" is the number or entries, not a sizeof.
+ * Configures a UPM. The function requires the respective MxMR to be set
+ * before calling this function. "size" is the number or entries, not a sizeof.
*/
void upmconfig (uint upm, uint * table, uint size)
{
int i, mdr, mad, old_mad = 0;
volatile u32 *mxmr;
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
- int loopval = 0x00004440;
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile u32 *brp,*orp;
volatile u8* dummy = NULL;
int upmmask;
@@ -331,8 +348,8 @@ void upmconfig (uint upm, uint * table, uint size)
i++, brp += 2, orp += 2) {
/* Look for a valid BR with selected UPM */
- if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
- dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
+ if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
+ dummy = (volatile u8*)(in_be32(brp) & BR_BA);
break;
}
}
@@ -344,7 +361,7 @@ void upmconfig (uint upm, uint * table, uint size)
for (i = 0; i < size; i++) {
/* 1 */
- out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */
+ out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
/* 2 */
out_be32(&lbc->mdr, table[i]);
/* 3 */
@@ -353,39 +370,43 @@ void upmconfig (uint upm, uint * table, uint size)
*(volatile u8 *)dummy = 0;
/* 5 */
do {
- mad = in_be32(mxmr) & 0x3f;
+ mad = in_be32(mxmr) & MxMR_MAD_MSK;
} while (mad <= old_mad && !(!mad && i == (size-1)));
old_mad = mad;
}
- out_be32(mxmr, loopval); /* OP_NORMAL */
+ out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
}
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIGMPC85XX_FEC)
-/* Default initializations for TSEC controllers. To override,
- * create a board-specific function called:
- * int board_eth_init(bd_t *bis)
- */
-
-extern int tsec_initialize(bd_t * bis, int index, char *devname);
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
int cpu_eth_init(bd_t *bis)
{
-#if defined(CONFIG_TSEC1)
- tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
+#if defined(CONFIG_ETHER_ON_FCC)
+ fec_initialize(bis);
#endif
-#if defined(CONFIG_TSEC2)
- tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
+#if defined(CONFIG_UEC_ETH1)
+ uec_initialize(0);
#endif
-#if defined(CONFIG_MPC85XX_FEC)
- tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME);
-#else
-#if defined(CONFIG_TSEC3)
- tsec_initialize(bis, 2, CONFIG_TSEC3_NAME);
+#if defined(CONFIG_UEC_ETH2)
+ uec_initialize(1);
+#endif
+#if defined(CONFIG_UEC_ETH3)
+ uec_initialize(2);
#endif
-#if defined(CONFIG_TSEC4)
- tsec_initialize(bis, 3, CONFIG_TSEC4_NAME);
+#if defined(CONFIG_UEC_ETH4)
+ uec_initialize(3);
#endif
+#if defined(CONFIG_UEC_ETH5)
+ uec_initialize(4);
+#endif
+#if defined(CONFIG_UEC_ETH6)
+ uec_initialize(5);
+#endif
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
+ tsec_standard_init(bis);
#endif
return 0;
}
-#endif
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 783c5ba..0b7c609 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -132,32 +132,33 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
/* We run cpu_init_early_f in AS = 1 */
void cpu_init_early_f(void)
{
- set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+ /* Clear initial global data */
+ memset ((void *) gd, 0, sizeof (gd_t));
+
+ set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
1, 0, BOOKE_PAGESZ_4K, 0);
/* set up CCSR if we want it moved */
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS)
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
{
u32 temp;
+ volatile u32 *ccsr_virt =
+ (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
- set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT,
+ set_tlb(0, (u32)ccsr_virt, CONFIG_SYS_CCSRBAR_DEFAULT,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
1, 1, BOOKE_PAGESZ_4K, 0);
- temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT);
- out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12);
-
- temp = in_be32((volatile u32 *)CFG_CCSRBAR);
+ temp = in_be32(ccsr_virt);
+ out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
+ temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
}
#endif
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
-
- /* Clear initial global data */
- memset ((void *) gd, 0, sizeof (gd_t));
-
init_laws();
invalidate_tlb(0);
init_tlbs();
@@ -172,69 +173,82 @@ void cpu_init_early_f(void)
void cpu_init_f (void)
{
- volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
extern void m8560_cpm_reset (void);
+#ifdef CONFIG_MPC8548
+ ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ uint svr = get_svr();
+
+ /*
+ * CPU2 errata workaround: A core hang possible while executing
+ * a msync instruction and a snoopable transaction from an I/O
+ * master tagged to make quick forward progress is present.
+ * Fixed in silicon rev 2.1.
+ */
+ if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
+ out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
+#endif
disable_tlb(14);
disable_tlb(15);
#ifdef CONFIG_CPM2
- config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
+ config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
#endif
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
-#if defined(CFG_OR0_REMAP)
- memctl->or0 = CFG_OR0_REMAP;
+#if defined(CONFIG_SYS_OR0_REMAP)
+ memctl->or0 = CONFIG_SYS_OR0_REMAP;
#endif
-#if defined(CFG_OR1_REMAP)
- memctl->or1 = CFG_OR1_REMAP;
+#if defined(CONFIG_SYS_OR1_REMAP)
+ memctl->or1 = CONFIG_SYS_OR1_REMAP;
#endif
/* now restrict to preliminary range */
/* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (! memctl->br1 & 1) {
-#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
- memctl->br0 = CFG_BR0_PRELIM;
- memctl->or0 = CFG_OR0_PRELIM;
+#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
+ memctl->br0 = CONFIG_SYS_BR0_PRELIM;
+ memctl->or0 = CONFIG_SYS_OR0_PRELIM;
#endif
-#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
- memctl->or1 = CFG_OR1_PRELIM;
- memctl->br1 = CFG_BR1_PRELIM;
+#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
+ memctl->or1 = CONFIG_SYS_OR1_PRELIM;
+ memctl->br1 = CONFIG_SYS_BR1_PRELIM;
#endif
}
-#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
- memctl->or2 = CFG_OR2_PRELIM;
- memctl->br2 = CFG_BR2_PRELIM;
+#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
+ memctl->or2 = CONFIG_SYS_OR2_PRELIM;
+ memctl->br2 = CONFIG_SYS_BR2_PRELIM;
#endif
-#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
- memctl->or3 = CFG_OR3_PRELIM;
- memctl->br3 = CFG_BR3_PRELIM;
+#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
+ memctl->or3 = CONFIG_SYS_OR3_PRELIM;
+ memctl->br3 = CONFIG_SYS_BR3_PRELIM;
#endif
-#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
- memctl->or4 = CFG_OR4_PRELIM;
- memctl->br4 = CFG_BR4_PRELIM;
+#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
+ memctl->or4 = CONFIG_SYS_OR4_PRELIM;
+ memctl->br4 = CONFIG_SYS_BR4_PRELIM;
#endif
-#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
- memctl->or5 = CFG_OR5_PRELIM;
- memctl->br5 = CFG_BR5_PRELIM;
+#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
+ memctl->or5 = CONFIG_SYS_OR5_PRELIM;
+ memctl->br5 = CONFIG_SYS_BR5_PRELIM;
#endif
-#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
- memctl->or6 = CFG_OR6_PRELIM;
- memctl->br6 = CFG_BR6_PRELIM;
+#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
+ memctl->or6 = CONFIG_SYS_OR6_PRELIM;
+ memctl->br6 = CONFIG_SYS_BR6_PRELIM;
#endif
-#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
- memctl->or7 = CFG_OR7_PRELIM;
- memctl->br7 = CFG_BR7_PRELIM;
+#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
+ memctl->or7 = CONFIG_SYS_OR7_PRELIM;
+ memctl->br7 = CONFIG_SYS_BR7_PRELIM;
#endif
#if defined(CONFIG_CPM2)
@@ -264,7 +278,7 @@ int cpu_init_r(void)
puts ("L2: ");
#if defined(CONFIG_L2_CACHE)
- volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
+ volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
volatile uint cache_ctl;
uint svr, ver;
uint l2srbar;
@@ -317,13 +331,13 @@ int cpu_init_r(void)
if (l2cache->l2ctl & 0x80000000) {
puts("already enabled");
l2srbar = l2cache->l2srbar0;
-#ifdef CFG_INIT_L2_ADDR
- if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
- l2srbar = CFG_INIT_L2_ADDR;
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ if (l2cache->l2ctl & 0x00010000 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
+ l2srbar = CONFIG_SYS_INIT_L2_ADDR;
l2cache->l2srbar0 = l2srbar;
- printf("moving to 0x%08x", CFG_INIT_L2_ADDR);
+ printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
}
-#endif /* CFG_INIT_L2_ADDR */
+#endif /* CONFIG_SYS_INIT_L2_ADDR */
puts("\n");
} else {
asm("msync;isync");
@@ -335,7 +349,7 @@ int cpu_init_r(void)
puts("disabled\n");
#endif
#ifdef CONFIG_QE
- uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
+ uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
qe_init(qe_base);
qe_reset();
#endif
diff --git a/cpu/mpc85xx/ddr-gen1.c b/cpu/mpc85xx/ddr-gen1.c
index 2c11ee4..e24c9af 100644
--- a/cpu/mpc85xx/ddr-gen1.c
+++ b/cpu/mpc85xx/ddr-gen1.c
@@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num)
{
unsigned int i;
- volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR;
+ volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
if (ctrl_num != 0) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@@ -79,7 +79,7 @@ ddr_enable_ecc(unsigned int dram_size)
{
uint *p = 0;
uint i = 0;
- volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+ volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
dma_init();
diff --git a/cpu/mpc85xx/ddr-gen2.c b/cpu/mpc85xx/ddr-gen2.c
index 130090c..655f99c 100644
--- a/cpu/mpc85xx/ddr-gen2.c
+++ b/cpu/mpc85xx/ddr-gen2.c
@@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num)
{
unsigned int i;
- volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR;
+ volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
if (ctrl_num) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c
index d7cc9db..a2b45c5 100644
--- a/cpu/mpc85xx/ddr-gen3.c
+++ b/cpu/mpc85xx/ddr-gen3.c
@@ -22,10 +22,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) {
case 0:
- ddr = (void *)CFG_MPC85xx_DDR_ADDR;
+ ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
break;
case 1:
- ddr = (void *)CFG_MPC85xx_DDR2_ADDR;
+ ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
break;
default:
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@@ -79,15 +79,18 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
/*
- * 32-bit workaround for DDR2
- * 32_BE
+ * For 8572 DDR1 erratum - DDR controller may enter illegal state
+ * when operatiing in 32-bit bus mode with 4-beat bursts,
+ * This erratum does not affect DDR3 mode, only for DDR2 mode.
*/
+#ifdef CONFIG_MPC8572
if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
- && in_be32(&ddr->sdram_cfg_2) & 0x80000) {
+ && in_be32(&ddr->sdram_cfg) & 0x80000) {
/* set DEBUG_1[31] */
u32 temp = in_be32(&ddr->debug_1);
out_be32(&ddr->debug_1, temp | 1);
}
+#endif
/*
* 200 painful micro-seconds must elapse between
diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c
index bd62aab..32ad469 100644
--- a/cpu/mpc85xx/ether_fcc.c
+++ b/cpu/mpc85xx/ether_fcc.c
@@ -74,8 +74,8 @@ static struct ether_fcc_info_s
PROFF_FCC1,
CPM_CR_FCC1_SBLOCK,
CPM_CR_FCC1_PAGE,
- CFG_CMXFCR_MASK1,
- CFG_CMXFCR_VALUE1
+ CONFIG_SYS_CMXFCR_MASK1,
+ CONFIG_SYS_CMXFCR_VALUE1
},
#endif
@@ -85,8 +85,8 @@ static struct ether_fcc_info_s
PROFF_FCC2,
CPM_CR_FCC2_SBLOCK,
CPM_CR_FCC2_PAGE,
- CFG_CMXFCR_MASK2,
- CFG_CMXFCR_VALUE2
+ CONFIG_SYS_CMXFCR_MASK2,
+ CONFIG_SYS_CMXFCR_VALUE2
},
#endif
@@ -96,8 +96,8 @@ static struct ether_fcc_info_s
PROFF_FCC3,
CPM_CR_FCC3_SBLOCK,
CPM_CR_FCC3_PAGE,
- CFG_CMXFCR_MASK3,
- CFG_CMXFCR_VALUE3
+ CONFIG_SYS_CMXFCR_MASK3,
+ CONFIG_SYS_CMXFCR_VALUE3
},
#endif
};
@@ -230,7 +230,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
{
struct ether_fcc_info_s * info = dev->priv;
int i;
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
fcc_enet_t *pram_ptr;
unsigned long mem_addr;
@@ -257,11 +257,11 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
/* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
} else if (info->ether_index == 1){
- cpm->im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
} else if (info->ether_index == 2){
- cpm->im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
}
/* 28.9 - (6): FDSR: Ethernet Syn */
@@ -321,14 +321,14 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
/* localbus SDRAM should be preferred */
pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
- CFG_CPMFCR_RAMTYPE) << 24;
+ CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
pram_ptr->fen_genfcc.fcc_rbdstat = 0;
pram_ptr->fen_genfcc.fcc_rbdlen = 0;
pram_ptr->fen_genfcc.fcc_rdptr = 0;
/* localbus SDRAM should be preferred */
pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
- CFG_CPMFCR_RAMTYPE) << 24;
+ CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
pram_ptr->fen_genfcc.fcc_tbdstat = 0;
pram_ptr->fen_genfcc.fcc_tbdlen = 0;
@@ -426,7 +426,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
static void fec_halt(struct eth_device* dev)
{
struct ether_fcc_info_s * info = dev->priv;
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
/* write GFMR: disable tx/rx */
if(info->ether_index == 0) {
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index bc1550d..59aafb1 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -83,7 +83,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
/* return size in kilobytes */
static inline u32 l2cache_size(void)
{
- volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
+ volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
u32 ver = SVR_SOC_VER(get_svr());
@@ -152,7 +152,6 @@ static inline void ft_fixup_l2cache(void *blob)
}
fdt_setprop(blob, off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
- fdt_setprop_cell(blob, off, "cache-line-size", line_size);
fdt_setprop_cell(blob, off, "cache-size", size);
fdt_setprop_cell(blob, off, "cache-sets", num_sets);
fdt_setprop_cell(blob, off, "cache-level", 2);
@@ -181,7 +180,6 @@ static inline void ft_fixup_cache(void *blob)
dnum_sets = dsize / (dline_size * dnum_ways);
fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
- fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size);
fdt_setprop_cell(blob, off, "d-cache-size", dsize);
fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
@@ -192,7 +190,6 @@ static inline void ft_fixup_cache(void *blob)
inum_sets = isize / (iline_size * inum_ways);
fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
- fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size);
fdt_setprop_cell(blob, off, "i-cache-size", isize);
fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
@@ -204,6 +201,15 @@ static inline void ft_fixup_cache(void *blob)
}
+void fdt_add_enet_stashing(void *fdt)
+{
+ do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
+
+ do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
+
+ do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
+}
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
/* delete crypto node if not on an E-processor */
@@ -213,6 +219,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
fdt_fixup_ethernet(blob);
+
+ fdt_add_enet_stashing(blob);
#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
@@ -227,9 +235,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_qe_setup(blob);
#endif
-#ifdef CFG_NS16550
+#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "ns16550",
- "clock-frequency", CFG_NS16550_CLK, 1);
+ "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
#endif
#ifdef CONFIG_CPM2
diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c
index 06d4d8b..4ef8395 100644
--- a/cpu/mpc85xx/interrupts.c
+++ b/cpu/mpc85xx/interrupts.c
@@ -34,43 +34,43 @@
int interrupt_init_cpu(unsigned long *decrementer_count)
{
- volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
pic->gcr = MPC85xx_PICGCR_RST;
while (pic->gcr & MPC85xx_PICGCR_RST)
;
pic->gcr = MPC85xx_PICGCR_M;
- *decrementer_count = get_tbclk() / CFG_HZ;
+ *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
/* PIE is same as DIE, dec interrupt enable */
mtspr(SPRN_TCR, TCR_PIE);
#ifdef CONFIG_INTERRUPTS
pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
- debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
+ debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1);
pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
- debug("iivpr2@%x = %x\n",&pic->iivpr2, pic->iivpr2);
+ debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2);
pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
- debug("iivpr3@%x = %x\n",&pic->iivpr3, pic->iivpr3);
+ debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3);
#ifdef CONFIG_PCI1
pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
- debug("iivpr8@%x = %x\n",&pic->iivpr8, pic->iivpr8);
+ debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8);
#endif
#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
- debug("iivpr9@%x = %x\n",&pic->iivpr9, pic->iivpr9);
+ debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9);
#endif
#ifdef CONFIG_PCIE1
pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */
- debug("iivpr10@%x = %x\n",&pic->iivpr10, pic->iivpr10);
+ debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10);
#endif
#ifdef CONFIG_PCIE3
pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */
- debug("iivpr11@%x = %x\n",&pic->iivpr11, pic->iivpr11);
+ debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11);
#endif
pic->ctpr=0; /* 40080 clear current task priority register */
diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index 4e09c9c..3338c1a 100644
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -36,7 +36,7 @@ u32 get_my_id()
int cpu_reset(int nr)
{
- volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
out_be32(&pic->pir, 1 << nr);
(void)in_be32(&pic->pir);
out_be32(&pic->pir, 0x0);
@@ -87,7 +87,7 @@ int cpu_release(int nr, int argc, char *argv[])
return 1;
}
-#ifdef CFG_64BIT_STRTOUL
+#ifdef CONFIG_SYS_64BIT_STRTOUL
boot_addr = simple_strtoull(argv[0], NULL, 16);
#else
boot_addr = simple_strtoul(argv[0], NULL, 16);
@@ -129,9 +129,9 @@ static void pq3_mp_up(unsigned long bootpg)
u32 up, cpu_up_mask, whoami;
u32 *table = (u32 *)get_spin_addr();
volatile u32 bpcr;
- volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
u32 devdisr;
int timeout = 10;
diff --git a/cpu/mpc85xx/mpc8536_serdes.c b/cpu/mpc85xx/mpc8536_serdes.c
index ae091e6..d9ac466 100644
--- a/cpu/mpc85xx/mpc8536_serdes.c
+++ b/cpu/mpc85xx/mpc8536_serdes.c
@@ -54,8 +54,8 @@
void fsl_serdes_init(void)
{
- void *guts = (void *)(CFG_MPC85xx_GUTS_ADDR);
- void *sd = (void *)CFG_MPC85xx_SERDES2_ADDR;
+ void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
u32 srds2_io_sel;
u32 tmp;
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index fdc4c83..787c6eb 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -39,11 +39,11 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
u16 reg16;
u32 dev;
- volatile ccsr_pcix_t *pcix = (void *)(CFG_MPC85xx_PCIX_ADDR);
+ volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
#ifdef CONFIG_MPC85XX_PCI2
- volatile ccsr_pcix_t *pcix2 = (void *)(CFG_MPC85xx_PCIX2_ADDR);
+ volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
#endif
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct pci_controller * hose;
pci_hose = board_hose;
@@ -54,8 +54,8 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
hose->last_busno = 0xff;
pci_setup_indirect(hose,
- (CFG_IMMR+0x8000),
- (CFG_IMMR+0x8004));
+ (CONFIG_SYS_IMMR+0x8000),
+ (CONFIG_SYS_IMMR+0x8004));
/*
* Hose scan.
@@ -70,7 +70,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
*/
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- if (!(gur->pordevsr & PORDEVSR_PCI)) {
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
/* PCI-X init */
if (CONFIG_SYS_CLK_FREQ < 66000000)
printf("PCI-X will only work at 66 MHz\n");
@@ -80,19 +80,19 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
}
- pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+ pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & 0x000fffff;
pcix->potear1 = 0x00000000;
- pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
+ pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
pcix->powbear1 = 0x00000000;
pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
- POWAR_MEM_WRITE | (__ilog2(CFG_PCI1_MEM_SIZE) - 1));
+ POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
- pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
+ pcix->potar2 = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff;
pcix->potear2 = 0x00000000;
- pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
+ pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
pcix->powbear2 = 0x00000000;
pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
- POWAR_IO_WRITE | (__ilog2(CFG_PCI1_IO_SIZE) - 1));
+ POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
pcix->pitar1 = 0x00000000;
pcix->piwbar1 = 0x00000000;
@@ -105,15 +105,15 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pcix->piwar3 = 0;
pci_set_region(hose->regions + 0,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
+ CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_PHYS,
+ CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
pci_set_region(hose->regions + 1,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
+ CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_PHYS,
+ CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 2;
@@ -152,8 +152,8 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
hose->last_busno = 0xff;
pci_setup_indirect(hose,
- (CFG_IMMR+0x9000),
- (CFG_IMMR+0x9004));
+ (CONFIG_SYS_IMMR+0x9000),
+ (CONFIG_SYS_IMMR+0x9004));
dev = PCI_BDF(hose->first_busno, 0, 0);
pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
@@ -165,19 +165,19 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
*/
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff;
+ pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & 0x000fffff;
pcix2->potear1 = 0x00000000;
- pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
+ pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
pcix2->powbear1 = 0x00000000;
pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
- POWAR_MEM_WRITE | (__ilog2(CFG_PCI2_MEM_SIZE) - 1));
+ POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
- pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
+ pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff;
pcix2->potear2 = 0x00000000;
- pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
+ pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
pcix2->powbear2 = 0x00000000;
pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
- POWAR_IO_WRITE | (__ilog2(CFG_PCI2_IO_SIZE) - 1));
+ POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
pcix2->pitar1 = 0x00000000;
pcix2->piwbar1 = 0x00000000;
@@ -190,15 +190,15 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pcix2->piwar3 = 0;
pci_set_region(hose->regions + 0,
- CFG_PCI2_MEM_BASE,
- CFG_PCI2_MEM_PHYS,
- CFG_PCI2_MEM_SIZE,
+ CONFIG_SYS_PCI2_MEM_BASE,
+ CONFIG_SYS_PCI2_MEM_PHYS,
+ CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
pci_set_region(hose->regions + 1,
- CFG_PCI2_IO_BASE,
- CFG_PCI2_IO_PHYS,
- CFG_PCI2_IO_SIZE,
+ CONFIG_SYS_PCI2_IO_BASE,
+ CONFIG_SYS_PCI2_IO_PHYS,
+ CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 2;
diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c
index 21ea38b..72a29b7 100644
--- a/cpu/mpc85xx/qe_io.c
+++ b/cpu/mpc85xx/qe_io.c
@@ -34,7 +34,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
u32 pin_2bit_assign;
u32 pin_1bit_mask;
u32 tmp_val;
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile par_io_t *par_io = (volatile par_io_t *)
&(gur->qe_par_io);
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 75676b5..7c3e8a1 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -24,19 +24,28 @@
__secondary_start_page:
/* First do some preliminary setup */
lis r3, HID0_EMCP@h /* enable machine check */
+#ifndef CONFIG_E500MC
ori r3,r3,HID0_TBEN@l /* enable Timebase */
+#endif
#ifdef CONFIG_PHYS_64BIT
ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
#endif
mtspr SPRN_HID0,r3
+#ifndef CONFIG_E500MC
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr SPRN_HID1,r3
+#endif
/* Enable branch prediction */
li r3,0x201
mtspr SPRN_BUCSR,r3
+ /* Ensure TB is 0 */
+ li r3,0
+ mttbl r3
+ mttbu r3
+
/* Enable/invalidate the I-Cache */
mfspr r0,SPRN_L1CSR1
ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
@@ -59,7 +68,11 @@ __secondary_start_page:
/* r10 has the base address for the entry */
mfspr r0,SPRN_PIR
+#ifdef CONFIG_E500MC
+ rlwinm r4,r0,27,27,31
+#else
mr r4,r0
+#endif
slwi r8,r4,5
add r10,r3,r8
diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c
index 7ee3cc8..05fb808 100644
--- a/cpu/mpc85xx/serial_scc.c
+++ b/cpu/mpc85xx/serial_scc.c
@@ -88,7 +88,7 @@ DECLARE_GLOBAL_DATA_PTR;
int serial_init (void)
{
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
volatile ccsr_cpm_scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -201,7 +201,7 @@ serial_putc(const char c)
{
volatile scc_uart_t *up;
volatile cbd_t *tbdf;
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
if (c == '\n')
serial_putc ('\r');
@@ -234,7 +234,7 @@ serial_getc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
unsigned char c;
up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
@@ -258,7 +258,7 @@ serial_tstc()
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 1cda1e3..1e0f483 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info (sys_info_t * sysInfo)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint plat_ratio,e500_ratio,half_freqSystemBus;
plat_ratio = (gur->porpllsr) & 0x0000003e;
@@ -54,7 +54,8 @@ void get_sys_info (sys_info_t * sysInfo)
#ifdef CONFIG_DDR_CLK_FREQ
{
- u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+ >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
if (ddr_ratio != 0x7)
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
}
@@ -66,10 +67,10 @@ int get_clocks (void)
{
sys_info_t sys_info;
#ifdef CONFIG_MPC8544
- volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR;
+ volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
#endif
#if defined(CONFIG_CPM2)
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
uint sccr, dfbrg;
/* set VCO = 4 * BRG */
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 10fe936..8fa0ff7 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -30,6 +30,7 @@
#include <config.h>
#include <mpc85xx.h>
+#include <timestamp.h>
#include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
@@ -163,8 +164,10 @@ _start_e500:
ori r0,r0,HID0_TBEN@l /* Enable Timebase */
mtspr HID0,r0
+#ifndef CONFIG_E500MC
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr HID1,r0
+#endif
/* Enable Branch Prediction */
#if defined(CONFIG_BTB)
@@ -172,12 +175,12 @@ _start_e500:
mtspr BUCSR,r0
#endif
-#if defined(CFG_INIT_DBCR)
+#if defined(CONFIG_SYS_INIT_DBCR)
lis r1,0xffff
ori r1,r1,0xffff
mtspr DBSR,r1 /* Clear all status bits */
- lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */
- ori r0,r0,CFG_INIT_DBCR@l
+ lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
+ ori r0,r0,CONFIG_SYS_INIT_DBCR@l
mtspr DBCR0,r0
#endif
@@ -210,11 +213,11 @@ _start_e500:
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
- lis r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@h
- ori r8,r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@l
+ lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
+ ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
- lis r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
mtspr MAS0,r6
mtspr MAS1,r7
@@ -238,8 +241,8 @@ switch_as:
/* Allocate Initial RAM in data cache.
*/
- lis r3,CFG_INIT_RAM_ADDR@h
- ori r3,r3,CFG_INIT_RAM_ADDR@l
+ lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
mfspr r2, L1CFG0
andi. r2, r2, 0x1ff
/* cache size * 1024 / (2 * L1 line size) */
@@ -249,17 +252,17 @@ switch_as:
1:
dcbz r0,r3
dcbtls 0,r0,r3
- addi r3,r3,CFG_CACHELINE_SIZE
+ addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
/* Jump out the last 4K page and continue to 'normal' start */
-#ifdef CFG_RAMBOOT
+#ifdef CONFIG_SYS_RAMBOOT
b _start_cont
#else
/* Calculate absolute address in FLASH and jump there */
/*--------------------------------------------------------------*/
- lis r3,CFG_MONITOR_BASE@h
- ori r3,r3,CFG_MONITOR_BASE@l
+ lis r3,CONFIG_SYS_MONITOR_BASE@h
+ ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
addi r3,r3,_start_cont - _start + _START_OFFSET
mtlr r3
blr
@@ -272,15 +275,15 @@ _start:
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
.align 4
.globl _start_cont
_start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
- lis r1,CFG_INIT_RAM_ADDR@h
- ori r1,r1,CFG_INIT_SP_OFFSET@l
+ lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
li r0,0
stwu r0,-4(r1)
@@ -565,6 +568,7 @@ mck_return:
/* Cache functions.
*/
+.globl invalidate_icache
invalidate_icache:
mfspr r0,L1CSR1
ori r0,r0,L1CSR1_ICFI
@@ -574,6 +578,7 @@ invalidate_icache:
isync
blr /* entire I cache */
+.globl invalidate_dcache
invalidate_dcache:
mfspr r0,L1CSR0
ori r0,r0,L1CSR0_DCFI
@@ -778,16 +783,16 @@ relocate_code:
mr r10,r5 /* Save copy of Destination Address */
mr r3,r5 /* Destination Address */
- lis r4,CFG_MONITOR_BASE@h /* Source Address */
- ori r4,r4,CFG_MONITOR_BASE@l
+ lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
lwz r5,GOT(__init_end)
sub r5,r5,r4
- li r6,CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
@@ -996,20 +1001,20 @@ trap_reloc:
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
- lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
- ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
+ lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
+ ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
mfspr r4,L1CFG0
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: dcbi r0,r3
- addi r3,r3,CFG_CACHELINE_SIZE
+ addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
sync
/* Invalidate the TLB entries for the cache */
- lis r3,CFG_INIT_RAM_ADDR@h
- ori r3,r3,CFG_INIT_RAM_ADDR@l
+ lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
tlbivax 0,r3
addi r3,r3,0x1000
tlbivax 0,r3
@@ -1019,3 +1024,50 @@ unlock_ram_in_cache:
tlbivax 0,r3
isync
blr
+
+.globl flush_dcache
+flush_dcache:
+ mfspr r3,SPRN_L1CFG0
+
+ rlwinm r5,r3,9,3 /* Extract cache block size */
+ twlgti r5,1 /* Only 32 and 64 byte cache blocks
+ * are currently defined.
+ */
+ li r4,32
+ subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
+ * log2(number of ways)
+ */
+ slw r5,r4,r5 /* r5 = cache block size */
+
+ rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
+ mulli r7,r7,13 /* An 8-way cache will require 13
+ * loads per set.
+ */
+ slw r7,r7,r6
+
+ /* save off HID0 and set DCFA */
+ mfspr r8,SPRN_HID0
+ ori r9,r8,HID0_DCFA@l
+ mtspr SPRN_HID0,r9
+ isync
+
+ lis r4,0
+ mtctr r7
+
+1: lwz r3,0(r4) /* Load... */
+ add r4,r4,r5
+ bdnz 1b
+
+ msync
+ lis r4,0
+ mtctr r7
+
+1: dcbf 0,r4 /* ...and flush. */
+ add r4,r4,r5
+ bdnz 1b
+
+ /* restore HID0 */
+ mtspr SPRN_HID0,r8
+ isync
+
+ blr
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 7ce7a14..a2d16ae 100644
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -138,7 +138,7 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
* Starting at TLB1 8, use no more than 8 TLB1 entries.
*/
ram_tlb_index = 8;
- ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
+ ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
&& ram_tlb_index < 16) {
set_tlb(1, ram_tlb_address, ram_tlb_address,
diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c
index 0eab694..1045cc1 100644
--- a/cpu/mpc85xx/traps.c
+++ b/cpu/mpc85xx/traps.c
@@ -290,7 +290,7 @@ UnknownException(struct pt_regs *regs)
void
ExtIntException(struct pt_regs *regs)
{
- volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
uint vect;
diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile
index a9767ad..34a9755 100644
--- a/cpu/mpc86xx/Makefile
+++ b/cpu/mpc86xx/Makefile
@@ -31,6 +31,10 @@ LIB = $(obj)lib$(CPU).a
START = start.o
SOBJS = cache.o
+ifneq ($(CONFIG_NUM_CPUS),1)
+COBJS-y += mp.o
+SOBJS += release.o
+endif
COBJS-y += traps.o
COBJS-y += cpu.o
COBJS-y += cpu_init.o
diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S
index 80ff688..0bb058b 100644
--- a/cpu/mpc86xx/cache.S
+++ b/cpu/mpc86xx/cache.S
@@ -53,7 +53,7 @@ _GLOBAL(invalidate_l1_data_cache)
/*
* Flush data cache.
*/
-_GLOBAL(flush_data_cache)
+_GLOBAL(flush_dcache)
lis r3,0
lis r5,CACHE_LINE_SIZE
flush:
@@ -279,7 +279,7 @@ _GLOBAL(dcache_enable)
mtspr HID0, r5 /* enable + invalidate */
mtspr HID0, r3 /* enable */
sync
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
mflr r5
bl l2cache_enable /* uses r3 and r4 */
sync
@@ -290,12 +290,12 @@ _GLOBAL(dcache_enable)
/*
* Disable data cache(s) - L1 and optionally L2
- * Calls flush_data_cache and l2cache_disable_no_flush.
+ * Calls flush_dcache and l2cache_disable_no_flush.
* LR saved in r4
*/
_GLOBAL(dcache_disable)
mflr r4 /* save link register */
- bl flush_data_cache /* uses r3 and r5 */
+ bl flush_dcache /* uses r3 and r5 */
sync
mfspr r3, HID0
li r5, HID0_DCFI|HID0_DLOCK
@@ -305,7 +305,7 @@ _GLOBAL(dcache_disable)
andc r3, r3, r5 /* no enable, no invalidate */
mtspr HID0, r3
sync
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
bl l2cache_disable_no_flush /* uses r3 */
#endif
mtlr r4 /* restore link register */
@@ -363,11 +363,11 @@ _GLOBAL(l2cache_enable)
/*
* Disable L2 cache
- * Calls flush_data_cache. LR is saved in r4
+ * Calls flush_dcache. LR is saved in r4
*/
_GLOBAL(l2cache_disable)
mflr r4 /* save link register */
- bl flush_data_cache /* uses r3 and r5 */
+ bl flush_dcache /* uses r3 and r5 */
sync
mtlr r4 /* restore link register */
l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index ecea5b0..4cace98 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -28,6 +28,7 @@
#include <asm/cache.h>
#include <asm/mmu.h>
#include <mpc86xx.h>
+#include <tsec.h>
#include <asm/fsl_law.h>
@@ -40,7 +41,7 @@ checkcpu(void)
uint major, minor;
uint lcrr; /* local bus clock ratio register */
uint clkdiv; /* clock divider portion of lcrr */
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
puts("Freescale PowerPC\n");
@@ -99,11 +100,11 @@ checkcpu(void)
printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
-#if defined(CFG_LBC_LCRR)
- lcrr = CFG_LBC_LCRR;
+#if defined(CONFIG_SYS_LBC_LCRR)
+ lcrr = CONFIG_SYS_LBC_LCRR;
#else
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
lcrr = lbc->lcrr;
@@ -160,16 +161,16 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
-#ifdef CFG_RESET_ADDRESS
- ulong addr = CFG_RESET_ADDRESS;
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ ulong addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
- * note: when CFG_MONITOR_BASE points to a RAM address,
- * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
+ * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
+ * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
* address. Better pick an address known to be invalid on your
- * system and assign it to CFG_RESET_ADDRESS.
+ * system and assign it to CONFIG_SYS_RESET_ADDRESS.
*/
- ulong addr = CFG_MONITOR_BASE - sizeof(ulong);
+ ulong addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
#endif
/* flush and disable I/D cache */
@@ -218,7 +219,7 @@ watchdog_reset(void)
/*
* This actually feed the hard enabled watchdog.
*/
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_wdt_t *wdt = &immap->im_wdt;
volatile ccsr_gur_t *gur = &immap->im_gur;
u32 tmp = gur->pordevsr;
@@ -236,7 +237,7 @@ watchdog_reset(void)
void
dma_init(void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
dma->satr0 = 0x00040000;
@@ -247,7 +248,7 @@ dma_init(void)
uint
dma_check(void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
volatile uint status = dma->sr0;
@@ -265,7 +266,7 @@ dma_check(void)
int
dma_xfer(void *dest, uint count, void *src)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
dma->dar0 = (uint) dest;
@@ -287,7 +288,7 @@ dma_xfer(void *dest, uint count, void *src)
*/
void mpc86xx_reginfo(void)
{
- immap_t *immap = (immap_t *)CFG_IMMR;
+ immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
ccsr_lbc_t *lbc = &immap->im_lbc;
print_bats();
@@ -305,28 +306,15 @@ void mpc86xx_reginfo(void)
}
-#ifdef CONFIG_TSEC_ENET
-/* Default initializations for TSEC controllers. To override,
- * create a board-specific function called:
- * int board_eth_init(bd_t *bis)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
*/
-
-extern int tsec_initialize(bd_t * bis, int index, char *devname);
-
int cpu_eth_init(bd_t *bis)
{
-#if defined(CONFIG_TSEC1)
- tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
-#endif
-#if defined(CONFIG_TSEC2)
- tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
-#endif
-#if defined(CONFIG_TSEC3)
- tsec_initialize(bis, 2, CONFIG_TSEC3_NAME);
-#endif
-#if defined(CONFIG_TSEC4)
- tsec_initialize(bis, 3, CONFIG_TSEC4_NAME);
+#if defined(CONFIG_TSEC_ENET)
+ tsec_standard_init(bis);
#endif
+
return 0;
}
-#endif /* CONFIG_TSEC_ENET */
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 1fda3fe..a7e6036 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -31,6 +31,9 @@
#include <mpc86xx.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
+#include "mp.h"
+
+void setup_bats(void);
DECLARE_GLOBAL_DATA_PTR;
@@ -43,11 +46,11 @@ DECLARE_GLOBAL_DATA_PTR;
void cpu_init_f(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
@@ -56,57 +59,59 @@ void cpu_init_f(void)
init_laws();
#endif
+ setup_bats();
+
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
-#if defined(CFG_OR0_REMAP)
- memctl->or0 = CFG_OR0_REMAP;
+#if defined(CONFIG_SYS_OR0_REMAP)
+ memctl->or0 = CONFIG_SYS_OR0_REMAP;
#endif
-#if defined(CFG_OR1_REMAP)
- memctl->or1 = CFG_OR1_REMAP;
+#if defined(CONFIG_SYS_OR1_REMAP)
+ memctl->or1 = CONFIG_SYS_OR1_REMAP;
#endif
/* now restrict to preliminary range */
-#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
- memctl->br0 = CFG_BR0_PRELIM;
- memctl->or0 = CFG_OR0_PRELIM;
+#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
+ memctl->br0 = CONFIG_SYS_BR0_PRELIM;
+ memctl->or0 = CONFIG_SYS_OR0_PRELIM;
#endif
-#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
- memctl->or1 = CFG_OR1_PRELIM;
- memctl->br1 = CFG_BR1_PRELIM;
+#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
+ memctl->or1 = CONFIG_SYS_OR1_PRELIM;
+ memctl->br1 = CONFIG_SYS_BR1_PRELIM;
#endif
-#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
- memctl->or2 = CFG_OR2_PRELIM;
- memctl->br2 = CFG_BR2_PRELIM;
+#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
+ memctl->or2 = CONFIG_SYS_OR2_PRELIM;
+ memctl->br2 = CONFIG_SYS_BR2_PRELIM;
#endif
-#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
- memctl->or3 = CFG_OR3_PRELIM;
- memctl->br3 = CFG_BR3_PRELIM;
+#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
+ memctl->or3 = CONFIG_SYS_OR3_PRELIM;
+ memctl->br3 = CONFIG_SYS_BR3_PRELIM;
#endif
-#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
- memctl->or4 = CFG_OR4_PRELIM;
- memctl->br4 = CFG_BR4_PRELIM;
+#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
+ memctl->or4 = CONFIG_SYS_OR4_PRELIM;
+ memctl->br4 = CONFIG_SYS_BR4_PRELIM;
#endif
-#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
- memctl->or5 = CFG_OR5_PRELIM;
- memctl->br5 = CFG_BR5_PRELIM;
+#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
+ memctl->or5 = CONFIG_SYS_OR5_PRELIM;
+ memctl->br5 = CONFIG_SYS_BR5_PRELIM;
#endif
-#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
- memctl->or6 = CFG_OR6_PRELIM;
- memctl->br6 = CFG_BR6_PRELIM;
+#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
+ memctl->or6 = CONFIG_SYS_OR6_PRELIM;
+ memctl->br6 = CONFIG_SYS_BR6_PRELIM;
#endif
-#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
- memctl->or7 = CFG_OR7_PRELIM;
- memctl->br7 = CFG_BR7_PRELIM;
+#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
+ memctl->or7 = CONFIG_SYS_OR7_PRELIM;
+ memctl->br7 = CONFIG_SYS_BR7_PRELIM;
#endif
/* enable the timebase bit in HID0 */
@@ -121,28 +126,31 @@ void cpu_init_f(void)
*/
int cpu_init_r(void)
{
+#if (CONFIG_NUM_CPUS > 1)
+ setup_mp();
+#endif
return 0;
}
/* Set up BAT registers */
void setup_bats(void)
{
- write_bat(DBAT0, CFG_DBAT0U, CFG_DBAT0L);
- write_bat(IBAT0, CFG_IBAT0U, CFG_IBAT0L);
- write_bat(DBAT1, CFG_DBAT1U, CFG_DBAT1L);
- write_bat(IBAT1, CFG_IBAT1U, CFG_IBAT1L);
- write_bat(DBAT2, CFG_DBAT2U, CFG_DBAT2L);
- write_bat(IBAT2, CFG_IBAT2U, CFG_IBAT2L);
- write_bat(DBAT3, CFG_DBAT3U, CFG_DBAT3L);
- write_bat(IBAT3, CFG_IBAT3U, CFG_IBAT3L);
- write_bat(DBAT4, CFG_DBAT4U, CFG_DBAT4L);
- write_bat(IBAT4, CFG_IBAT4U, CFG_IBAT4L);
- write_bat(DBAT5, CFG_DBAT5U, CFG_DBAT5L);
- write_bat(IBAT5, CFG_IBAT5U, CFG_IBAT5L);
- write_bat(DBAT6, CFG_DBAT6U, CFG_DBAT6L);
- write_bat(IBAT6, CFG_IBAT6U, CFG_IBAT6L);
- write_bat(DBAT7, CFG_DBAT7U, CFG_DBAT7L);
- write_bat(IBAT7, CFG_IBAT7U, CFG_IBAT7L);
+ write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
+ write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
+ write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
+ write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
+ write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
+ write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L);
+ write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L);
+ write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L);
+ write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L);
+ write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L);
+ write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L);
+ write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L);
+ write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
+ write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
+ write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L);
+ write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L);
return;
}
diff --git a/cpu/mpc86xx/ddr-8641.c b/cpu/mpc86xx/ddr-8641.c
index f936182..51d0102 100644
--- a/cpu/mpc86xx/ddr-8641.c
+++ b/cpu/mpc86xx/ddr-8641.c
@@ -22,10 +22,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) {
case 0:
- ddr = (void *)CFG_MPC86xx_DDR_ADDR;
+ ddr = (void *)CONFIG_SYS_MPC86xx_DDR_ADDR;
break;
case 1:
- ddr = (void *)CFG_MPC86xx_DDR2_ADDR;
+ ddr = (void *)CONFIG_SYS_MPC86xx_DDR2_ADDR;
break;
default:
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c
index 12d9052..3adfad9 100644
--- a/cpu/mpc86xx/fdt.c
+++ b/cpu/mpc86xx/fdt.c
@@ -9,9 +9,17 @@
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include "mp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
void ft_cpu_setup(void *blob, bd_t *bd)
{
+#if (CONFIG_NUM_CPUS > 1)
+ int off;
+ u32 bootpg;
+#endif
+
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 4, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
@@ -28,8 +36,21 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_ethernet(blob);
#endif
-#ifdef CFG_NS16550
+#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "ns16550",
- "clock-frequency", CFG_NS16550_CLK, 1);
+ "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+#endif
+
+#if (CONFIG_NUM_CPUS > 1)
+ /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
+ if (gd->ram_size > 0xfffff000)
+ bootpg = 0xfff00000;
+ else
+ bootpg = gd->ram_size - (1024 * 1024);
+
+ /* Reserve the boot page so OSes dont use it */
+ off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
+ if (off < 0)
+ printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
#endif
}
diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c
index f16744b..c78fc72 100644
--- a/cpu/mpc86xx/interrupts.c
+++ b/cpu/mpc86xx/interrupts.c
@@ -35,78 +35,23 @@
#include <mpc86xx.h>
#include <command.h>
#include <asm/processor.h>
-#include <ppc_asm.tmpl>
-#include <watchdog.h>
-unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */
-unsigned long timestamp;
-
-
-static __inline__ unsigned long get_msr(void)
-{
- unsigned long msr;
-
- asm volatile ("mfmsr %0":"=r" (msr):);
-
- return msr;
-}
-
-static __inline__ void set_msr(unsigned long msr)
-{
- asm volatile ("mtmsr %0"::"r" (msr));
-}
-
-static __inline__ unsigned long get_dec(void)
-{
- unsigned long val;
-
- asm volatile ("mfdec %0":"=r" (val):);
-
- return val;
-}
-
-static __inline__ void set_dec(unsigned long val)
-{
- if (val)
- asm volatile ("mtdec %0"::"r" (val));
-}
-
-/* interrupt is not supported yet */
int interrupt_init_cpu(unsigned long *decrementer_count)
{
- return 0;
-}
-
-int interrupt_init(void)
-{
- int ret;
-
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- immr->im_pic.gcr = MPC86xx_PICGCR_RST;
- while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
- immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
-
- /* call cpu specific function from $(CPU)/interrupts.c */
- ret = interrupt_init_cpu(&decrementer_count);
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ volatile ccsr_pic_t *pic = &immr->im_pic;
- if (ret)
- return ret;
+ pic->gcr = MPC86xx_PICGCR_RST;
+ while (pic->gcr & MPC86xx_PICGCR_RST)
+ ;
+ pic->gcr = MPC86xx_PICGCR_MODE;
- decrementer_count = get_tbclk() / CFG_HZ;
+ *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
debug("interrupt init: tbclk() = %d MHz, decrementer_count = %ld\n",
(get_tbclk() / 1000000),
- decrementer_count);
-
- set_dec(decrementer_count);
-
- set_msr(get_msr() | MSR_EE);
-
- debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n",
- get_msr(),
- get_dec());
+ *decrementer_count);
#ifdef CONFIG_INTERRUPTS
- volatile ccsr_pic_t *pic = &immr->im_pic;
pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1);
@@ -132,25 +77,6 @@ int interrupt_init(void)
return 0;
}
-void enable_interrupts(void)
-{
- set_msr(get_msr() | MSR_EE);
-}
-
-/* returns flag if MSR_EE was set before */
-int disable_interrupts(void)
-{
- ulong msr = get_msr();
-
- set_msr(msr & ~MSR_EE);
- return (msr & MSR_EE) != 0;
-}
-
-void increment_timestamp(void)
-{
- timestamp++;
-}
-
/*
* timer_interrupt - gets called when the decrementer overflows,
* with interrupts disabled.
@@ -161,50 +87,9 @@ void timer_interrupt_cpu(struct pt_regs *regs)
/* nothing to do here */
}
-void timer_interrupt(struct pt_regs *regs)
-{
- /* call cpu specific function from $(CPU)/interrupts.c */
- timer_interrupt_cpu(regs);
-
- timestamp++;
-
- /* Restore Decrementer Count */
- set_dec(decrementer_count);
-
-#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
- if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0)
- WATCHDOG_RESET();
-#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
-
-#ifdef CONFIG_STATUS_LED
- status_led_tick(timestamp);
-#endif /* CONFIG_STATUS_LED */
-
-#ifdef CONFIG_SHOW_ACTIVITY
- board_show_activity(timestamp);
-#endif /* CONFIG_SHOW_ACTIVITY */
-
-}
-
-void reset_timer(void)
-{
- timestamp = 0;
-}
-
-ulong get_timer(ulong base)
-{
- return timestamp - base;
-}
-
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
/*
* Install and free a interrupt handler. Not implemented yet.
*/
-
void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
{
}
@@ -218,8 +103,6 @@ void irq_free_handler(int vec)
*/
int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- printf("\nInterrupt-unsupported:\n");
-
return 0;
}
diff --git a/cpu/mpc86xx/mp.c b/cpu/mpc86xx/mp.c
new file mode 100644
index 0000000..5014401
--- /dev/null
+++ b/cpu/mpc86xx/mp.c
@@ -0,0 +1,68 @@
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <ioports.h>
+#include <lmb.h>
+#include <asm/io.h>
+#include "mp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_NUM_CPUS > 1)
+void cpu_mp_lmb_reserve(struct lmb *lmb)
+{
+ u32 bootpg;
+
+ /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
+ if ((u64)gd->ram_size > 0xfffff000)
+ bootpg = 0xfff00000;
+ else
+ bootpg = gd->ram_size - (1024 * 1024);
+
+ /* tell u-boot we stole a page */
+ lmb_reserve(lmb, bootpg, 4096);
+}
+
+/*
+ * Copy the code for other cpus to execute into an
+ * aligned location accessible via BPTR
+ */
+void setup_mp(void)
+{
+ extern ulong __secondary_start_page;
+ ulong fixup = (ulong)&__secondary_start_page;
+ u32 bootpg;
+ u32 bootpg_va;
+
+ /*
+ * If we have 4G or more of memory, put the boot page at 4Gb-1M.
+ * Otherwise, put it at the very end of RAM.
+ */
+ if (gd->ram_size > 0xfffff000)
+ bootpg = 0xfff00000;
+ else
+ bootpg = gd->ram_size - (1024 * 1024);
+
+ if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
+ /* We're not covered by the DDR mapping, set up BAT */
+ write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
+ BATU_VS | BATU_VP,
+ bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
+ bootpg_va = CONFIG_SYS_SCRATCH_VA;
+ } else {
+ bootpg_va = bootpg;
+ }
+
+ memcpy((void *)bootpg_va, (void *)fixup, 4096);
+ flush_cache(bootpg_va, 4096);
+
+ /* remove the temporary BAT mapping */
+ if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
+ write_bat(DBAT7, 0, 0);
+
+ /* If the physical location of bootpg is not at fff00000, set BPTR */
+ if (bootpg != 0xfff00000)
+ out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
+ (bootpg >> 12));
+}
+#endif
diff --git a/cpu/mpc86xx/mp.h b/cpu/mpc86xx/mp.h
new file mode 100644
index 0000000..886e0c8
--- /dev/null
+++ b/cpu/mpc86xx/mp.h
@@ -0,0 +1,7 @@
+#ifndef __MPC86XX_MP_H_
+#define __MPC86XX_MP_H_
+
+void setup_mp(void);
+void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+#endif
diff --git a/cpu/mpc86xx/release.S b/cpu/mpc86xx/release.S
new file mode 100644
index 0000000..95efbb4
--- /dev/null
+++ b/cpu/mpc86xx/release.S
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2004, 2007, 2008 Freescale Semiconductor.
+ * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <mpc86xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/* If this is a multi-cpu system then we need to handle the
+ * 2nd cpu. The assumption is that the 2nd cpu is being
+ * held in boot holdoff mode until the 1st cpu unlocks it
+ * from Linux. We'll do some basic cpu init and then pass
+ * it to the Linux Reset Vector.
+ * Sri: Much of this initialization is not required. Linux
+ * rewrites the bats, and the sprs and also enables the L1 cache.
+ *
+ * Core 0 must copy this to a 1M aligned region and set BPTR
+ * to point to it.
+ */
+#if (CONFIG_NUM_CPUS > 1)
+ .align 12
+.globl __secondary_start_page
+__secondary_start_page:
+ .space 0x100 /* space over to reset vector loc */
+ mfspr r0, MSSCR0
+ andi. r0, r0, 0x0020
+ rlwinm r0,r0,27,31,31
+ mtspr PIR, r0
+
+ /* Invalidate BATs */
+ li r0, 0
+ mtspr IBAT0U, r0
+ mtspr IBAT1U, r0
+ mtspr IBAT2U, r0
+ mtspr IBAT3U, r0
+ mtspr IBAT4U, r0
+ mtspr IBAT5U, r0
+ mtspr IBAT6U, r0
+ mtspr IBAT7U, r0
+ isync
+ mtspr DBAT0U, r0
+ mtspr DBAT1U, r0
+ mtspr DBAT2U, r0
+ mtspr DBAT3U, r0
+ mtspr DBAT4U, r0
+ mtspr DBAT5U, r0
+ mtspr DBAT6U, r0
+ mtspr DBAT7U, r0
+ isync
+ sync
+
+ /* enable extended addressing */
+ mfspr r0, HID0
+ lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
+ ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
+ mtspr HID0, r0
+ sync
+ isync
+
+#ifdef CONFIG_SYS_L2
+ /* init the L2 cache */
+ addis r3, r0, L2_INIT@h
+ ori r3, r3, L2_INIT@l
+ sync
+ mtspr l2cr, r3
+#ifdef CONFIG_ALTIVEC
+ dssall
+#endif
+ /* invalidate the L2 cache */
+ mfspr r3, l2cr
+ rlwinm. r3, r3, 0, 0, 0
+ beq 1f
+
+ mfspr r3, l2cr
+ rlwinm r3, r3, 0, 1, 31
+
+#ifdef CONFIG_ALTIVEC
+ dssall
+#endif
+ sync
+ mtspr l2cr, r3
+ sync
+1: mfspr r3, l2cr
+ oris r3, r3, L2CR_L2I@h
+ mtspr l2cr, r3
+
+invl2:
+ mfspr r3, l2cr
+ andis. r3, r3, L2CR_L2I@h
+ bne invl2
+ sync
+#endif
+
+ /* enable and invalidate the data cache */
+ mfspr r3, HID0
+ li r5, HID0_DCFI|HID0_DLOCK
+ andc r3, r3, r5
+ mtspr HID0, r3 /* no invalidate, unlock */
+ ori r3, r3, HID0_DCE
+ ori r5, r3, HID0_DCFI
+ mtspr HID0, r5 /* enable + invalidate */
+ mtspr HID0, r3 /* enable */
+ sync
+#ifdef CONFIG_SYS_L2
+ sync
+ lis r3, L2_ENABLE@h
+ ori r3, r3, L2_ENABLE@l
+ mtspr l2cr, r3
+ isync
+ sync
+#endif
+
+ /* enable and invalidate the instruction cache*/
+ mfspr r3, HID0
+ li r5, HID0_ICFI|HID0_ILOCK
+ andc r3, r3, r5
+ ori r3, r3, HID0_ICE
+ ori r5, r3, HID0_ICFI
+ mtspr HID0, r5
+ mtspr HID0, r3
+ isync
+ sync
+
+ /* TBEN in HID0 */
+ mfspr r4, HID0
+ oris r4, r4, 0x0400
+ mtspr HID0, r4
+ sync
+ isync
+
+ /* MCP|SYNCBE|ABE in HID1 */
+ mfspr r4, HID1
+ oris r4, r4, 0x8000
+ ori r4, r4, 0x0C00
+ mtspr HID1, r4
+ sync
+ isync
+
+ lis r3, CONFIG_LINUX_RESET_VEC@h
+ ori r3, r3, CONFIG_LINUX_RESET_VEC@l
+ mtlr r3
+ blr
+
+ /* Never Returns, Running in Linux Now */
+#endif
diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c
index da5b58b..415ac9d 100644
--- a/cpu/mpc86xx/speed.c
+++ b/cpu/mpc86xx/speed.c
@@ -36,7 +36,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
void get_sys_info(sys_info_t *sysInfo)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint plat_ratio, e600_ratio;
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 03f2128..63cc8db 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -32,6 +32,7 @@
*/
#include <config.h>
#include <mpc86xx.h>
+#include <timestamp.h>
#include <version.h>
#include <ppc_asm.tmpl>
@@ -76,7 +77,7 @@
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
. = EXC_OFF_SYS_RESET
@@ -179,22 +180,12 @@ _end_of_vectors:
boot_cold:
boot_warm:
-
- /* if this is a multi-core system we need to check which cpu
- * this is, if it is not cpu 0 send the cpu to the linux reset
- * vector */
-#if (CONFIG_NUM_CPUS > 1)
- mfspr r0, MSSCR0
- andi. r0, r0, 0x0020
- rlwinm r0,r0,27,31,31
- mtspr PIR, r0
- beq 1f
-
- bl secondary_cpu_setup
-#endif
-
+ /*
+ * NOTE: Only Cpu 0 will ever come here. Other cores go to an
+ * address specified by the BPTR
+ */
1:
-#ifdef CFG_RAMBOOT
+#ifdef CONFIG_SYS_RAMBOOT
/* disable everything */
li r0, 0
mtspr HID0, r0
@@ -202,10 +193,14 @@ boot_warm:
mtmsr 0
#endif
+ /* Invalidate BATs */
bl invalidate_bats
sync
+ /* Invalidate all of TLB before MMU turn on */
+ bl clear_tlbs
+ sync
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
/* init the L2 cache */
lis r3, L2_INIT@h
ori r3, r3, L2_INIT@l
@@ -218,8 +213,8 @@ boot_warm:
/*
* Calculate absolute address in FLASH and jump there
*------------------------------------------------------*/
- lis r3, CFG_MONITOR_BASE@h
- ori r3, r3, CFG_MONITOR_BASE@l
+ lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
+ ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
@@ -245,9 +240,15 @@ in_flash:
*/
/* enable address translation */
- bl enable_addr_trans
- sync
+ mfmsr r5
+ ori r5, r5, (MSR_IR | MSR_DR)
+ lis r3,addr_trans_enabled@h
+ ori r3, r3, addr_trans_enabled@l
+ mtspr SPRN_SRR0,r3
+ mtspr SPRN_SRR1,r5
+ rfi
+addr_trans_enabled:
/* enable and invalidate the data cache */
/* bl l1dcache_enable */
bl dcache_enable
@@ -257,15 +258,19 @@ in_flash:
bl icache_enable
#endif
-#ifdef CFG_INIT_RAM_LOCK
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
bl lock_ram_in_cache
sync
#endif
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+ bl setup_ccsrbar
+#endif
+
/* set up the stack pointer in our newly created
* cache-ram (r1) */
- lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
- ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+ lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
+ ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
@@ -273,16 +278,6 @@ in_flash:
GET_GOT /* initialize GOT access */
- /* setup the rest of the bats */
- bl setup_bats
- bl clear_tlbs
- sync
-
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
- /* setup ccsrbar */
- bl setup_ccsrbar
-#endif
-
/* run low-level CPU init code (from Flash) */
bl cpu_init_f
sync
@@ -290,7 +285,7 @@ in_flash:
#ifdef RUN_DIAG
/* Load PX_AUX register address in r4 */
- lis r4, 0xf810
+ lis r4, PIXIS_BASE@h
ori r4, r4, 0x6
/* Load contents of PX_AUX in r3 bits 24 to 31*/
lbz r3, 0(r4)
@@ -308,8 +303,8 @@ in_flash:
stb r3, 0(r4)
/* Get the address to jump to in r3*/
- lis r3, CFG_DIAG_ADDR@h
- ori r3, r3, CFG_DIAG_ADDR@l
+ lis r3, CONFIG_SYS_DIAG_ADDR@h
+ ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
/* Load the LR with the branch address */
mtlr r3
@@ -362,45 +357,83 @@ invalidate_bats:
* early_bats:
*
* Set up bats needed early on - this is usually the BAT for the
- * stack-in-cache and the Flash
+ * stack-in-cache, the Flash, and CCSR space
*/
.globl early_bats
early_bats:
+ /* IBAT 3 */
+ lis r4, CONFIG_SYS_IBAT3L@h
+ ori r4, r4, CONFIG_SYS_IBAT3L@l
+ lis r3, CONFIG_SYS_IBAT3U@h
+ ori r3, r3, CONFIG_SYS_IBAT3U@l
+ mtspr IBAT3L, r4
+ mtspr IBAT3U, r3
+ isync
+
+ /* DBAT 3 */
+ lis r4, CONFIG_SYS_DBAT3L@h
+ ori r4, r4, CONFIG_SYS_DBAT3L@l
+ lis r3, CONFIG_SYS_DBAT3U@h
+ ori r3, r3, CONFIG_SYS_DBAT3U@l
+ mtspr DBAT3L, r4
+ mtspr DBAT3U, r3
+ isync
+
/* IBAT 5 */
- lis r4, CFG_IBAT5L@h
- ori r4, r4, CFG_IBAT5L@l
- lis r3, CFG_IBAT5U@h
- ori r3, r3, CFG_IBAT5U@l
+ lis r4, CONFIG_SYS_IBAT5L@h
+ ori r4, r4, CONFIG_SYS_IBAT5L@l
+ lis r3, CONFIG_SYS_IBAT5U@h
+ ori r3, r3, CONFIG_SYS_IBAT5U@l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
isync
/* DBAT 5 */
- lis r4, CFG_DBAT5L@h
- ori r4, r4, CFG_DBAT5L@l
- lis r3, CFG_DBAT5U@h
- ori r3, r3, CFG_DBAT5U@l
+ lis r4, CONFIG_SYS_DBAT5L@h
+ ori r4, r4, CONFIG_SYS_DBAT5L@l
+ lis r3, CONFIG_SYS_DBAT5U@h
+ ori r3, r3, CONFIG_SYS_DBAT5U@l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
isync
/* IBAT 6 */
- lis r4, CFG_IBAT6L@h
- ori r4, r4, CFG_IBAT6L@l
- lis r3, CFG_IBAT6U@h
- ori r3, r3, CFG_IBAT6U@l
+ lis r4, CONFIG_SYS_IBAT6L_EARLY@h
+ ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
+ lis r3, CONFIG_SYS_IBAT6U_EARLY@h
+ ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
isync
/* DBAT 6 */
- lis r4, CFG_DBAT6L@h
- ori r4, r4, CFG_DBAT6L@l
- lis r3, CFG_DBAT6U@h
- ori r3, r3, CFG_DBAT6U@l
+ lis r4, CONFIG_SYS_DBAT6L_EARLY@h
+ ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
+ lis r3, CONFIG_SYS_DBAT6U_EARLY@h
+ ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
isync
+
+#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+ /* IBAT 7 */
+ lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
+ ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
+ lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
+ ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
+ mtspr IBAT7L, r4
+ mtspr IBAT7U, r3
+ isync
+
+ /* DBAT 7 */
+ lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
+ ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
+ lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
+ ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
+ mtspr DBAT7L, r4
+ mtspr DBAT7U, r3
+ isync
+#endif
blr
.globl clear_tlbs
@@ -416,15 +449,6 @@ tlblp:
blt tlblp
blr
- .globl enable_addr_trans
-enable_addr_trans:
- /* enable address translation */
- mfmsr r5
- ori r5, r5, (MSR_IR | MSR_DR)
- mtmsr r5
- isync
- blr
-
.globl disable_addr_trans
disable_addr_trans:
/* disable address translation */
@@ -617,20 +641,19 @@ relocate_code:
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Global Data pointer */
- mr r2, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
@@ -644,16 +667,6 @@ relocate_code:
/*
* Now relocate code
*/
-#ifdef CONFIG_ECC
- bl board_relocate_rom
- sync
- mr r3, r10 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
- lwz r5, GOT(__init_end)
- sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
-#else
cmplw cr1,r3,r4
addi r0,r5,3
srwi. r0,r0,2
@@ -675,7 +688,6 @@ relocate_code:
3: lwzu r0,-4(r8)
stwu r0,-4(r7)
bdnz 3b
-#endif
/*
* Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line.
@@ -708,9 +720,6 @@ relocate_code:
blr
in_ram:
-#ifdef CONFIG_ECC
- bl board_init_ecc
-#endif
/*
* Relocation Function, r14 point to got2+0x8000
*
@@ -864,40 +873,43 @@ enable_ext_addr:
isync
blr
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
.globl setup_ccsrbar
setup_ccsrbar:
/* Special sequence needed to update CCSRBAR itself */
- lis r4, CFG_CCSRBAR_DEFAULT@h
- ori r4, r4, CFG_CCSRBAR_DEFAULT@l
-
- lis r5, CFG_CCSRBAR@h
- ori r5, r5, CFG_CCSRBAR@l
- srwi r6,r5,12
- stw r6, 0(r4)
+ lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
+ ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
+
+ lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
+ ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+ srwi r5,r5,12
+ li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+ rlwimi r5,r6,20,8,11
+ stw r5, 0(r4) /* Store physical value of CCSR */
isync
- lis r5, 0xffff
- ori r5,r5,0xf000
+ lis r5, TEXT_BASE@h
+ ori r5,r5,TEXT_BASE@l
lwz r5, 0(r5)
isync
- lis r3, CFG_CCSRBAR@h
- lwz r5, CFG_CCSRBAR@l(r3)
+ /* Use VA of CCSR to do read */
+ lis r3, CONFIG_SYS_CCSRBAR@h
+ lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
isync
blr
#endif
-#ifdef CFG_INIT_RAM_LOCK
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
lock_ram_in_cache:
/* Allocate Initial RAM in data cache.
*/
- lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
- li r2, ((CFG_INIT_RAM_END & ~31) + \
- (CFG_INIT_RAM_ADDR & 31) + 31) / 32
- mtctr r2
+ lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+ li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r4
1:
dcbz r0, r3
addi r3, r3, 32
@@ -928,11 +940,11 @@ lock_ram_in_cache:
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
- lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
- li r2, ((CFG_INIT_RAM_END & ~31) + \
- (CFG_INIT_RAM_ADDR & 31) + 31) / 32
- mtctr r2
+ lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+ li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r4
1: icbi r0, r3
addi r3, r3, 32
bdnz 1b
@@ -970,64 +982,3 @@ unlock_ram_in_cache:
blr
#endif
#endif
-
-/* If this is a multi-cpu system then we need to handle the
- * 2nd cpu. The assumption is that the 2nd cpu is being
- * held in boot holdoff mode until the 1st cpu unlocks it
- * from Linux. We'll do some basic cpu init and then pass
- * it to the Linux Reset Vector.
- * Sri: Much of this initialization is not required. Linux
- * rewrites the bats, and the sprs and also enables the L1 cache.
- */
-#if (CONFIG_NUM_CPUS > 1)
-.globl secondary_cpu_setup
-secondary_cpu_setup:
- /* Do only core setup on all cores except cpu0 */
- bl invalidate_bats
- sync
- bl enable_ext_addr
-
-#ifdef CFG_L2
- /* init the L2 cache */
- addis r3, r0, L2_INIT@h
- ori r3, r3, L2_INIT@l
- sync
- mtspr l2cr, r3
-#ifdef CONFIG_ALTIVEC
- dssall
-#endif
- /* invalidate the L2 cache */
- bl l2cache_invalidate
- sync
-#endif
-
- /* enable and invalidate the data cache */
- bl dcache_enable
- sync
-
- /* enable and invalidate the instruction cache*/
- bl icache_enable
- sync
-
- /* TBEN in HID0 */
- mfspr r4, HID0
- oris r4, r4, 0x0400
- mtspr HID0, r4
- sync
- isync
-
- /* MCP|SYNCBE|ABE in HID1 */
- mfspr r4, HID1
- oris r4, r4, 0x8000
- ori r4, r4, 0x0C00
- mtspr HID1, r4
- sync
- isync
-
- lis r3, CONFIG_LINUX_RESET_VEC@h
- ori r3, r3, CONFIG_LINUX_RESET_VEC@l
- mtlr r3
- blr
-
- /* Never Returns, Running in Linux Now */
-#endif
diff --git a/cpu/mpc8xx/commproc.c b/cpu/mpc8xx/commproc.c
index 07c763c..a87a0dc 100644
--- a/cpu/mpc8xx/commproc.c
+++ b/cpu/mpc8xx/commproc.c
@@ -26,7 +26,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
int dpram_init (void)
{
@@ -82,14 +82,14 @@ uint dpram_base_align (uint align)
return (gd->dp_alloc_base + mask) & ~mask;
}
-#endif /* CFG_ALLOC_DPRAM */
+#endif /* CONFIG_SYS_ALLOC_DPRAM */
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
void post_word_store (ulong a)
{
volatile void *save_addr =
- ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR;
+ ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR;
*(volatile ulong *) save_addr = a;
}
@@ -97,7 +97,7 @@ void post_word_store (ulong a)
ulong post_word_load (void)
{
volatile void *save_addr =
- ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR;
+ ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR;
return *(volatile ulong *) save_addr;
}
@@ -109,7 +109,7 @@ ulong post_word_load (void)
void bootcount_store (ulong a)
{
volatile ulong *save_addr =
- (volatile ulong *)( ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem +
+ (volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem +
CPM_BOOTCOUNT_ADDR );
save_addr[0] = a;
@@ -119,7 +119,7 @@ void bootcount_store (ulong a)
ulong bootcount_load (void)
{
volatile ulong *save_addr =
- (volatile ulong *)( ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem +
+ (volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem +
CPM_BOOTCOUNT_ADDR );
if (save_addr[1] != BOOTCOUNT_MAGIC)
diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c
index ec6a3fd..2eb848b 100644
--- a/cpu/mpc8xx/cpu.c
+++ b/cpu/mpc8xx/cpu.c
@@ -37,6 +37,8 @@
#include <watchdog.h>
#include <command.h>
#include <mpc8xx.h>
+#include <commproc.h>
+#include <netdev.h>
#include <asm/cache.h>
#if defined(CONFIG_OF_LIBFDT)
@@ -137,13 +139,13 @@ static int check_CPU (long clock, uint pvr, uint immr)
printf ("unknown M%s (0x%08x)", id_str, k);
-#if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX)
+#if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
strmhz (buf, clock),
- CFG_8xx_CPUCLK_MIN / 1000000,
- ((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
- CFG_8xx_CPUCLK_MAX / 1000000,
- ((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
+ CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
+ ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
+ CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
+ ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
);
#else
printf (" at %s MHz: ", strmhz (buf, clock));
@@ -375,7 +377,7 @@ int checkcpu (void)
int checkicache (void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
u32 cacheon = rd_ic_cst () & IDC_ENABLED;
@@ -422,7 +424,7 @@ int checkicache (void)
int checkdcache (void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
u32 cacheon = rd_dc_cst () & IDC_ENABLED;
@@ -462,7 +464,7 @@ void upmconfig (uint upm, uint * table, uint size)
{
uint i;
uint addr = 0;
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
for (i = 0; i < size; i++) {
@@ -480,7 +482,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong msr, addr;
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
@@ -495,16 +497,16 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
-#ifdef CFG_RESET_ADDRESS
- addr = CFG_RESET_ADDRESS;
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
- * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
+ * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
* - sizeof (ulong) is usually a valid address. Better pick an address
- * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
+ * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
* "(ulong)-1" used to be a good choice for many systems...
*/
- addr = CFG_MONITOR_BASE - sizeof (ulong);
+ addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
((void (*)(void)) addr) ();
return 1;
@@ -525,7 +527,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
disable_interrupts ();
/* make sure the watchdog is running */
- reset_8xx_watchdog ((immap_t *) CFG_IMMR);
+ reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
/* wait for watchdog reset */
while (1) {};
@@ -591,7 +593,7 @@ void watchdog_reset (void)
{
int re_enable = disable_interrupts ();
- reset_8xx_watchdog ((immap_t *) CFG_IMMR);
+ reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
if (re_enable)
enable_interrupts ();
}
@@ -635,3 +637,18 @@ void reset_8xx_watchdog (volatile immap_t * immr)
# endif /* CONFIG_LWMON */
}
#endif /* CONFIG_WATCHDOG */
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(SCC_ENET) && defined(CONFIG_CMD_NET)
+ scc_initialize(bis);
+#endif
+#if defined(FEC_ENET)
+ fec_initialize(bis);
+#endif
+ return 0;
+}
diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c
index fb3414a..eb0091b 100644
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -27,12 +27,12 @@
#include <mpc8xx.h>
#include <commproc.h>
-#if defined(CFG_RTCSC) || defined(CFG_RMDS)
+#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
DECLARE_GLOBAL_DATA_PTR;
#endif
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \
- defined(CFG_SMC_UCODE_PATCH)
+#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
+ defined(CONFIG_SYS_SMC_UCODE_PATCH)
void cpm_load_patch (volatile immap_t * immr);
#endif
@@ -47,7 +47,7 @@ void cpu_init_f (volatile immap_t * immr)
{
#ifndef CONFIG_MBX
volatile memctl8xx_t *memctl = &immr->im_memctl;
-# ifdef CFG_PLPRCR
+# ifdef CONFIG_SYS_PLPRCR
ulong mfmask;
# endif
#endif
@@ -55,7 +55,7 @@ void cpu_init_f (volatile immap_t * immr)
/* SYPCR - contains watchdog control (11-9) */
- immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
+ immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
#if defined(CONFIG_WATCHDOG)
reset_8xx_watchdog (immr);
@@ -63,27 +63,27 @@ void cpu_init_f (volatile immap_t * immr)
/* SIUMCR - contains debug pin configuration (11-6) */
#ifndef CONFIG_SVM_SC8xx
- immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
+ immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
#else
- immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
+ immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
#endif
/* initialize timebase status and control register (11-26) */
/* unlock TBSCRK */
immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
- immr->im_sit.sit_tbscr = CFG_TBSCR;
+ immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
/* initialize the PIT (11-31) */
immr->im_sitk.sitk_piscrk = KAPWR_KEY;
- immr->im_sit.sit_piscr = CFG_PISCR;
+ immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
/* System integration timers. Don't change EBDF! (15-27) */
immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
reg = immr->im_clkrst.car_sccr;
reg &= SCCR_MASK;
- reg |= CFG_SCCR;
+ reg |= CONFIG_SYS_SCCR;
immr->im_clkrst.car_sccr = reg;
/* PLL (CPU clock) settings (15-30) */
@@ -92,25 +92,25 @@ void cpu_init_f (volatile immap_t * immr)
#ifndef CONFIG_MBX /* MBX board does things different */
- /* If CFG_PLPRCR (set in the various *_config.h files) tries to
- * set the MF field, then just copy CFG_PLPRCR over car_plprcr,
- * otherwise OR in CFG_PLPRCR so we do not change the current MF
+ /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
+ * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
+ * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
* field value.
*
* For newer (starting MPC866) chips PLPRCR layout is different.
*/
-#ifdef CFG_PLPRCR
+#ifdef CONFIG_SYS_PLPRCR
if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
mfmask = PLPRCR_MFACT_MSK;
else
mfmask = PLPRCR_MF_MSK;
- if ((CFG_PLPRCR & mfmask) != 0)
- reg = CFG_PLPRCR; /* reset control bits */
+ if ((CONFIG_SYS_PLPRCR & mfmask) != 0)
+ reg = CONFIG_SYS_PLPRCR; /* reset control bits */
else {
reg = immr->im_clkrst.car_plprcr;
reg &= mfmask; /* isolate MF-related fields */
- reg |= CFG_PLPRCR; /* reset control bits */
+ reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
}
immr->im_clkrst.car_plprcr = reg;
#endif
@@ -130,20 +130,20 @@ void cpu_init_f (volatile immap_t * immr)
* when FLASH size has been determined
*
* Depending on the size of the memory region defined by
- * CFG_OR0_REMAP some boards (wide address mask) allow to map the
- * CFG_MONITOR_BASE, while others (narrower address mask) can't
- * map CFG_MONITOR_BASE.
+ * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
+ * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
+ * map CONFIG_SYS_MONITOR_BASE.
*
- * For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is
- * 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000.
+ * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
+ * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
*
* If BR0 wasn't loaded with address base 0xff000000, then BR0's
* base address remains as 0x00000000. However, the address mask
- * have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped
+ * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
* into the Bank0.
*
* This is why CONFIG_IVMS8 and similar boards must load BR0 with
- * CFG_BR0_PRELIM in advance.
+ * CONFIG_SYS_BR0_PRELIM in advance.
*
* [Thanks to Michael Liao for this explanation.
* I owe him a free beer. - wd]
@@ -165,60 +165,60 @@ void cpu_init_f (volatile immap_t * immr)
defined(CONFIG_SPC1920) || \
defined(CONFIG_SPD823TS)
- memctl->memc_br0 = CFG_BR0_PRELIM;
+ memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
#endif
-#if defined(CFG_OR0_REMAP)
- memctl->memc_or0 = CFG_OR0_REMAP;
+#if defined(CONFIG_SYS_OR0_REMAP)
+ memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
#endif
-#if defined(CFG_OR1_REMAP)
- memctl->memc_or1 = CFG_OR1_REMAP;
+#if defined(CONFIG_SYS_OR1_REMAP)
+ memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
#endif
-#if defined(CFG_OR5_REMAP)
- memctl->memc_or5 = CFG_OR5_REMAP;
+#if defined(CONFIG_SYS_OR5_REMAP)
+ memctl->memc_or5 = CONFIG_SYS_OR5_REMAP;
#endif
/* now restrict to preliminary range */
- memctl->memc_br0 = CFG_BR0_PRELIM;
- memctl->memc_or0 = CFG_OR0_PRELIM;
+ memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
+ memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
-#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
- memctl->memc_or1 = CFG_OR1_PRELIM;
- memctl->memc_br1 = CFG_BR1_PRELIM;
+#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
+ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+ memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
#endif
#if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
memctl->memc_br0 = 0;
#endif
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
- memctl->memc_or2 = CFG_OR2_PRELIM;
- memctl->memc_br2 = CFG_BR2_PRELIM;
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+ memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+ memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
#endif
-#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
- memctl->memc_or3 = CFG_OR3_PRELIM;
- memctl->memc_br3 = CFG_BR3_PRELIM;
+#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+ memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
#endif
-#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
- memctl->memc_or4 = CFG_OR4_PRELIM;
- memctl->memc_br4 = CFG_BR4_PRELIM;
+#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
+ memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+ memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
#endif
-#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
- memctl->memc_or5 = CFG_OR5_PRELIM;
- memctl->memc_br5 = CFG_BR5_PRELIM;
+#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
+ memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
+ memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
#endif
-#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
- memctl->memc_or6 = CFG_OR6_PRELIM;
- memctl->memc_br6 = CFG_BR6_PRELIM;
+#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
+ memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
+ memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
#endif
-#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
- memctl->memc_or7 = CFG_OR7_PRELIM;
- memctl->memc_br7 = CFG_BR7_PRELIM;
+#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
+ memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
+ memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
#endif
#endif /* ! CONFIG_MBX */
@@ -245,17 +245,17 @@ void cpu_init_f (volatile immap_t * immr)
rpxclassic_init ();
#endif
-#if defined(CONFIG_RPXLITE) && defined(CFG_ENV_IS_IN_NVRAM)
+#if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM)
rpxlite_init ();
#endif
-#ifdef CFG_RCCR /* must be done before cpm_load_patch() */
+#ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */
/* write config value */
- immr->im_cpm.cp_rccr = CFG_RCCR;
+ immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
#endif
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \
- defined(CFG_SMC_UCODE_PATCH)
+#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
+ defined(CONFIG_SYS_SMC_UCODE_PATCH)
cpm_load_patch (immr); /* load mpc8xx microcode patch */
#endif
}
@@ -265,21 +265,21 @@ void cpu_init_f (volatile immap_t * immr)
*/
int cpu_init_r (void)
{
-#if defined(CFG_RTCSC) || defined(CFG_RMDS)
+#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
bd_t *bd = gd->bd;
volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
#endif
-#ifdef CFG_RTCSC
+#ifdef CONFIG_SYS_RTCSC
/* Unlock RTSC register */
immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
/* write config value */
- immr->im_sit.sit_rtcsc = CFG_RTCSC;
+ immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC;
#endif
-#ifdef CFG_RMDS
+#ifdef CONFIG_SYS_RMDS
/* write config value */
- immr->im_cpm.cp_rmds = CFG_RMDS;
+ immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS;
#endif
return (0);
}
diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index 37eb481..89c1ff9 100644
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
/* define WANT_MII when MII support is required */
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
#define WANT_MII
#else
#undef WANT_MII
@@ -59,7 +59,7 @@ DECLARE_GLOBAL_DATA_PTR;
#error RMII support is unusable without a working PHY.
#endif
-#ifdef CFG_DISCOVER_PHY
+#ifdef CONFIG_SYS_DISCOVER_PHY
static int mii_discover_phy(struct eth_device *dev);
#endif
@@ -197,7 +197,7 @@ static int fec_send(struct eth_device* dev, volatile void *packet, int length)
{
int j, rc;
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
+ volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
/* section 16.9.23.3
* Wait for ready
@@ -248,7 +248,7 @@ static int fec_recv (struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
volatile fec_t *fecp =
- (volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
+ (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
int length;
for (;;) {
@@ -339,7 +339,7 @@ static inline void fec_10Mbps(struct eth_device *dev)
if ((unsigned int)fecidx >= 2)
hang();
- ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |= mask;
+ ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask;
}
static inline void fec_100Mbps(struct eth_device *dev)
@@ -351,7 +351,7 @@ static inline void fec_100Mbps(struct eth_device *dev)
if ((unsigned int)fecidx >= 2)
hang();
- ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~mask;
+ ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
}
#endif
@@ -359,7 +359,7 @@ static inline void fec_100Mbps(struct eth_device *dev)
static inline void fec_full_duplex(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
+ volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
@@ -368,7 +368,7 @@ static inline void fec_full_duplex(struct eth_device *dev)
static inline void fec_half_duplex(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
+ volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
@@ -377,7 +377,7 @@ static inline void fec_half_duplex(struct eth_device *dev)
static void fec_pin_init(int fecidx)
{
bd_t *bd = gd->bd;
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile fec_t *fecp;
/*
@@ -398,7 +398,7 @@ static void fec_pin_init(int fecidx)
* * the MII management interface clock must be less than or equal
* * to 2.5 MHz.
* * This MDC frequency is equal to system clock / (2 * MII_SPEED).
- * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
+ * * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
*
* All MII configuration is done via FEC1 registers:
*/
@@ -474,7 +474,7 @@ static void fec_pin_init(int fecidx)
* Configure port A for MII.
*/
-#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY)
/*
* On the ICU862 board the MII-MDC pin is routed to PD8 pin
@@ -569,9 +569,9 @@ static int fec_reset(volatile fec_t *fecp)
static int fec_init (struct eth_device *dev, bd_t * bd)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile fec_t *fecp =
- (volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
+ (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
int i;
if (efis->ether_index == 0) {
@@ -657,7 +657,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
txIdx = 0;
if (!rtx) {
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
dpram_alloc_align (sizeof (RTXBD), 8));
#else
@@ -721,7 +721,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
if (efis->phy_addr == -1) {
-#ifdef CFG_DISCOVER_PHY
+#ifdef CONFIG_SYS_DISCOVER_PHY
/*
* wait for the PHY to wake up after reset
*/
@@ -772,7 +772,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
static void fec_halt(struct eth_device* dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
+ volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
int i;
/* avoid halt if initialized; mii gets stuck otherwise */
@@ -801,7 +801,7 @@ static void fec_halt(struct eth_device* dev)
efis->initialized = 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/* Make MII read/write commands for the FEC.
*/
@@ -846,7 +846,7 @@ mii_send(uint mii_cmd)
volatile fec_t *ep;
int cnt;
- ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec);
+ ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec);
ep->fec_mii_data = mii_cmd; /* command to phy */
@@ -868,7 +868,7 @@ mii_send(uint mii_cmd)
}
#endif
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
static int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -937,7 +937,7 @@ static int mii_discover_phy(struct eth_device *dev)
}
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
@@ -948,7 +948,7 @@ static int mii_discover_phy(struct eth_device *dev)
*/
static void __mii_init(void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
if (fec_reset(fecp) < 0)
diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c
index f05b666..338caba 100644
--- a/cpu/mpc8xx/i2c.c
+++ b/cpu/mpc8xx/i2c.c
@@ -42,19 +42,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* define to enable debug messages */
#undef DEBUG_I2C
-/*-----------------------------------------------------------------------
- * Set default values
- */
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED 50000
-#endif
-
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE 0xFE
-#endif
-/*-----------------------------------------------------------------------
- */
-
/* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
#define TOUT_LOOP 1000000
@@ -162,7 +149,7 @@ i2c_roundrate(int hz, int speed, int filter, int modval,
static int
i2c_setrate (int hz, int speed)
{
- immap_t *immap = (immap_t *) CFG_IMMR;
+ immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
int brgval,
modval, /* 0-3 */
@@ -207,7 +194,7 @@ i2c_setrate (int hz, int speed)
void
i2c_init(int speed, int slaveaddr)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
@@ -215,21 +202,21 @@ i2c_init(int speed, int slaveaddr)
volatile I2C_BD *rxbd, *txbd;
uint dpaddr;
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
/* call board specific i2c bus reset routine before accessing the */
/* environment, which might be in a chip on that bus. For details */
/* about this problem see doc/I2C_Edge_Conditions. */
i2c_init_board();
#endif
-#ifdef CFG_I2C_UCODE_PATCH
+#ifdef CONFIG_SYS_I2C_UCODE_PATCH
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
#else
/* Disable relocation */
iip->iic_rpbase = 0;
#endif
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = iip->iic_rbase;
if (dpaddr == 0) {
/* need to allocate dual port ram */
@@ -269,7 +256,7 @@ i2c_init(int speed, int slaveaddr)
* divide BRGCLK by 1)
*/
PRINTD(("[I2C] Setting rate...\n"));
- i2c_setrate (gd->cpu_clk, CFG_I2C_SPEED) ;
+ i2c_setrate (gd->cpu_clk, CONFIG_SYS_I2C_SPEED) ;
/* Set I2C controller in master mode */
i2c->i2c_i2com = 0x01;
@@ -295,7 +282,7 @@ i2c_init(int speed, int slaveaddr)
/* Set maximum receive size. */
iip->iic_mrblr = I2C_RXTX_LEN;
-#ifdef CFG_I2C_UCODE_PATCH
+#ifdef CONFIG_SYS_I2C_UCODE_PATCH
/*
* Initialize required parameters if using microcode patch.
*/
@@ -318,13 +305,13 @@ i2c_init(int speed, int slaveaddr)
static void
i2c_newio(i2c_state_t *state)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
PRINTD(("[I2C] i2c_newio\n"));
-#ifdef CFG_I2C_UCODE_PATCH
+#ifdef CONFIG_SYS_I2C_UCODE_PATCH
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
#endif
state->rx_idx = 0;
@@ -492,7 +479,7 @@ i2c_receive(i2c_state_t *state,
static int i2c_doio(i2c_state_t *state)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
@@ -501,7 +488,7 @@ static int i2c_doio(i2c_state_t *state)
PRINTD(("[I2C] i2c_doio\n"));
-#ifdef CFG_I2C_UCODE_PATCH
+#ifdef CONFIG_SYS_I2C_UCODE_PATCH
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
#endif
@@ -593,7 +580,7 @@ int i2c_probe(uchar chip)
int rc;
uchar buf[1];
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
i2c_newio(&state);
@@ -628,7 +615,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones like
* Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
@@ -639,7 +626,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
* be one byte because the extra address bits are hidden in the
* chip address.
*/
- chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
i2c_newio(&state);
@@ -678,7 +665,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones like
* Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
@@ -689,7 +676,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
* be one byte because the extra address bits are hidden in the
* chip address.
*/
- chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
i2c_newio(&state);
@@ -717,24 +704,4 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
return 0;
}
-uchar
-i2c_reg_read(uchar i2c_addr, uchar reg)
-{
- uchar buf;
-
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
-
- i2c_read(i2c_addr, reg, 1, &buf, 1);
-
- return (buf);
-}
-
-void
-i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
-{
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
-
- i2c_write(i2c_addr, reg, 1, &val, 1);
-}
-
#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/mpc8xx/interrupts.c b/cpu/mpc8xx/interrupts.c
index 20e7012..5daa6b2 100644
--- a/cpu/mpc8xx/interrupts.c
+++ b/cpu/mpc8xx/interrupts.c
@@ -47,9 +47,9 @@ static void cpm_interrupt (void *regs);
int interrupt_init_cpu (unsigned *decrementer_count)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- *decrementer_count = get_tbclk () / CFG_HZ;
+ *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
/* disable all interrupts */
immr->im_siu_conf.sc_simask = 0;
@@ -67,7 +67,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
*/
void external_interrupt (struct pt_regs *regs)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int irq;
ulong simask, newmask;
ulong vec, v_bit;
@@ -124,7 +124,7 @@ void external_interrupt (struct pt_regs *regs)
*/
static void cpm_interrupt (void *regs)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
uint vec;
/*
@@ -165,7 +165,7 @@ static void cpm_error_interrupt (void *dummy)
void irq_install_handler (int vec, interrupt_handler_t * handler,
void *arg)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
if ((vec & CPMVEC_OFFSET) != 0) {
/* CPM interrupt */
@@ -202,7 +202,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler,
void irq_free_handler (int vec)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
if ((vec & CPMVEC_OFFSET) != 0) {
/* CPM interrupt */
@@ -230,7 +230,7 @@ void irq_free_handler (int vec)
static void cpm_interrupt_init (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
/*
* Initialize the CPM interrupt controller.
@@ -266,7 +266,7 @@ static void cpm_interrupt_init (void)
*/
void timer_interrupt_cpu (struct pt_regs *regs)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
#if 0
printf ("*** Timer Interrupt *** ");
diff --git a/cpu/mpc8xx/kgdb.S b/cpu/mpc8xx/kgdb.S
index 812baa3..2cc8fe6 100644
--- a/cpu/mpc8xx/kgdb.S
+++ b/cpu/mpc8xx/kgdb.S
@@ -52,21 +52,21 @@ kgdb_flush_cache_all:
.globl kgdb_flush_cache_range
kgdb_flush_cache_range:
- li r5,CFG_CACHELINE_SIZE-1
+ li r5,CONFIG_SYS_CACHELINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
- srwi. r4,r4,CFG_CACHELINE_SHIFT
+ srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
beqlr
mtctr r4
mr r6,r3
1: dcbst 0,r3
- addi r3,r3,CFG_CACHELINE_SIZE
+ addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
sync /* wait for dcbst's to get to ram */
mtctr r4
2: icbi 0,r6
- addi r6,r6,CFG_CACHELINE_SIZE
+ addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
bdnz 2b
SYNC
blr
diff --git a/cpu/mpc8xx/lcd.c b/cpu/mpc8xx/lcd.c
index 3c64a9b..4474e24 100644
--- a/cpu/mpc8xx/lcd.c
+++ b/cpu/mpc8xx/lcd.c
@@ -63,7 +63,7 @@
#define LCD_BPP LCD_COLOR4
vidinfo_t panel_info = {
- 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
+ 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0
/* wbl, vpw, lcdac, wbf */
};
@@ -76,7 +76,7 @@ vidinfo_t panel_info = {
* Hitachi SP19X001-. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 154, 116, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
+ 640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
/* wbl, vpw, lcdac, wbf */
};
@@ -89,7 +89,7 @@ vidinfo_t panel_info = {
* NEC NL6448AC33-18. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 144, 2, 0, 33
/* wbl, vpw, lcdac, wbf */
};
@@ -101,7 +101,7 @@ vidinfo_t panel_info = {
* NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 144, 2, 0, 33
/* wbl, vpw, lcdac, wbf */
};
@@ -113,7 +113,7 @@ vidinfo_t panel_info = {
* NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 212, 158, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 144, 2, 0, 33
/* wbl, vpw, lcdac, wbf */
};
@@ -125,7 +125,7 @@ vidinfo_t panel_info = {
* SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW,
+ 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
3, 0, 0, 1, 1, 25, 1, 0, 33
/* wbl, vpw, lcdac, wbf */
};
@@ -138,7 +138,7 @@ vidinfo_t panel_info = {
* not sure what it is.......
*/
vidinfo_t panel_info = {
- 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
+ 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 15, 4, 0, 3
};
#endif /* CONFIG_SHARP_16x9 */
@@ -152,7 +152,7 @@ vidinfo_t panel_info = {
#define LCD_DF 12
vidinfo_t panel_info = {
- 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 15, 4, 0, 3
/* wbl, vpw, lcdac, wbf */
};
@@ -165,7 +165,7 @@ vidinfo_t panel_info = {
* Sharp LQ64D341 display, 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 128, 16, 0, 32
/* wbl, vpw, lcdac, wbf */
};
@@ -176,7 +176,7 @@ vidinfo_t panel_info = {
* Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 400, 240, 143, 79, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
+ 400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 248, 4, 0, 35
/* wbl, vpw, lcdac, wbf */
};
@@ -188,7 +188,7 @@ vidinfo_t panel_info = {
* Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 171, 129, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW,
+ 640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
3, 0, 0, 1, 1, 160, 3, 0, 48
/* wbl, vpw, lcdac, wbf */
};
@@ -201,7 +201,7 @@ vidinfo_t panel_info = {
* HLD1045 display, 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 160, 3, 0, 48
/* wbl, vpw, lcdac, wbf */
};
@@ -213,7 +213,7 @@ vidinfo_t panel_info = {
* Prime View V16C6448AC
*/
vidinfo_t panel_info = {
- 640, 480, 130, 98, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 144, 2, 0, 35
/* wbl, vpw, lcdac, wbf */
};
@@ -235,7 +235,7 @@ vidinfo_t panel_info = {
/* 1 - 4 grey levels, 2 bpp */
/* 2 - 16 grey levels, 4 bpp */
vidinfo_t panel_info = {
- 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW,
+ 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
};
#endif /* CONFIG_OPTREX_BW */
@@ -249,7 +249,7 @@ vidinfo_t panel_info = {
#define LCD_DF 10
vidinfo_t panel_info = {
- 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW,
+ 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0
};
#endif
@@ -307,7 +307,7 @@ ulong calc_fbsize (void)
void lcd_ctrl_init (void *lcdbase)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile lcd823_t *lcdp = &immr->im_lcd;
uint lccrtmp;
@@ -320,7 +320,7 @@ void lcd_ctrl_init (void *lcdbase)
#ifdef CONFIG_RPXLITE
/* This is special for RPXlite_DW Software Development Platform **[Sam]** */
- panel_info.vl_dp = CFG_LOW;
+ panel_info.vl_dp = CONFIG_SYS_LOW;
#endif
lccrtmp = LCDBIT (LCCR_BNUM_BIT,
@@ -436,14 +436,14 @@ void lcd_ctrl_init (void *lcdbase)
static void
lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(immr->im_cpm);
unsigned short colreg, *cmap_ptr;
cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
colreg = *cmap_ptr;
-#ifdef CFG_INVERT_COLORS
+#ifdef CONFIG_SYS_INVERT_COLORS
colreg ^= 0x0FFF;
#endif
@@ -459,7 +459,7 @@ lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
void
lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(immr->im_cpm);
unsigned short colreg, *cmap_ptr;
@@ -468,7 +468,7 @@ lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
colreg = ((red & 0x0F) << 8) |
((green & 0x0F) << 4) |
(blue & 0x0F) ;
-#ifdef CFG_INVERT_COLORS
+#ifdef CONFIG_SYS_INVERT_COLORS
colreg ^= 0x0FFF;
#endif
*cmap_ptr = colreg;
@@ -486,7 +486,7 @@ lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
static
void lcd_initcolregs (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(immr->im_cpm);
ushort regno;
@@ -501,7 +501,7 @@ void lcd_initcolregs (void)
void lcd_enable (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile lcd823_t *lcdp = &immr->im_lcd;
/* Enable the LCD panel */
@@ -521,7 +521,7 @@ void lcd_enable (void)
#if defined(CONFIG_LWMON)
{ uchar c = pic_read (0x60);
-#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CFG_POST_SYSMON)
+#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
/* Enable LCD later in sysmon test, only if temperature is OK */
#else
c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */
@@ -586,7 +586,7 @@ void lcd_enable (void)
#if defined (CONFIG_RBC823)
void lcd_disable (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile lcd823_t *lcdp = &immr->im_lcd;
#if defined(CONFIG_LWMON)
diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c
index 09a3db1..effb967 100644
--- a/cpu/mpc8xx/scc.c
+++ b/cpu/mpc8xx/scc.c
@@ -191,7 +191,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
int i;
scc_enet_t *pram_ptr;
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
#if defined(CONFIG_LWMON)
reset_phy();
@@ -215,12 +215,14 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
rxIdx = 0;
txIdx = 0;
-#ifdef CFG_ALLOC_DPRAM
- rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
- dpram_alloc_align (sizeof (RTXBD), 8));
+ if (!rtx) {
+#ifdef CONFIG_SYS_ALLOC_DPRAM
+ rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
+ dpram_alloc_align (sizeof (RTXBD), 8));
#else
- rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
-#endif /* 0 */
+ rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
+#endif
+ }
#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
/* Configure port A pins for Txd and Rxd.
@@ -550,7 +552,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
static void scc_halt (struct eth_device *dev)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &=
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
@@ -561,7 +563,7 @@ static void scc_halt (struct eth_device *dev)
#if 0
void restart (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c
index ad02299..bd90dcd 100644
--- a/cpu/mpc8xx/serial.c
+++ b/cpu/mpc8xx/serial.c
@@ -70,12 +70,12 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
if(divisor/16>0x1000) {
- /* bad divisor, assume 50Mhz clock and 9600 baud */
+ /* bad divisor, assume 50MHz clock and 9600 baud */
divisor=(50*1000*1000 + 8*9600)/16/9600;
}
-#ifdef CFG_BRGCLK_PRESCALE
- divisor /= CFG_BRGCLK_PRESCALE;
+#ifdef CONFIG_SYS_BRGCLK_PRESCALE
+ divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
#endif
if(divisor<=0x1000) {
@@ -94,7 +94,7 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
static void smc_setbrg (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
/* Set up the baud rate generator.
@@ -110,7 +110,7 @@ static void smc_setbrg (void)
static int smc_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile smc_t *sp;
volatile smc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -124,7 +124,7 @@ static int smc_init (void)
sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
-#ifdef CFG_SMC_UCODE_PATCH
+#ifdef CONFIG_SYS_SMC_UCODE_PATCH
up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
#else
/* Disable relocation */
@@ -140,15 +140,15 @@ static int smc_init (void)
im->im_siu_conf.sc_sdcr = 1;
/* clear error conditions */
-#ifdef CFG_SDSR
- im->im_sdma.sdma_sdsr = CFG_SDSR;
+#ifdef CONFIG_SYS_SDSR
+ im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
#else
im->im_sdma.sdma_sdsr = 0x83;
#endif
/* clear SDMA interrupt mask */
-#ifdef CFG_SDMR
- im->im_sdma.sdma_sdmr = CFG_SDMR;
+#ifdef CONFIG_SYS_SDMR
+ im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
#else
im->im_sdma.sdma_sdmr = 0x00;
#endif
@@ -193,7 +193,7 @@ static int smc_init (void)
* the buffer descriptors.
*/
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
#else
dpaddr = CPM_SERIAL_BASE ;
@@ -218,7 +218,7 @@ static int smc_init (void)
up->smc_tbase = dpaddr+sizeof(cbd_t);
up->smc_rfcr = SMC_EB;
up->smc_tfcr = SMC_EB;
-#if defined (CFG_SMC_UCODE_PATCH)
+#if defined (CONFIG_SYS_SMC_UCODE_PATCH)
up->smc_rbptr = up->smc_rbase;
up->smc_tbptr = up->smc_tbase;
up->smc_rstate = 0;
@@ -239,11 +239,11 @@ static int smc_init (void)
sp->smc_smcm = 0;
sp->smc_smce = 0xff;
-#ifdef CFG_SPC1920_SMC1_CLK4
+#ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
/* clock source is PLD */
/* set freq to 19200 Baud */
- *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0x3;
+ *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3;
/* configure clk4 as input */
im->im_ioport.iop_pdpar |= 0x800;
im->im_ioport.iop_pddir &= ~0x800;
@@ -288,7 +288,7 @@ smc_putc(const char c)
volatile cbd_t *tbdf;
volatile char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
#ifdef CONFIG_MODEM_SUPPORT
@@ -300,7 +300,7 @@ smc_putc(const char c)
smc_putc ('\r');
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-#ifdef CFG_SMC_UCODE_PATCH
+#ifdef CONFIG_SYS_SMC_UCODE_PATCH
up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
@@ -336,12 +336,12 @@ smc_getc(void)
volatile cbd_t *rbdf;
volatile unsigned char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
unsigned char c;
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-#ifdef CFG_SMC_UCODE_PATCH
+#ifdef CONFIG_SYS_SMC_UCODE_PATCH
up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
@@ -365,11 +365,11 @@ smc_tstc(void)
{
volatile cbd_t *rbdf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-#ifdef CFG_SMC_UCODE_PATCH
+#ifdef CONFIG_SYS_SMC_UCODE_PATCH
up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
@@ -398,7 +398,7 @@ struct serial_device serial_smc_device =
static void
scc_setbrg (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
/* Set up the baud rate generator.
@@ -414,7 +414,7 @@ scc_setbrg (void)
static int scc_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -474,7 +474,7 @@ static int scc_init (void)
/* Allocate space for two buffer descriptors in the DP ram.
*/
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
#else
dpaddr = CPM_SERIAL2_BASE ;
@@ -580,7 +580,7 @@ scc_putc(const char c)
volatile cbd_t *tbdf;
volatile char *buf;
volatile scc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
#ifdef CONFIG_MODEM_SUPPORT
@@ -625,7 +625,7 @@ scc_getc(void)
volatile cbd_t *rbdf;
volatile unsigned char *buf;
volatile scc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
unsigned char c;
@@ -651,7 +651,7 @@ scc_tstc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index 070babc..f309f29 100644
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG)
+#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CONFIG_SYS_MEASURE_CPUCLK) || defined(DEBUG)
#define PITC_SHIFT 16
#define PITR_SHIFT 16
@@ -87,12 +87,12 @@ static __inline__ void set_msr(unsigned long msr)
unsigned long measure_gclk(void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
ulong timer2_val;
ulong msr_val;
-#ifdef CFG_8XX_XIN
+#ifdef CONFIG_SYS_8XX_XIN
/* dont use OSCM, only use EXTCLK/512 */
immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
#else
@@ -137,7 +137,7 @@ unsigned long measure_gclk(void)
immr->im_sit.sit_pitc = SPEED_PITC_INIT;
immr->im_sitk.sitk_piscrk = KAPWR_KEY;
- immr->im_sit.sit_piscr = CFG_PISCR;
+ immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
/*
* Start measurement - disable interrupts, just in case
@@ -164,9 +164,9 @@ unsigned long measure_gclk(void)
timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
immr->im_sit.sit_piscr &= ~PISCR_PTE;
-#if defined(CFG_8XX_XIN)
+#if defined(CONFIG_SYS_8XX_XIN)
/* not using OSCM, using XIN, so scale appropriately */
- return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
+ return (((timer2_val + 2) / 4) * (CONFIG_SYS_8XX_XIN/512))/8192 * 100000L;
#else
return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
#endif
@@ -261,7 +261,7 @@ static long init_pll_866 (long clk);
*/
int get_clocks_866 (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
char tmp[64];
long cpuclk = 0;
long sccr_reg;
@@ -269,11 +269,11 @@ int get_clocks_866 (void)
if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
- if ((CFG_8xx_CPUCLK_MIN > cpuclk) || (CFG_8xx_CPUCLK_MAX < cpuclk))
+ if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk))
cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
gd->cpu_clk = init_pll_866 (cpuclk);
-#if defined(CFG_MEASURE_CPUCLK)
+#if defined(CONFIG_SYS_MEASURE_CPUCLK)
gd->cpu_clk = measure_gclk ();
#endif
@@ -301,12 +301,12 @@ int get_clocks_866 (void)
*/
int sdram_adjust_866 (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
long mamr;
mamr = immr->im_memctl.memc_mamr;
mamr &= ~MAMR_PTA_MSK;
- mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+ mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
immr->im_memctl.memc_mamr = mamr;
return (0);
@@ -320,7 +320,7 @@ static long init_pll_866 (long clk)
{
extern void plprcr_write_866 (long);
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
long n, plprcr;
char mfi, mfn, mfd, s, pdf;
long step_mfi, step_mfn;
@@ -394,13 +394,13 @@ static long init_pll_866 (long clk)
*/
int adjust_sdram_tbs_8xx (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
long mamr;
long sccr;
mamr = immr->im_memctl.memc_mamr;
mamr &= ~MAMR_PTA_MSK;
- mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+ mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
immr->im_memctl.memc_mamr = mamr;
if (gd->cpu_clk < 67000000) {
diff --git a/cpu/mpc8xx/spi.c b/cpu/mpc8xx/spi.c
index e318ed0..b2ac23e 100644
--- a/cpu/mpc8xx/spi.c
+++ b/cpu/mpc8xx/spi.c
@@ -41,7 +41,7 @@
#include <post.h>
#include <serial.h>
-#if (defined(CONFIG_SPI)) || (CONFIG_POST & CFG_POST_SPI)
+#if (defined(CONFIG_SPI)) || (CONFIG_POST & CONFIG_SYS_POST_SPI)
/* Warning:
* You cannot enable DEBUG for early system initalization, i. e. when
@@ -64,8 +64,8 @@
* The value 0xb00 makes it far enough from the start of the data
* area (as well as from the stack pointer).
* --------------------------------------------------------------- */
-#ifndef CFG_SPI_INIT_OFFSET
-#define CFG_SPI_INIT_OFFSET 0xB00
+#ifndef CONFIG_SYS_SPI_INIT_OFFSET
+#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
#endif
#ifdef DEBUG
@@ -118,11 +118,11 @@ ssize_t spi_xfer (size_t);
* Initially we place the RX and TX buffers at a fixed location in DPRAM!
* ---------------------------------------------------------------------- */
static uchar *rxbuf =
- (uchar *)&((cpm8xx_t *)&((immap_t *)CFG_IMMR)->im_cpm)->cp_dpmem
- [CFG_SPI_INIT_OFFSET];
+ (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
+ [CONFIG_SYS_SPI_INIT_OFFSET];
static uchar *txbuf =
- (uchar *)&((cpm8xx_t *)&((immap_t *)CFG_IMMR)->im_cpm)->cp_dpmem
- [CFG_SPI_INIT_OFFSET+MAX_BUFFER];
+ (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
+ [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
/* **************************************************************************
*
@@ -144,12 +144,12 @@ void spi_init_f (void)
volatile iop8xx_t *iop;
volatile cbd_t *tbdf, *rbdf;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
cpi = (cpic8xx_t *)&immr->im_cpic;
iop = (iop8xx_t *) &immr->im_ioport;
cp = (cpm8xx_t *) &immr->im_cpm;
-#ifdef CFG_SPI_UCODE_PATCH
+#ifdef CONFIG_SYS_SPI_UCODE_PATCH
spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
#else
spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
@@ -210,7 +210,7 @@ void spi_init_f (void)
/* Allocate space for one transmit and one receive buffer
* descriptor in the DP ram
*/
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2, 8);
#else
dpaddr = CPM_SPI_BASE;
@@ -234,7 +234,7 @@ void spi_init_f (void)
spi->spi_tbptr = spi->spi_tbase;
/* 4 */
-#ifdef CFG_SPI_UCODE_PATCH
+#ifdef CONFIG_SYS_SPI_UCODE_PATCH
/*
* Initialize required parameters if using microcode patch.
*/
@@ -247,7 +247,7 @@ void spi_init_f (void)
cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG;
while (cp->cp_cpcr & CPM_CR_FLG)
;
-#endif /* CFG_SPI_UCODE_PATCH */
+#endif /* CONFIG_SYS_SPI_UCODE_PATCH */
/* 5 */
/* Set SDMA configuration register */
@@ -299,10 +299,10 @@ void spi_init_r (void)
volatile immap_t *immr;
volatile cbd_t *tbdf, *rbdf;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
cp = (cpm8xx_t *) &immr->im_cpm;
-#ifdef CFG_SPI_UCODE_PATCH
+#ifdef CONFIG_SYS_SPI_UCODE_PATCH
spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
#else
spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
@@ -392,10 +392,10 @@ ssize_t spi_xfer (size_t count)
DPRINT (("*** spi_xfer entered ***\n"));
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
cp = (cpm8xx_t *) &immr->im_cpm;
-#ifdef CFG_SPI_UCODE_PATCH
+#ifdef CONFIG_SYS_SPI_UCODE_PATCH
spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
#else
spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
@@ -468,7 +468,7 @@ ssize_t spi_xfer (size_t count)
return count;
}
-#endif /* CONFIG_SPI || (CONFIG_POST & CFG_POST_SPI) */
+#endif /* CONFIG_SPI || (CONFIG_POST & CONFIG_SYS_POST_SPI) */
/*
* SPI test
@@ -481,7 +481,7 @@ ssize_t spi_xfer (size_t count)
* TEST_NUM - number of tests
*/
-#if CONFIG_POST & CFG_POST_SPI
+#if CONFIG_POST & CONFIG_SYS_POST_SPI
#define TEST_MIN_LENGTH 1
#define TEST_MAX_LENGTH MAX_BUFFER
@@ -513,7 +513,7 @@ static int packet_check (char * packet, int length)
int spi_post_test (int flags)
{
int res = -1;
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = (cpm8xx_t *) & immr->im_cpm;
int i;
int l;
@@ -557,4 +557,4 @@ int spi_post_test (int flags)
return res;
}
-#endif /* CONFIG_POST & CFG_POST_SPI */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_SPI */
diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S
index eca4b50..45c902e 100644
--- a/cpu/mpc8xx/start.S
+++ b/cpu/mpc8xx/start.S
@@ -39,6 +39,7 @@
*/
#include <config.h>
#include <mpc8xx.h>
+#include <timestamp.h>
#include <version.h>
#define CONFIG_8xx 1 /* needed for Linux kernel header files */
@@ -87,13 +88,13 @@
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
_start:
- lis r3, CFG_IMMR@h /* position IMMR */
+ lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
mtspr 638, r3
li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
b boot_cold
@@ -159,8 +160,8 @@ boot_warm:
* Calculate absolute address in FLASH and jump there
*----------------------------------------------------------------------*/
- lis r3, CFG_MONITOR_BASE@h
- ori r3, r3, CFG_MONITOR_BASE@l
+ lis r3, CONFIG_SYS_MONITOR_BASE@h
+ ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
@@ -170,8 +171,8 @@ in_flash:
/* initialize some SPRs that are hard to access from C */
/*----------------------------------------------------------------------*/
- lis r3, CFG_IMMR@h /* pass IMMR as arg1 to C routine */
- ori r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
+ lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */
+ ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
/* Note: R0 is still 0 here */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
@@ -187,8 +188,8 @@ in_flash:
/* Set up debug mode entry */
- lis r2, CFG_DER@h
- ori r2, r2, CFG_DER@l
+ lis r2, CONFIG_SYS_DER@h
+ ori r2, r2, CONFIG_SYS_DER@l
mtspr DER, r2
/* let the C-code set up the rest */
@@ -495,16 +496,16 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
diff --git a/cpu/mpc8xx/upatch.c b/cpu/mpc8xx/upatch.c
index 4d6c522..a8cb735 100644
--- a/cpu/mpc8xx/upatch.c
+++ b/cpu/mpc8xx/upatch.c
@@ -1,8 +1,8 @@
#include <common.h>
#include <commproc.h>
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \
- defined(CFG_SMC_UCODE_PATCH)
+#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
+ defined(CONFIG_SYS_SMC_UCODE_PATCH)
static void UcodeCopy (volatile cpm8xx_t *cpm);
@@ -11,36 +11,36 @@ void cpm_load_patch (volatile immap_t *immr)
immr->im_cpm.cp_rccr &= ~0x0003; /* Disable microcode program area */
UcodeCopy ((cpm8xx_t *)&immr->im_cpm); /* Copy ucode patch to DPRAM */
-#ifdef CFG_SPI_UCODE_PATCH
+#ifdef CONFIG_SYS_SPI_UCODE_PATCH
{
volatile spi_t *spi = (spi_t *) & immr->im_cpm.cp_dparam[PROFF_SPI];
/* Activate the microcode per the instructions in the microcode manual */
/* NOTE: We're only relocating the SPI parameters (not I2C). */
immr->im_cpm.cp_cpmcr1 = 0x802a; /* Write Trap register 1 value */
immr->im_cpm.cp_cpmcr2 = 0x8028; /* Write Trap register 2 value */
- spi->spi_rpbase = CFG_SPI_DPMEM_OFFSET; /* Where to relocte SPI params */
+ spi->spi_rpbase = CONFIG_SYS_SPI_DPMEM_OFFSET; /* Where to relocte SPI params */
}
#endif
-#ifdef CFG_I2C_UCODE_PATCH
+#ifdef CONFIG_SYS_I2C_UCODE_PATCH
{
volatile iic_t *iip = (iic_t *) & immr->im_cpm.cp_dparam[PROFF_IIC];
/* Activate the microcode per the instructions in the microcode manual */
/* NOTE: We're only relocating the I2C parameters (not SPI). */
immr->im_cpm.cp_cpmcr3 = 0x802e; /* Write Trap register 3 value */
immr->im_cpm.cp_cpmcr4 = 0x802c; /* Write Trap register 4 value */
- iip->iic_rpbase = CFG_I2C_DPMEM_OFFSET; /* Where to relocte I2C params */
+ iip->iic_rpbase = CONFIG_SYS_I2C_DPMEM_OFFSET; /* Where to relocte I2C params */
}
#endif
-#ifdef CFG_SMC_UCODE_PATCH
+#ifdef CONFIG_SYS_SMC_UCODE_PATCH
{
volatile smc_uart_t *up = (smc_uart_t *) & immr->im_cpm.cp_dparam[PROFF_SMC1];
/* Activate the microcode per the instructions in the microcode manual */
/* NOTE: We're only relocating the SMC parameters. */
immr->im_cpm.cp_cpmcr1 = 0x8080; /* Write Trap register 1 value */
immr->im_cpm.cp_cpmcr2 = 0x8088; /* Write Trap register 2 value */
- up->smc_rpbase = CFG_SMC_DPMEM_OFFSET; /* Where to relocte SMC params */
+ up->smc_rpbase = CONFIG_SYS_SMC_DPMEM_OFFSET; /* Where to relocte SMC params */
}
#endif
@@ -48,14 +48,14 @@ void cpm_load_patch (volatile immap_t *immr)
* Enable DPRAM microcode to execute from the first 512 bytes
* and a 256 byte extension of DPRAM.
*/
-#ifdef CFG_SMC_UCODE_PATCH
+#ifdef CONFIG_SYS_SMC_UCODE_PATCH
immr->im_cpm.cp_rccr |= 0x0002;
#else
immr->im_cpm.cp_rccr |= 0x0001;
#endif
}
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCh)
+#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCh)
static ulong patch_2000[] = {
0x7FFFEFD9, 0x3FFD0000, 0x7FFB49F7, 0x7FF90000,
0x5FEFADF7, 0x5F88ADF7, 0x5FEFAFF7, 0x5F88AFF7,
@@ -191,4 +191,4 @@ static void UcodeCopy (volatile cpm8xx_t *cpm)
}
}
-#endif /* CFG_I2C_UCODE_PATCH, CFG_SPI_UCODE_PATCH */
+#endif /* CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_SPI_UCODE_PATCH */
diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c
index ef91165..4a59927 100644
--- a/cpu/mpc8xx/video.c
+++ b/cpu/mpc8xx/video.c
@@ -33,6 +33,7 @@
#include <common.h>
#include <config.h>
#include <version.h>
+#include <timestamp.h>
#include <i2c.h>
#include <linux/types.h>
#include <devices.h>
@@ -517,7 +518,7 @@ static void inline video_mode_addentry (VRAM * vr,
static int video_mode_generate (void)
{
- immap_t *immap = (immap_t *) CFG_IMMR;
+ immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
VRAM *vr = (VRAM *) (((void *) immap) + 0xb00); /* Pointer to the VRAM table */
int DX, X1, X2, DY, Y1, Y2, entry = 0, fifo;
@@ -808,7 +809,7 @@ static void video_encoder_init (void)
/* Initialize the I2C */
debug ("[VIDEO ENCODER] Initializing I2C bus...\n");
- i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#ifdef CONFIG_FADS
/* Reset ADV7176 chip */
@@ -856,7 +857,7 @@ static void video_encoder_init (void)
static void video_ctrl_init (void *memptr)
{
- immap_t *immap = (immap_t *) CFG_IMMR;
+ immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
video_fb_address = memptr;
@@ -1174,7 +1175,8 @@ static void *video_logo (void)
easylogo_plot (VIDEO_LOGO_ADDR, screen, width, 0, 0);
#ifdef VIDEO_INFO
- sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__);
+ sprintf (info, "%s (%s - %s) ",
+ U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info);
sprintf (info, "(C) 2002 DENX Software Engineering");
@@ -1235,13 +1237,13 @@ static int video_init (void *videobase)
video_setpalette (CONSOLE_COLOR_GREY2, 0xF8, 0xF8, 0xF8);
video_setpalette (CONSOLE_COLOR_WHITE, 0xFF, 0xFF, 0xFF);
-#ifndef CFG_WHITE_ON_BLACK
+#ifndef CONFIG_SYS_WHITE_ON_BLACK
video_setfgcolor (CONSOLE_COLOR_BLACK);
video_setbgcolor (CONSOLE_COLOR_GREY2);
#else
video_setfgcolor (CONSOLE_COLOR_GREY2);
video_setbgcolor (CONSOLE_COLOR_BLACK);
-#endif /* CFG_WHITE_ON_BLACK */
+#endif /* CONFIG_SYS_WHITE_ON_BLACK */
#ifdef CONFIG_VIDEO_LOGO
/* Paint the logo and retrieve tv base address */
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index ca67551..1783e92 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -95,16 +95,10 @@ static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
col_bits_cs_n = dimm_params[i/2].n_col_addr - 8;
}
- /* FIXME: intlv_en, intlv_ctl only on CS0_CONFIG */
- if (i != 0) {
- intlv_en = 0;
- intlv_ctl = 0;
- }
-
ddr->cs[i].config = (0
| ((cs_n_en & 0x1) << 31)
| ((intlv_en & 0x3) << 29)
- | ((intlv_en & 0xf) << 24)
+ | ((intlv_ctl & 0xf) << 24)
| ((ap_n_en & 0x1) << 23)
/* XXX: some implementation only have 1 bit starting at left */
@@ -117,6 +111,7 @@ static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
| ((row_bits_cs_n & 0x7) << 8)
| ((col_bits_cs_n & 0x7) << 0)
);
+ debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
}
/* Chip Select Configuration 2 (CSn_CONFIG_2) */
@@ -126,6 +121,7 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
unsigned int pasr_cfg = 0; /* Partial array self refresh config */
ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
+ debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
}
/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
@@ -196,6 +192,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
| ((ext_caslat & 0x1) << 12)
| ((cntl_adj & 0x7) << 0)
);
+ debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
}
/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
@@ -263,6 +260,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
| ((acttoact_mclk & 0x07) << 4)
| ((wrtord_mclk & 0x07) << 0)
);
+ debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
}
/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
@@ -319,6 +317,7 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
| ((cke_pls & 0x7) << 6)
| ((four_act & 0x1f) << 0)
);
+ debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
}
/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
@@ -385,6 +384,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
| ((mem_halt & 0x1) << 1)
| ((bi & 0x1) << 0)
);
+ debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
}
/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
@@ -449,6 +449,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
| ((rcw_en & 0x1) << 2)
| ((md_en & 0x1) << 0)
);
+ debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
}
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
@@ -461,6 +462,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr)
| ((esdmode2 & 0xFFFF) << 16)
| ((esdmode3 & 0xFFFF) << 0)
);
+ debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
}
/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
@@ -480,6 +482,7 @@ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
| ((refint & 0xFFFF) << 16)
| ((bstopre & 0x3FFF) << 0)
);
+ debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
}
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
@@ -520,7 +523,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
unsigned int wr; /* Write Recovery */
unsigned int dll_res; /* DLL Reset */
unsigned int mode; /* Normal=0 or Test=1 */
- unsigned int caslat; /* CAS# latency */
+ unsigned int caslat = 0;/* CAS# latency */
/* BT: Burst Type (0=Sequential, 1=Interleaved) */
unsigned int bt;
unsigned int bl; /* BL: Burst Length */
@@ -572,7 +575,9 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
0x6, /* 2.5 clocks */
0x3 /* 3.0 clocks */
};
- caslat = mode_caslat_table[cas_latency - 1];
+ caslat = mode_caslat_table[cas_latency - 1];
+ } else {
+ printf("Warning: unknown cas_latency %d\n", cas_latency);
}
#elif defined(CONFIG_FSL_DDR2)
caslat = cas_latency;
@@ -611,6 +616,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
| ((esdmode & 0xFFFF) << 16)
| ((sdmode & 0xFFFF) << 0)
);
+ debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
}
@@ -673,6 +679,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
| ((wwt & 0xf) << 16)
| (dll_lock & 0x3)
);
+ debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
}
/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
@@ -689,6 +696,7 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
| ((wodt_on & 0xf) << 12)
| ((wodt_off & 0xf) << 8)
);
+ debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
}
/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
@@ -872,8 +880,13 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
phys_size_t sa = 0;
phys_size_t ea = 0;
- if (popts->ba_intlv_ctl && i > 0) {
- /* Don't set up boundaries if bank interleaving */
+
+ if (popts->ba_intlv_ctl && (i > 0) &&
+ ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) {
+ /* Don't set up boundaries for other CS
+ * other than CS0, if bank interleaving
+ * is enabled and not CS2+CS3 interleaved.
+ */
break;
}
@@ -892,7 +905,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
* on each controller is twice the amount present on
* each controller.
*/
- ea = (2 * common_dimm->total_mem >> dbw_cap_adj) - 1;
+ unsigned long long rank_density
+ = dimm_params[0].capacity;
+ ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
}
else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
/*
@@ -904,8 +919,44 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
* controller needs to be programmed into its
* respective CS0_BNDS.
*/
- sa = common_dimm->base_address;
- ea = sa + (common_dimm->total_mem >> dbw_cap_adj) - 1;
+ unsigned long long rank_density
+ = dimm_params[i/2].rank_density;
+ switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
+ case FSL_DDR_CS0_CS1_CS2_CS3:
+ /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
+ * needs to be set.
+ */
+ sa = common_dimm->base_address;
+ ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
+ break;
+ case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+ /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
+ * and CS2_CNDS need to be set.
+ */
+ if (!(i&1)) {
+ sa = dimm_params[i/2].base_address;
+ ea = sa + (i * (rank_density >>
+ dbw_cap_adj)) - 1;
+ }
+ break;
+ case FSL_DDR_CS0_CS1:
+ /* CS0+CS1 interleaving, CS0_CNDS needs
+ * to be set
+ */
+ sa = common_dimm->base_address;
+ ea = sa + (2 * (rank_density >> dbw_cap_adj))-1;
+ break;
+ case FSL_DDR_CS2_CS3:
+ /* CS2+CS3 interleaving*/
+ if (i == 2) {
+ sa = dimm_params[i/2].base_address;
+ ea = sa + (2 * (rank_density >>
+ dbw_cap_adj)) - 1;
+ }
+ break;
+ default: /* No bank(chip-select) interleaving */
+ break;
+ }
}
else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
/*
@@ -953,6 +1004,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
| ((ea & 0xFFF) << 0) /* ending address MSB */
);
+ debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
set_csn_config(i, ddr, popts, dimm_params);
set_csn_config_2(i, ddr);
}
diff --git a/cpu/mpc8xxx/ddr/ddr.h b/cpu/mpc8xxx/ddr/ddr.h
index f5dc40a..9ffd548 100644
--- a/cpu/mpc8xxx/ddr/ddr.h
+++ b/cpu/mpc8xxx/ddr/ddr.h
@@ -10,8 +10,8 @@
#define FSL_DDR_MAIN_H
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
-#include "ddr1_2_dimm_params.h"
#include "common_timing_params.h"
/*
@@ -31,17 +31,17 @@ compute_dimm_parameters(const generic_spd_eeprom_t *spd,
*
* All data structures have to be on the stack
*/
-#define CFG_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
-#define CFG_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
+#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
typedef struct {
generic_spd_eeprom_t
- spd_installed_dimms[CFG_NUM_DDR_CTLRS][CFG_DIMM_SLOTS_PER_CTLR];
+ spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
struct dimm_params_s
- dimm_params[CFG_NUM_DDR_CTLRS][CFG_DIMM_SLOTS_PER_CTLR];
- memctl_options_t memctl_opts[CFG_NUM_DDR_CTLRS];
- common_timing_params_t common_timing_params[CFG_NUM_DDR_CTLRS];
- fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CFG_NUM_DDR_CTLRS];
+ dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
+ memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
+ common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
+ fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
} fsl_ddr_info_t;
/* Compute steps */
@@ -71,6 +71,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
unsigned int number_of_dimms);
extern unsigned int populate_memctl_options(int all_DIMMs_registered,
memctl_options_t *popts,
+ dimm_params_t *pdimm,
unsigned int ctrl_num);
extern unsigned int mclk_to_picos(unsigned int mclk);
diff --git a/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h b/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h
deleted file mode 100644
index c794eed..0000000
--- a/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#ifndef DDR2_DIMM_PARAMS_H
-#define DDR2_DIMM_PARAMS_H
-
-/* Parameters for a DDR2 dimm computed from the SPD */
-typedef struct dimm_params_s {
-
- /* DIMM organization parameters */
- char mpart[19]; /* guaranteed null terminated */
-
- unsigned int n_ranks;
- unsigned long long rank_density;
- unsigned long long capacity;
- unsigned int data_width;
- unsigned int primary_sdram_width;
- unsigned int ec_sdram_width;
- unsigned int registered_dimm;
-
- /* SDRAM device parameters */
- unsigned int n_row_addr;
- unsigned int n_col_addr;
- unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
- unsigned int n_banks_per_sdram_device;
- unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
- unsigned int row_density;
-
- /* used in computing base address of DIMMs */
- unsigned long long base_address;
-
- /* DIMM timing parameters */
-
- /*
- * SDRAM clock periods
- * The range for these are 1000-10000 so a short should be sufficient
- */
- unsigned int tCKmin_X_ps;
- unsigned int tCKmin_X_minus_1_ps;
- unsigned int tCKmin_X_minus_2_ps;
- unsigned int tCKmax_ps;
-
- /* SPD-defined CAS latencies */
- unsigned int caslat_X;
- unsigned int caslat_X_minus_1;
- unsigned int caslat_X_minus_2;
-
- unsigned int caslat_lowest_derated; /* Derated CAS latency */
-
- /* basic timing parameters */
- unsigned int tRCD_ps;
- unsigned int tRP_ps;
- unsigned int tRAS_ps;
-
- unsigned int tWR_ps; /* maximum = 63750 ps */
- unsigned int tWTR_ps; /* maximum = 63750 ps */
- unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns
- = 511750 ps */
-
- unsigned int tRRD_ps; /* maximum = 63750 ps */
- unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
-
- unsigned int refresh_rate_ps;
-
- unsigned int tIS_ps; /* byte 32, spd->ca_setup */
- unsigned int tIH_ps; /* byte 33, spd->ca_hold */
- unsigned int tDS_ps; /* byte 34, spd->data_setup */
- unsigned int tDH_ps; /* byte 35, spd->data_hold */
- unsigned int tRTP_ps; /* byte 38, spd->trtp */
- unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */
- unsigned int tQHS_ps; /* byte 45, spd->tqhs */
-} dimm_params_t;
-
-extern unsigned int ddr_compute_dimm_parameters(
- const generic_spd_eeprom_t *spd,
- dimm_params_t *pdimm,
- unsigned int dimm_number);
-
-#endif
diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index ac4b80c..f1ad132 100644
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -44,10 +44,10 @@ extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
*
* memory controller/documention |industry |this code |signals
* -------------------------------|-----------|-----------|-----------------
- * physical bank/bank |rank |rank |chip select (CS)
- * logical bank/sub-bank |bank |bank |bank address (BA)
- * page/row |row |page |row address
- * ??? |column |column |column address
+ * physical bank/bank |rank |rank |chip select (CS)
+ * logical bank/sub-bank |bank |bank |bank address (BA)
+ * page/row |row |page |row address
+ * ??? |column |column |column address
*
* The naming confusion is further exacerbated by the descriptions of the
* memory controller interleaving feature, where accesses are interleaved
@@ -55,24 +55,24 @@ extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
* CS0_CONFIG[INTLV_CTL] of each memory controller.
*
* memory controller documentation | number of chip selects
- * | per memory controller supported
+ * | per memory controller supported
* --------------------------------|-----------------------------------------
- * cache line interleaving | 1 (CS0 only)
- * page interleaving | 1 (CS0 only)
- * bank interleaving | 1 (CS0 only)
- * superbank interleraving | depends on bank (chip select)
- * | interleraving [rank interleaving]
- * | mode used on every memory controller
+ * cache line interleaving | 1 (CS0 only)
+ * page interleaving | 1 (CS0 only)
+ * bank interleaving | 1 (CS0 only)
+ * superbank interleraving | depends on bank (chip select)
+ * | interleraving [rank interleaving]
+ * | mode used on every memory controller
*
* Even further confusing is the existence of the interleaving feature
* _WITHIN_ each memory controller. The feature is referred to in
* documentation as chip select interleaving or bank interleaving,
* although it is configured in the DDR_SDRAM_CFG field.
*
- * Name of field | documentation name | this code
+ * Name of field | documentation name | this code
* -----------------------------|-----------------------|------------------
- * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
- * | interleaving
+ * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
+ * | interleaving
*/
#ifdef DEBUG
@@ -164,6 +164,24 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
}
if (j == 2) {
*memctl_interleaving = 1;
+
+ printf("\nMemory controller interleaving enabled: ");
+
+ switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
+ case FSL_DDR_CACHE_LINE_INTERLEAVING:
+ printf("Cache-line interleaving!\n");
+ break;
+ case FSL_DDR_PAGE_INTERLEAVING:
+ printf("Page interleaving!\n");
+ break;
+ case FSL_DDR_BANK_INTERLEAVING:
+ printf("Bank interleaving!\n");
+ break;
+ case FSL_DDR_SUPERBANK_INTERLEAVING:
+ printf("Super bank interleaving\n");
+ default:
+ break;
+ }
}
/* Check that all controllers are rank interleaving. */
@@ -175,10 +193,30 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
}
if (j == 2) {
*rank_interleaving = 1;
+
+ printf("Bank(chip-select) interleaving enabled: ");
+
+ switch (pinfo->memctl_opts[0].ba_intlv_ctl &
+ FSL_DDR_CS0_CS1_CS2_CS3) {
+ case FSL_DDR_CS0_CS1_CS2_CS3:
+ printf("CS0+CS1+CS2+CS3\n");
+ break;
+ case FSL_DDR_CS0_CS1:
+ printf("CS0+CS1\n");
+ break;
+ case FSL_DDR_CS2_CS3:
+ printf("CS2+CS3\n");
+ break;
+ case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+ printf("CS0+CS1 and CS2+CS3\n");
+ default:
+ break;
+ }
}
if (*memctl_interleaving) {
phys_addr_t addr;
+ phys_size_t total_mem_per_ctlr = 0;
/*
* If interleaving between memory controllers,
@@ -197,14 +235,18 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
addr = 0;
+ pinfo->common_timing_params[i].base_address =
+ (phys_addr_t)addr;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
unsigned long long cap
= pinfo->dimm_params[i][j].capacity;
pinfo->dimm_params[i][j].base_address = addr;
addr += (phys_addr_t)(cap >> dbw_cap_adj[i]);
+ total_mem_per_ctlr += cap >> dbw_cap_adj[i];
}
}
+ pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
} else {
/*
* Simple linear assignment if memory
@@ -270,7 +312,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
generic_spd_eeprom_t *spd =
&(pinfo->spd_installed_dimms[i][j]);
dimm_params_t *pdimm =
- &(pinfo->dimm_params[i][j]);
+ &(pinfo->dimm_params[i][j]);
retval = compute_dimm_parameters(spd, pdimm, i);
if (retval == 2) {
@@ -314,7 +356,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
*/
populate_memctl_options(
timing_params[i].all_DIMMs_registered,
- &pinfo->memctl_opts[i], i);
+ &pinfo->memctl_opts[i],
+ pinfo->dimm_params[i], i);
}
case STEP_ASSIGN_ADDRESSES:
@@ -432,9 +475,14 @@ phys_size_t fsl_ddr_sdram(void)
*/
memctl_interleaved = 1;
} else {
- printf("Error: memctl interleaving not "
+ printf("Warning: memctl interleaving not "
"properly configured on all controllers\n");
- while (1);
+ memctl_interleaved = 0;
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+ info.memctl_opts[i].memctl_interleaving = 0;
+ debug("Recomputing with memctl_interleaving off.\n");
+ total_memory = fsl_ddr_compute(&info,
+ STEP_ASSIGN_ADDRESSES);
}
}
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 6c2b43c..af7f73a 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -13,13 +13,16 @@
/* Board-specific functions defined in each board's ddr.c */
extern void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
unsigned int ctrl_num);
unsigned int populate_memctl_options(int all_DIMMs_registered,
memctl_options_t *popts,
+ dimm_params_t *pdimm,
unsigned int ctrl_num)
{
unsigned int i;
+ const char *p;
/* Chip select options. */
@@ -179,19 +182,88 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
#error "FIXME determine four activates for DDR3"
#endif
- /* ODT should only be used for DDR2 */
-
- /* FIXME? */
-
/*
- * Interleaving checks.
+ * Check interleaving configuration from environment.
+ * Please refer to doc/README.fsl-ddr for the detail.
*
* If memory controller interleaving is enabled, then the data
* bus widths must be programmed identically for the 2 memory
* controllers.
+ *
+ * XXX: Attempt to set both controllers to the same chip select
+ * interleaving mode. It will do a best effort to get the
+ * requested ranks interleaved together such that the result
+ * should be a subset of the requested configuration.
*/
+ if ((p = getenv("memctl_intlv_ctl")) != NULL) {
+ if (pdimm[0].n_ranks == 0) {
+ printf("There is no rank on CS0. Because only rank on "
+ "CS0 and ranks chip-select interleaved with CS0"
+ " are controller interleaved, force non memory "
+ "controller interleaving\n");
+ popts->memctl_interleaving = 0;
+ } else {
+ popts->memctl_interleaving = 1;
+ if (strcmp(p, "cacheline") == 0)
+ popts->memctl_interleaving_mode =
+ FSL_DDR_CACHE_LINE_INTERLEAVING;
+ else if (strcmp(p, "page") == 0)
+ popts->memctl_interleaving_mode =
+ FSL_DDR_PAGE_INTERLEAVING;
+ else if (strcmp(p, "bank") == 0)
+ popts->memctl_interleaving_mode =
+ FSL_DDR_BANK_INTERLEAVING;
+ else if (strcmp(p, "superbank") == 0)
+ popts->memctl_interleaving_mode =
+ FSL_DDR_SUPERBANK_INTERLEAVING;
+ else
+ popts->memctl_interleaving_mode =
+ simple_strtoul(p, NULL, 0);
+ }
+ }
+
+ if( (p = getenv("ba_intlv_ctl")) != NULL) {
+ if (strcmp(p, "cs0_cs1") == 0)
+ popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
+ else if (strcmp(p, "cs2_cs3") == 0)
+ popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
+ else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0)
+ popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
+ else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0)
+ popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
+ else
+ popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0);
+
+ switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
+ case FSL_DDR_CS0_CS1_CS2_CS3:
+ case FSL_DDR_CS0_CS1:
+ if (pdimm[0].n_ranks != 2) {
+ popts->ba_intlv_ctl = 0;
+ printf("Not enough bank(chip-select) for "
+ "CS0+CS1, force non-interleaving!\n");
+ }
+ break;
+ case FSL_DDR_CS2_CS3:
+ if (pdimm[1].n_ranks !=2){
+ popts->ba_intlv_ctl = 0;
+ printf("Not enough bank(CS) for CS2+CS3, "
+ "force non-interleaving!\n");
+ }
+ break;
+ case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+ if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
+ popts->ba_intlv_ctl = 0;
+ printf("Not enough bank(CS) for CS0+CS1 or "
+ "CS2+CS3, force non-interleaving!\n");
+ }
+ break;
+ default:
+ popts->ba_intlv_ctl = 0;
+ break;
+ }
+ }
- fsl_ddr_board_options(popts, ctrl_num);
+ fsl_ddr_board_options(popts, pdimm, ctrl_num);
return 0;
}
diff --git a/cpu/nios/asmi.c b/cpu/nios/asmi.c
index c2cd8fe..2c2e838 100644
--- a/cpu/nios/asmi.c
+++ b/cpu/nios/asmi.c
@@ -27,8 +27,8 @@
#include <command.h>
#include <nios-io.h>
-#if !defined(CFG_NIOS_ASMIBASE)
-#error "*** CFG_NIOS_ASMIBASE not defined ***"
+#if !defined(CONFIG_SYS_NIOS_ASMIBASE)
+#error "*** CONFIG_SYS_NIOS_ASMIBASE not defined ***"
#endif
/*-----------------------------------------------------------------------*/
@@ -69,7 +69,7 @@
#define ASMI_STATUS_WIP (1<<0) /* Write in progress */
#define ASMI_STATUS_WEL (1<<1) /* Write enable latch */
-static nios_asmi_t *asmi = (nios_asmi_t *)CFG_NIOS_ASMIBASE;
+static nios_asmi_t *asmi = (nios_asmi_t *)CONFIG_SYS_NIOS_ASMIBASE;
/***********************************************************************
* Device access
diff --git a/cpu/nios/interrupts.c b/cpu/nios/interrupts.c
index 75e491d..55a5718 100644
--- a/cpu/nios/interrupts.c
+++ b/cpu/nios/interrupts.c
@@ -68,15 +68,15 @@ void set_timer (ulong t)
/* The board must handle this interrupt if a timer is not
* provided.
*/
-#if defined(CFG_NIOS_TMRBASE)
+#if defined(CONFIG_SYS_NIOS_TMRBASE)
void timer_interrupt (struct pt_regs *regs)
{
/* Interrupt is cleared by writing anything to the
* status register.
*/
- nios_timer_t *tmr = (nios_timer_t *)CFG_NIOS_TMRBASE;
+ nios_timer_t *tmr = (nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
tmr->status = 0;
- timestamp += CFG_NIOS_TMRMS;
+ timestamp += CONFIG_SYS_NIOS_TMRMS;
#ifdef CONFIG_STATUS_LED
status_led_tick(timestamp);
#endif
@@ -125,14 +125,14 @@ int interrupt_init (void)
{
int vec;
-#if defined(CFG_NIOS_TMRBASE)
- nios_timer_t *tmr = (nios_timer_t *)CFG_NIOS_TMRBASE;
+#if defined(CONFIG_SYS_NIOS_TMRBASE)
+ nios_timer_t *tmr = (nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
tmr->control &= ~NIOS_TIMER_ITO;
tmr->control |= NIOS_TIMER_STOP;
-#if defined(CFG_NIOS_TMRCNT)
- tmr->periodl = CFG_NIOS_TMRCNT & 0xffff;
- tmr->periodh = (CFG_NIOS_TMRCNT >> 16) & 0xffff;
+#if defined(CONFIG_SYS_NIOS_TMRCNT)
+ tmr->periodl = CONFIG_SYS_NIOS_TMRCNT & 0xffff;
+ tmr->periodh = (CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff;
#endif
#endif
@@ -143,11 +143,11 @@ int interrupt_init (void)
}
/* Need timus interruptus -- start the lopri timer */
-#if defined(CFG_NIOS_TMRBASE)
+#if defined(CONFIG_SYS_NIOS_TMRBASE)
tmr->control |= ( NIOS_TIMER_ITO |
NIOS_TIMER_CONT |
NIOS_TIMER_START );
- ipri (CFG_NIOS_TMRIRQ + 1);
+ ipri (CONFIG_SYS_NIOS_TMRIRQ + 1);
#endif
enable_interrupts ();
return (0);
diff --git a/cpu/nios/serial.c b/cpu/nios/serial.c
index 5ecdc6d..44aa600 100644
--- a/cpu/nios/serial.c
+++ b/cpu/nios/serial.c
@@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
*-----------------------------------------------------------------*/
#if defined(CONFIG_CONSOLE_JTAG)
-static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE;
+static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE;
void serial_setbrg( void ){ return; }
int serial_init( void ) { return(0);}
@@ -71,9 +71,9 @@ int serial_getc (void)
*-----------------------------------------------------------------*/
#else
-static nios_uart_t *uart = (nios_uart_t *)CFG_NIOS_CONSOLE;
+static nios_uart_t *uart = (nios_uart_t *)CONFIG_SYS_NIOS_CONSOLE;
-#if defined(CFG_NIOS_FIXEDBAUD)
+#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
/* Everything's already setup for fixed-baud PTF
* assignment
@@ -98,7 +98,7 @@ int serial_init (void)
return (0);
}
-#endif /* CFG_NIOS_FIXEDBAUD */
+#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
/*-----------------------------------------------------------------------
diff --git a/cpu/nios/spi.c b/cpu/nios/spi.c
index 6408180..89f9797 100644
--- a/cpu/nios/spi.c
+++ b/cpu/nios/spi.c
@@ -28,19 +28,19 @@
#include <nios-io.h>
#include <spi.h>
-#if !defined(CFG_NIOS_SPIBASE)
-#error "*** CFG_NIOS_SPIBASE not defined ***"
+#if !defined(CONFIG_SYS_NIOS_SPIBASE)
+#error "*** CONFIG_SYS_NIOS_SPIBASE not defined ***"
#endif
-#if !defined(CFG_NIOS_SPIBITS)
-#error "*** CFG_NIOS_SPIBITS not defined ***"
+#if !defined(CONFIG_SYS_NIOS_SPIBITS)
+#error "*** CONFIG_SYS_NIOS_SPIBITS not defined ***"
#endif
-#if (CFG_NIOS_SPIBITS != 8) && (CFG_NIOS_SPIBITS != 16)
-#error "*** CFG_NIOS_SPIBITS should be either 8 or 16 ***"
+#if (CONFIG_SYS_NIOS_SPIBITS != 8) && (CONFIG_SYS_NIOS_SPIBITS != 16)
+#error "*** CONFIG_SYS_NIOS_SPIBITS should be either 8 or 16 ***"
#endif
-static nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE;
+static nios_spi_t *spi = (nios_spi_t *)CONFIG_SYS_NIOS_SPIBASE;
/* Warning:
* You cannot enable DEBUG for early system initalization, i. e. when
@@ -139,7 +139,7 @@ int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout,
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
- if (!(flags & SPI_XFER_END) || bitlen > CFG_NIOS_SPIBITS) {
+ if (!(flags & SPI_XFER_END) || bitlen > CONFIG_SYS_NIOS_SPIBITS) {
/* leave chip select active */
spi->control |= NIOS_SPI_SSO;
}
@@ -147,7 +147,7 @@ int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout,
for ( j = 0; /* count each byte in */
j < ((bitlen + 7) / 8); /* dout[] and din[] */
-#if (CFG_NIOS_SPIBITS == 8)
+#if (CONFIG_SYS_NIOS_SPIBITS == 8)
j++) {
while ((spi->status & NIOS_SPI_TRDY) == 0)
@@ -158,7 +158,7 @@ int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout,
;
rxd[j] = (unsigned char)(spi->rxdata & 0xff);
-#elif (CFG_NIOS_SPIBITS == 16)
+#elif (CONFIG_SYS_NIOS_SPIBITS == 16)
j++, j++) {
while ((spi->status & NIOS_SPI_TRDY) == 0)
@@ -175,12 +175,12 @@ int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout,
rxd[j+1] = (unsigned char)(spi->rxdata & 0xff);
#else
-#error "*** unsupported value of CFG_NIOS_SPIBITS ***"
+#error "*** unsupported value of CONFIG_SYS_NIOS_SPIBITS ***"
#endif
}
- if (bitlen > CFG_NIOS_SPIBITS && (flags & SPI_XFER_END)) {
+ if (bitlen > CONFIG_SYS_NIOS_SPIBITS && (flags & SPI_XFER_END)) {
spi->control &= ~NIOS_SPI_SSO;
}
diff --git a/cpu/nios/start.S b/cpu/nios/start.S
index 9e73941..3578a04 100644
--- a/cpu/nios/start.S
+++ b/cpu/nios/start.S
@@ -23,6 +23,7 @@
#include <config.h>
+#include <timestamp.h>
#include <version.h>
#if !defined(CONFIG_IDENT_STRING)
@@ -71,10 +72,10 @@ _start:
/*
* STACK
*/
- pfx %hi(CFG_INIT_SP)
- movi %sp, %lo(CFG_INIT_SP)
- pfx %xhi(CFG_INIT_SP)
- movhi %sp, %xlo(CFG_INIT_SP)
+ pfx %hi(CONFIG_SYS_INIT_SP)
+ movi %sp, %lo(CONFIG_SYS_INIT_SP)
+ pfx %xhi(CONFIG_SYS_INIT_SP)
+ movhi %sp, %xlo(CONFIG_SYS_INIT_SP)
mov %fp, %sp
pfx %hi(4*16)
@@ -152,10 +153,10 @@ reloc:
/*
* INIT VECTOR TABLE
*/
- pfx %hi(CFG_VECT_BASE)
- movi %g0, %lo(CFG_VECT_BASE)
- pfx %xhi(CFG_VECT_BASE)
- movhi %g0, %xlo(CFG_VECT_BASE) /* dst */
+ pfx %hi(CONFIG_SYS_VECT_BASE)
+ movi %g0, %lo(CONFIG_SYS_VECT_BASE)
+ pfx %xhi(CONFIG_SYS_VECT_BASE)
+ movhi %g0, %xlo(CONFIG_SYS_VECT_BASE) /* dst */
mov %l0, %g0
pfx %hi(_vectors)
@@ -233,5 +234,5 @@ dly_clks:
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
diff --git a/cpu/nios2/cpu.c b/cpu/nios2/cpu.c
index f4217a8..6379534 100644
--- a/cpu/nios2/cpu.c
+++ b/cpu/nios2/cpu.c
@@ -25,14 +25,14 @@
#include <nios2.h>
#include <nios2-io.h>
-#if defined (CFG_NIOS_SYSID_BASE)
+#if defined (CONFIG_SYS_NIOS_SYSID_BASE)
extern void display_sysid (void);
-#endif /* CFG_NIOS_SYSID_BASE */
+#endif /* CONFIG_SYS_NIOS_SYSID_BASE */
int checkcpu (void)
{
printf ("CPU : Nios-II\n");
-#if !defined(CFG_NIOS_SYSID_BASE)
+#if !defined(CONFIG_SYS_NIOS_SYSID_BASE)
printf ("SYSID : <unknown>\n");
#else
display_sysid ();
@@ -43,7 +43,7 @@ int checkcpu (void)
int do_reset (void)
{
- void (*rst)(void) = (void(*)(void))CFG_RESET_ADDR;
+ void (*rst)(void) = (void(*)(void))CONFIG_SYS_RESET_ADDR;
disable_interrupts ();
rst();
return(0);
diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c
index 414c38c..968b50f 100644
--- a/cpu/nios2/epcs.c
+++ b/cpu/nios2/epcs.c
@@ -23,7 +23,7 @@
#include <common.h>
-#if defined(CFG_NIOS_EPCSBASE)
+#if defined(CONFIG_SYS_NIOS_EPCSBASE)
#include <command.h>
#include <asm/io.h>
#include <nios2-io.h>
@@ -72,7 +72,7 @@
*/
#define EPCS_TIMEOUT 100 /* 100 msec timeout */
-static nios_spi_t *epcs = (nios_spi_t *)CFG_NIOS_EPCSBASE;
+static nios_spi_t *epcs = (nios_spi_t *)CONFIG_SYS_NIOS_EPCSBASE;
/***********************************************************************
* Device access
diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c
index ec5db31b..1c3566e 100644
--- a/cpu/nios2/interrupts.c
+++ b/cpu/nios2/interrupts.c
@@ -37,8 +37,8 @@
#include <status_led.h>
#endif
-#if defined(CFG_NIOS_TMRBASE) && !defined(CFG_NIOS_TMRIRQ)
-#error CFG_NIOS_TMRIRQ not defined (see documentation)
+#if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ)
+#error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation)
#endif
/****************************************************************************/
@@ -74,7 +74,7 @@ void set_timer (ulong t)
/* The board must handle this interrupt if a timer is not
* provided.
*/
-#if defined(CFG_NIOS_TMRBASE)
+#if defined(CONFIG_SYS_NIOS_TMRBASE)
void tmr_isr (void *arg)
{
nios_timer_t *tmr = (nios_timer_t *)arg;
@@ -82,7 +82,7 @@ void tmr_isr (void *arg)
* status register.
*/
writel (&tmr->status, 0);
- timestamp += CFG_NIOS_TMRMS;
+ timestamp += CONFIG_SYS_NIOS_TMRMS;
#ifdef CONFIG_STATUS_LED
status_led_tick(timestamp);
#endif
@@ -90,22 +90,22 @@ void tmr_isr (void *arg)
static void tmr_init (void)
{
- nios_timer_t *tmr =(nios_timer_t *)CFG_NIOS_TMRBASE;
+ nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
writel (&tmr->status, 0);
writel (&tmr->control, 0);
writel (&tmr->control, NIOS_TIMER_STOP);
-#if defined(CFG_NIOS_TMRCNT)
- writel (&tmr->periodl, CFG_NIOS_TMRCNT & 0xffff);
- writel (&tmr->periodh, (CFG_NIOS_TMRCNT >> 16) & 0xffff);
+#if defined(CONFIG_SYS_NIOS_TMRCNT)
+ writel (&tmr->periodl, CONFIG_SYS_NIOS_TMRCNT & 0xffff);
+ writel (&tmr->periodh, (CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff);
#endif
writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT |
NIOS_TIMER_START );
- irq_install_handler (CFG_NIOS_TMRIRQ, tmr_isr, (void *)tmr);
+ irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr);
}
-#endif /* CFG_NIOS_TMRBASE */
+#endif /* CONFIG_SYS_NIOS_TMRBASE */
/*************************************************************************/
int disable_interrupts (void)
@@ -195,7 +195,7 @@ int interrupt_init (void)
vecs[i].count = 0;
}
-#if defined(CFG_NIOS_TMRBASE)
+#if defined(CONFIG_SYS_NIOS_TMRBASE)
tmr_init ();
#endif
diff --git a/cpu/nios2/serial.c b/cpu/nios2/serial.c
index 0bd3821..8bbb803 100644
--- a/cpu/nios2/serial.c
+++ b/cpu/nios2/serial.c
@@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
*-----------------------------------------------------------------*/
#if defined(CONFIG_CONSOLE_JTAG)
-static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE;
+static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE;
void serial_setbrg( void ){ return; }
int serial_init( void ) { return(0);}
@@ -79,9 +79,9 @@ int serial_getc (void)
*-----------------------------------------------------------------*/
#else
-static nios_uart_t *uart = (nios_uart_t *) CFG_NIOS_CONSOLE;
+static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE;
-#if defined(CFG_NIOS_FIXEDBAUD)
+#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
/* Everything's already setup for fixed-baud PTF
* assignment
@@ -106,7 +106,7 @@ int serial_init (void)
return (0);
}
-#endif /* CFG_NIOS_FIXEDBAUD */
+#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
/*-----------------------------------------------------------------------
diff --git a/cpu/nios2/start.S b/cpu/nios2/start.S
index 6c6f294..31cd5b0 100644
--- a/cpu/nios2/start.S
+++ b/cpu/nios2/start.S
@@ -23,6 +23,7 @@
#include <config.h>
+#include <timestamp.h>
#include <version.h>
/*************************************************************************
@@ -39,9 +40,9 @@ _start:
* just be invalidating the cache a second time. If cache
* is not implemented initi behaves as nop.
*/
- ori r4, r0, %lo(CFG_ICACHELINE_SIZE)
- movhi r5, %hi(CFG_ICACHE_SIZE)
- ori r5, r5, %lo(CFG_ICACHE_SIZE)
+ ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE)
+ movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE)
+ ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE)
mov r6, r0
0: initi r6
add r6, r6, r4
@@ -67,10 +68,10 @@ _except_end:
/* DCACHE INIT -- if dcache not implemented, initd behaves as
* nop.
*/
- movhi r4, %hi(CFG_DCACHELINE_SIZE)
- ori r4, r4, %lo(CFG_DCACHELINE_SIZE)
- movhi r5, %hi(CFG_DCACHE_SIZE)
- ori r5, r5, %lo(CFG_DCACHE_SIZE)
+ movhi r4, %hi(CONFIG_SYS_DCACHELINE_SIZE)
+ ori r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE)
+ movhi r5, %hi(CONFIG_SYS_DCACHE_SIZE)
+ ori r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE)
mov r6, r0
1: initd 0(r6)
add r6, r6, r4
@@ -136,8 +137,8 @@ _reloc:
ori r4, r4, %lo(_except_start)
movhi r5, %hi(_except_end)
ori r5, r5, %lo(_except_end)
- movhi r6, %hi(CFG_EXCEPTION_ADDR)
- ori r6, r6, %lo(CFG_EXCEPTION_ADDR)
+ movhi r6, %hi(CONFIG_SYS_EXCEPTION_ADDR)
+ ori r6, r6, %lo(CONFIG_SYS_EXCEPTION_ADDR)
beq r4, r6, 7f /* Skip if at proper addr */
6: ldwio r7, 0(r4)
@@ -150,8 +151,8 @@ _reloc:
/* STACK INIT -- zero top two words for call back chain.
*/
- movhi sp, %hi(CFG_INIT_SP)
- ori sp, sp, %lo(CFG_INIT_SP)
+ movhi sp, %hi(CONFIG_SYS_INIT_SP)
+ ori sp, sp, %lo(CONFIG_SYS_INIT_SP)
addi sp, sp, -8
stw r0, 0(sp)
stw r0, 4(sp)
@@ -195,7 +196,7 @@ _reloc:
dly_clks:
-#if (CFG_ICACHE_SIZE > 0)
+#if (CONFIG_SYS_ICACHE_SIZE > 0)
subi r4, r4, 3 /* 3 clocks/loop */
#else
subi r4, r4, 12 /* 12 clocks/loop */
@@ -212,5 +213,5 @@ dly_clks:
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
diff --git a/cpu/nios2/sysid.c b/cpu/nios2/sysid.c
index 697ed03..afd5d83 100644
--- a/cpu/nios2/sysid.c
+++ b/cpu/nios2/sysid.c
@@ -23,7 +23,7 @@
#include <common.h>
-#if defined (CFG_NIOS_SYSID_BASE)
+#if defined (CONFIG_SYS_NIOS_SYSID_BASE)
#include <command.h>
#include <asm/io.h>
@@ -32,7 +32,7 @@
void display_sysid (void)
{
- struct nios_sysid_t *sysid = (struct nios_sysid_t *)CFG_NIOS_SYSID_BASE;
+ struct nios_sysid_t *sysid = (struct nios_sysid_t *)CONFIG_SYS_NIOS_SYSID_BASE;
struct tm t;
char asc[32];
time_t stamp;
@@ -55,4 +55,4 @@ U_BOOT_CMD(
"sysid - display Nios-II system id\n\n",
"\n - display Nios-II system id\n"
);
-#endif /* CFG_NIOS_SYSID_BASE */
+#endif /* CONFIG_SYS_NIOS_SYSID_BASE */
diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c
index b21b13e..57861b3 100644
--- a/cpu/ppc4xx/40x_spd_sdram.c
+++ b/cpu/ppc4xx/40x_spd_sdram.c
@@ -52,12 +52,12 @@
/*
* Set default values
*/
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED 50000
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED 50000
#endif
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE 0xFE
+#ifndef CONFIG_SYS_I2C_SLAVE
+#define CONFIG_SYS_I2C_SLAVE 0xFE
#endif
#define ONE_BILLION 1000000000
@@ -163,7 +163,7 @@ long int spd_sdram(int(read_spd)(uint addr))
* Make sure I2C controller is initialized
* before continuing.
*/
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
}
/* Make shure we are using SDRAM */
diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index 9efcede..153391e 100644
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -62,12 +62,12 @@
/*
* Set default values
*/
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED 50000
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED 50000
#endif
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE 0xFE
+#ifndef CONFIG_SYS_I2C_SLAVE
+#define CONFIG_SYS_I2C_SLAVE 0xFE
#endif
#define ONE_BILLION 1000000000
@@ -119,7 +119,7 @@ struct bank_param {
typedef struct bank_param BANKPARMS;
-#ifdef CFG_SIMULATE_SPD_EEPROM
+#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
extern const unsigned char cfg_simulate_spd_eeprom[128];
#endif
@@ -174,7 +174,7 @@ long int spd_sdram(void) {
* Make sure I2C controller is initialized
* before continuing.
*/
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
/*
* Read the SPD information using I2C interface. Check to see if the
@@ -265,7 +265,7 @@ long int spd_sdram(void) {
/*
* If ecc is enabled, initialize the parity bits.
*/
- ecc_init(CFG_SDRAM_BASE, total_size);
+ ecc_init(CONFIG_SYS_SDRAM_BASE, total_size);
#endif
return total_size;
@@ -275,14 +275,14 @@ static unsigned char spd_read(uchar chip, uint addr)
{
unsigned char data[2];
-#ifdef CFG_SIMULATE_SPD_EEPROM
- if (chip == CFG_SIMULATE_SPD_EEPROM) {
+#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
+ if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) {
/*
* Onboard spd eeprom requested -> simulate values
*/
return cfg_simulate_spd_eeprom[addr];
}
-#endif /* CFG_SIMULATE_SPD_EEPROM */
+#endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */
if (i2c_probe(chip) == 0) {
if (i2c_read(chip, addr, 1, data, 1) == 0) {
@@ -1120,7 +1120,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
/*
* reset the bank_base address
*/
- bank_base_addr = CFG_SDRAM_BASE;
+ bank_base_addr = CONFIG_SYS_SDRAM_BASE;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 15250d4..b40e4b1 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -60,7 +60,25 @@
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)
-static inline void ppc4xx_ibm_ddr2_register_dump(void);
+#if defined(CONFIG_440)
+/*
+ * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
+ * memory region. Right now the cache should still be disabled in U-Boot
+ * because of the EMAC driver, that need its buffer descriptor to be located
+ * in non cached memory.
+ *
+ * If at some time this restriction doesn't apply anymore, just define
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
+ * everything correctly.
+ */
+#ifdef CONFIG_4xx_DCACHE
+/* enable caching on SDRAM */
+#define MY_TLB_WORD2_I_ENABLE 0
+#else
+/* disable caching on SDRAM */
+#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
+#endif /* CONFIG_4xx_DCACHE */
+#endif /* CONFIG_440 */
#if defined(CONFIG_SPD_EEPROM)
@@ -133,22 +151,6 @@ static inline void ppc4xx_ibm_ddr2_register_dump(void);
#define NUMLOOPS 64 /* memory test loops */
/*
- * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
- * region. Right now the cache should still be disabled in U-Boot because of the
- * EMAC driver, that need it's buffer descriptor to be located in non cached
- * memory.
- *
- * If at some time this restriction doesn't apply anymore, just define
- * CONFIG_4xx_DCACHE in the board config file and this code should setup
- * everything correctly.
- */
-#ifdef CONFIG_4xx_DCACHE
-#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
-#else
-#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
-#endif
-
-/*
* Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
* To support such configurations, we "only" map the first 2GB via the TLB's. We
* need some free virtual address space for the remaining peripherals like, SoC
@@ -260,62 +262,19 @@ static void program_ecc_addr(unsigned long start_address,
unsigned long num_bytes,
unsigned long tlb_word2_i_value);
#endif
+#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
static void program_DQS_calibration(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned char *iic0_dimm_addr,
+ unsigned long num_dimm_banks);
#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
static void test(void);
#else
static void DQS_calibration_process(void);
#endif
+#endif
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
void dcbz_area(u32 start_address, u32 num_bytes);
-static u32 mfdcr_any(u32 dcr)
-{
- u32 val;
-
- switch (dcr) {
- case SDRAM_R0BAS + 0:
- val = mfdcr(SDRAM_R0BAS + 0);
- break;
- case SDRAM_R0BAS + 1:
- val = mfdcr(SDRAM_R0BAS + 1);
- break;
- case SDRAM_R0BAS + 2:
- val = mfdcr(SDRAM_R0BAS + 2);
- break;
- case SDRAM_R0BAS + 3:
- val = mfdcr(SDRAM_R0BAS + 3);
- break;
- default:
- printf("DCR %d not defined in case statement!!!\n", dcr);
- val = 0; /* just to satisfy the compiler */
- }
-
- return val;
-}
-
-static void mtdcr_any(u32 dcr, u32 val)
-{
- switch (dcr) {
- case SDRAM_R0BAS + 0:
- mtdcr(SDRAM_R0BAS + 0, val);
- break;
- case SDRAM_R0BAS + 1:
- mtdcr(SDRAM_R0BAS + 1, val);
- break;
- case SDRAM_R0BAS + 2:
- mtdcr(SDRAM_R0BAS + 2, val);
- break;
- case SDRAM_R0BAS + 3:
- mtdcr(SDRAM_R0BAS + 3, val);
- break;
- default:
- printf("DCR %d not defined in case statement!!!\n", dcr);
- }
-}
-
static unsigned char spd_read(uchar chip, uint addr)
{
unsigned char data[2];
@@ -447,8 +406,8 @@ phys_size_t initdram(int board_type)
*/
/* switch to correct I2C bus */
- I2C_SET_BUS(CFG_SPD_BUS_NUM);
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
/*------------------------------------------------------------------
* Clear out the serial presence detect buffers.
@@ -609,7 +568,11 @@ phys_size_t initdram(int board_type)
/*------------------------------------------------------------------
* DQS calibration.
*-----------------------------------------------------------------*/
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+ DQS_autocalibration();
+#else
program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+#endif
#ifdef CONFIG_DDR_ECC
/*------------------------------------------------------------------
@@ -2302,10 +2265,12 @@ static void program_memory_queue(unsigned long *dimm_populated,
/*
* Set optimal value for Memory Queue HB/LL Configuration registers
*/
- mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
- SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
- mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
- SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+ mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
+ SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
+ SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
+ mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
+ SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
+ SDRAM_CONF1LL_RPLM);
mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
#endif
}
@@ -2329,18 +2294,6 @@ static unsigned long is_ecc_enabled(void)
return ecc;
}
-static void blank_string(int size)
-{
- int i;
-
- for (i=0; i<size; i++)
- putc('\b');
- for (i=0; i<size; i++)
- putc(' ');
- for (i=0; i<size; i++)
- putc('\b');
-}
-
#ifdef CONFIG_DDR_ECC
/*-----------------------------------------------------------------------------+
* program_ecc.
@@ -2468,6 +2421,7 @@ static void program_ecc_addr(unsigned long start_address,
}
#endif
+#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
/*-----------------------------------------------------------------------------+
* program_DQS_calibration.
*-----------------------------------------------------------------------------*/
@@ -3001,15 +2955,17 @@ static void test(void)
(ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
| ecc_temp);
}
-#endif
+#endif /* !HARD_CODED_DQS */
+#endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
#else /* CONFIG_SPD_EEPROM */
/*-----------------------------------------------------------------------------
* Function: initdram
- * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
- * banks. The configuration is performed using static, compile-
+ * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
+ * The configuration is performed using static, compile-
* time parameters.
+ * Configures the PPC405EX(r) and PPC460EX/GT
*---------------------------------------------------------------------------*/
phys_size_t initdram(int board_type)
{
@@ -3025,64 +2981,76 @@ phys_size_t initdram(int board_type)
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
unsigned long val;
+#if defined(CONFIG_440)
+ mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
+ mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
+ mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
+ mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
+ mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
+ mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
+ mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
+ mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
+ mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
+#endif
+
/* Set Memory Bank Configuration Registers */
- mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
- mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
- mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
- mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
+ mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
+ mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
+ mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
+ mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
/* Set Memory Clock Timing Register */
- mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
+ mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
/* Set Refresh Time Register */
- mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
+ mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
/* Set SDRAM Timing Registers */
- mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
- mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
- mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
+ mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
+ mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
+ mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
/* Set Mode and Extended Mode Registers */
- mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
- mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
+ mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
+ mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
/* Set Memory Controller Options 1 Register */
- mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
+ mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
/* Set Manual Initialization Control Registers */
- mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
- mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
- mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
- mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
- mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
- mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
- mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
- mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
- mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
- mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
- mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
- mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
- mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
- mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
- mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
- mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
+ mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
+ mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
+ mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
+ mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
+ mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
+ mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
+ mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
+ mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
+ mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
+ mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
+ mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
+ mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
+ mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
+ mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
+ mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
+ mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
/* Set On-Die Termination Registers */
- mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
- mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
- mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
+ mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
+ mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
+ mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
/* Set Write Timing Register */
- mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
+ mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
/*
* Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
@@ -3103,10 +3071,13 @@ phys_size_t initdram(int board_type)
/* Set Delay Control Registers */
- mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
- mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
- mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
- mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
+ mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
+
+#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+ mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
+ mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
+ mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
+#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
/*
* Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
@@ -3115,18 +3086,116 @@ phys_size_t initdram(int board_type)
mfsdram(SDRAM_MCOPT2, val);
mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
+#if defined(CONFIG_440)
+ /*
+ * Program TLB entries with caches enabled, for best performace
+ * while auto-calibrating and ECC generation
+ */
+ program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
+#endif
+
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+ /*------------------------------------------------------------------
+ | DQS calibration.
+ +-----------------------------------------------------------------*/
+ DQS_autocalibration();
+#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
+#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
+
#if defined(CONFIG_DDR_ECC)
- ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
+ ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
#endif /* defined(CONFIG_DDR_ECC) */
+#if defined(CONFIG_440)
+ /*
+ * Now after initialization (auto-calibration and ECC generation)
+ * remove the TLB entries with caches enabled and program again with
+ * desired cache functionality
+ */
+ remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
+ program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
+#endif
+
ppc4xx_ibm_ddr2_register_dump();
+
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+ /*
+ * Clear potential errors resulting from auto-calibration.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
+
#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
- return (CFG_MBYTES_SDRAM << 20);
+ return (CONFIG_SYS_MBYTES_SDRAM << 20);
}
#endif /* CONFIG_SPD_EEPROM */
-static inline void ppc4xx_ibm_ddr2_register_dump(void)
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_440)
+u32 mfdcr_any(u32 dcr)
+{
+ u32 val;
+
+ switch (dcr) {
+ case SDRAM_R0BAS + 0:
+ val = mfdcr(SDRAM_R0BAS + 0);
+ break;
+ case SDRAM_R0BAS + 1:
+ val = mfdcr(SDRAM_R0BAS + 1);
+ break;
+ case SDRAM_R0BAS + 2:
+ val = mfdcr(SDRAM_R0BAS + 2);
+ break;
+ case SDRAM_R0BAS + 3:
+ val = mfdcr(SDRAM_R0BAS + 3);
+ break;
+ default:
+ printf("DCR %d not defined in case statement!!!\n", dcr);
+ val = 0; /* just to satisfy the compiler */
+ }
+
+ return val;
+}
+
+void mtdcr_any(u32 dcr, u32 val)
+{
+ switch (dcr) {
+ case SDRAM_R0BAS + 0:
+ mtdcr(SDRAM_R0BAS + 0, val);
+ break;
+ case SDRAM_R0BAS + 1:
+ mtdcr(SDRAM_R0BAS + 1, val);
+ break;
+ case SDRAM_R0BAS + 2:
+ mtdcr(SDRAM_R0BAS + 2, val);
+ break;
+ case SDRAM_R0BAS + 3:
+ mtdcr(SDRAM_R0BAS + 3, val);
+ break;
+ default:
+ printf("DCR %d not defined in case statement!!!\n", dcr);
+ }
+}
+#endif /* defined(CONFIG_440) */
+
+void blank_string(int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++)
+ putc('\b');
+ for (i = 0; i < size; i++)
+ putc(' ');
+ for (i = 0; i < size; i++)
+ putc('\b');
+}
+#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
+
+inline void ppc4xx_ibm_ddr2_register_dump(void)
{
#if defined(DEBUG)
printf("\nPPC4xx IBM DDR2 Register Dump:\n");
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
deleted file mode 100644
index 8a38335..0000000
--- a/cpu/ppc4xx/4xx_enet.c
+++ /dev/null
@@ -1,1983 +0,0 @@
-/*-----------------------------------------------------------------------------+
- *
- * This source code has been made available to you by IBM on an AS-IS
- * basis. Anyone receiving this source is licensed under IBM
- * copyrights to use it in any way he or she deems fit, including
- * copying it, modifying it, compiling it, and redistributing it either
- * with or without modifications. No license under IBM patents or
- * patent applications is to be implied by the copyright license.
- *
- * Any user of this software should understand that IBM cannot provide
- * technical support for this software and will not be responsible for
- * any consequences resulting from the use of this software.
- *
- * Any person who transfers this source code or any derivative work
- * must include the IBM copyright notice, this paragraph, and the
- * preceding two paragraphs in the transferred software.
- *
- * COPYRIGHT I B M CORPORATION 1995
- * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
- *-----------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------+
- *
- * File Name: enetemac.c
- *
- * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
- *
- * Author: Mark Wisner
- *
- * Change Activity-
- *
- * Date Description of Change BY
- * --------- --------------------- ---
- * 05-May-99 Created MKW
- * 27-Jun-99 Clean up JWB
- * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
- * 29-Jul-99 Added Full duplex support MKW
- * 06-Aug-99 Changed names for Mal CR reg MKW
- * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
- * 24-Aug-99 Marked descriptor empty after call_xlc MKW
- * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
- * to avoid chaining maximum sized packets. Push starting
- * RX descriptor address up to the next cache line boundary.
- * 16-Jan-00 Added support for booting with IP of 0x0 MKW
- * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
- * EMAC_RXM register. JWB
- * 12-Mar-01 anne-sophie.harnois@nextream.fr
- * - Variables are compatible with those already defined in
- * include/net.h
- * - Receive buffer descriptor ring is used to send buffers
- * to the user
- * - Info print about send/received/handled packet number if
- * INFO_405_ENET is set
- * 17-Apr-01 stefan.roese@esd-electronics.com
- * - MAL reset in "eth_halt" included
- * - Enet speed and duplex output now in one line
- * 08-May-01 stefan.roese@esd-electronics.com
- * - MAL error handling added (eth_init called again)
- * 13-Nov-01 stefan.roese@esd-electronics.com
- * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
- * 04-Jan-02 stefan.roese@esd-electronics.com
- * - Wait for PHY auto negotiation to complete added
- * 06-Feb-02 stefan.roese@esd-electronics.com
- * - Bug fixed in waiting for auto negotiation to complete
- * 26-Feb-02 stefan.roese@esd-electronics.com
- * - rx and tx buffer descriptors now allocated (no fixed address
- * used anymore)
- * 17-Jun-02 stefan.roese@esd-electronics.com
- * - MAL error debug printf 'M' removed (rx de interrupt may
- * occur upon many incoming packets with only 4 rx buffers).
- *-----------------------------------------------------------------------------*
- * 17-Nov-03 travis.sawyer@sandburst.com
- * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
- * in the 440GX. This port should work with the 440GP
- * (2 EMACs) also
- * 15-Aug-05 sr@denx.de
- * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
- now handling all 4xx cpu's.
- *-----------------------------------------------------------------------------*/
-
-#include <config.h>
-#include <common.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <commproc.h>
-#include <ppc4xx.h>
-#include <ppc4xx_enet.h>
-#include <405_mal.h>
-#include <miiphy.h>
-#include <malloc.h>
-
-/*
- * Only compile for platform with AMCC EMAC ethernet controller and
- * network support enabled.
- * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
- */
-#if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
-
-#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
-#error "CONFIG_MII has to be defined!"
-#endif
-
-#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
-#error "CONFIG_NET_MULTI has to be defined for NetConsole"
-#endif
-
-#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
-#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
-
-/* Ethernet Transmit and Receive Buffers */
-/* AS.HARNOIS
- * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
- * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
- */
-#define ENET_MAX_MTU PKTSIZE
-#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
-
-/*-----------------------------------------------------------------------------+
- * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
- * Interrupt Controller).
- *-----------------------------------------------------------------------------*/
-#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
-
-#if defined(CONFIG_HAS_ETH3)
-#if !defined(CONFIG_440GX)
-#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
- UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
-#else
-/* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
-#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
-#define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
-#endif /* !defined(CONFIG_440GX) */
-#elif defined(CONFIG_HAS_ETH2)
-#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
- UIC_MASK(ETH_IRQ_NUM(2)))
-#elif defined(CONFIG_HAS_ETH1)
-#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
-#else
-#define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
-#endif
-
-/*
- * Define a default version for UIC_ETHxB for non 440GX so that we can
- * use common code for all 4xx variants
- */
-#if !defined(UIC_ETHxB)
-#define UIC_ETHxB 0
-#endif
-
-#define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
-#define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
-#define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
-#define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
-#define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
-
-#define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
-#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
-
-/*
- * We have 3 different interrupt types:
- * - MAL interrupts indicating successful transfer
- * - MAL error interrupts indicating MAL related errors
- * - EMAC interrupts indicating EMAC related errors
- *
- * All those interrupts can be on different UIC's, but since
- * now at least all interrupts from one type are on the same
- * UIC. Only exception is 440GX where the EMAC interrupts are
- * spread over two UIC's!
- */
-#if defined(CONFIG_440GX)
-#define UIC_BASE_MAL UIC1_DCR_BASE
-#define UIC_BASE_MAL_ERR UIC2_DCR_BASE
-#define UIC_BASE_EMAC UIC2_DCR_BASE
-#define UIC_BASE_EMAC_B UIC3_DCR_BASE
-#else
-#define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
-#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
-#define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
-#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
-#endif
-
-#undef INFO_4XX_ENET
-
-#define BI_PHYMODE_NONE 0
-#define BI_PHYMODE_ZMII 1
-#define BI_PHYMODE_RGMII 2
-#define BI_PHYMODE_GMII 3
-#define BI_PHYMODE_RTBI 4
-#define BI_PHYMODE_TBI 5
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
-#define BI_PHYMODE_SMII 6
-#define BI_PHYMODE_MII 7
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define BI_PHYMODE_RMII 8
-#endif
-#endif
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
-#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
-#else
-#define MAL_RX_CHAN_MUL 1
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Global variables. TX and RX descriptors and buffers.
- *-----------------------------------------------------------------------------*/
-#if !defined(CONFIG_NET_MULTI)
-struct eth_device *emac0_dev = NULL;
-#endif
-
-/*
- * Get count of EMAC devices (doesn't have to be the max. possible number
- * supported by the cpu)
- *
- * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
- * EMAC count is possible. As it is needed for the Kilauea/Haleakala
- * 405EX/405EXr eval board, using the same binary.
- */
-#if defined(CONFIG_BOARD_EMAC_COUNT)
-#define LAST_EMAC_NUM board_emac_count()
-#else /* CONFIG_BOARD_EMAC_COUNT */
-#if defined(CONFIG_HAS_ETH3)
-#define LAST_EMAC_NUM 4
-#elif defined(CONFIG_HAS_ETH2)
-#define LAST_EMAC_NUM 3
-#elif defined(CONFIG_HAS_ETH1)
-#define LAST_EMAC_NUM 2
-#else
-#define LAST_EMAC_NUM 1
-#endif
-#endif /* CONFIG_BOARD_EMAC_COUNT */
-
-/* normal boards start with EMAC0 */
-#if !defined(CONFIG_EMAC_NR_START)
-#define CONFIG_EMAC_NR_START 0
-#endif
-
-#define MAL_RX_DESC_SIZE 2048
-#define MAL_TX_DESC_SIZE 2048
-#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
-
-/*-----------------------------------------------------------------------------+
- * Prototypes and externals.
- *-----------------------------------------------------------------------------*/
-static void enet_rcv (struct eth_device *dev, unsigned long malisr);
-
-int enetInt (struct eth_device *dev);
-static void mal_err (struct eth_device *dev, unsigned long isr,
- unsigned long uic, unsigned long maldef,
- unsigned long mal_errr);
-static void emac_err (struct eth_device *dev, unsigned long isr);
-
-extern int phy_setup_aneg (char *devname, unsigned char addr);
-extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value);
-extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
-
-int board_emac_count(void);
-
-static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
-{
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_405EX)
- u32 val;
-
- mfsdr(sdr_mfr, val);
- val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
- mtsdr(sdr_mfr, val);
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
- u32 val;
-
- mfsdr(SDR0_ETH_CFG, val);
- val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
- mtsdr(SDR0_ETH_CFG, val);
-#endif
-}
-
-static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
-{
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_405EX)
- u32 val;
-
- mfsdr(sdr_mfr, val);
- val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
- mtsdr(sdr_mfr, val);
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
- u32 val;
-
- mfsdr(SDR0_ETH_CFG, val);
- val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
- mtsdr(SDR0_ETH_CFG, val);
-#endif
-}
-
-/*-----------------------------------------------------------------------------+
-| ppc_4xx_eth_halt
-| Disable MAL channel, and EMACn
-+-----------------------------------------------------------------------------*/
-static void ppc_4xx_eth_halt (struct eth_device *dev)
-{
- EMAC_4XX_HW_PST hw_p = dev->priv;
- u32 val = 10000;
-
- out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
-
- /* 1st reset MAL channel */
- /* Note: writing a 0 to a channel has no effect */
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
- mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
-#else
- mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
-#endif
- mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
-
- /* wait for reset */
- while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
- udelay (1000); /* Delay 1 MS so as not to hammer the register */
- val--;
- if (val == 0)
- break;
- }
-
- /* provide clocks for EMAC internal loopback */
- emac_loopback_enable(hw_p);
-
- /* EMAC RESET */
- out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
-
- /* remove clocks for EMAC internal loopback */
- emac_loopback_disable(hw_p);
-
-#ifndef CONFIG_NETCONSOLE
- hw_p->print_speed = 1; /* print speed message again next time */
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
- mfsdr(SDR0_ETH_CFG, val);
- val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
- mtsdr(SDR0_ETH_CFG, val);
-#endif
-
- return;
-}
-
-#if defined (CONFIG_440GX)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
- unsigned long pfc1;
- unsigned long zmiifer;
- unsigned long rmiifer;
-
- mfsdr(sdr_pfc1, pfc1);
- pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
-
- zmiifer = 0;
- rmiifer = 0;
-
- switch (pfc1) {
- case 1:
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_ZMII;
- bis->bi_phymode[2] = BI_PHYMODE_ZMII;
- bis->bi_phymode[3] = BI_PHYMODE_ZMII;
- break;
- case 2:
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_ZMII;
- bis->bi_phymode[2] = BI_PHYMODE_ZMII;
- bis->bi_phymode[3] = BI_PHYMODE_ZMII;
- break;
- case 3:
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- bis->bi_phymode[2] = BI_PHYMODE_RGMII;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 4:
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_ZMII;
- bis->bi_phymode[2] = BI_PHYMODE_RGMII;
- bis->bi_phymode[3] = BI_PHYMODE_RGMII;
- break;
- case 5:
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_ZMII;
- bis->bi_phymode[2] = BI_PHYMODE_ZMII;
- bis->bi_phymode[3] = BI_PHYMODE_RGMII;
- break;
- case 6:
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_ZMII;
- bis->bi_phymode[2] = BI_PHYMODE_RGMII;
- break;
- case 0:
- default:
- zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
- rmiifer = 0x0;
- bis->bi_phymode[0] = BI_PHYMODE_ZMII;
- bis->bi_phymode[1] = BI_PHYMODE_ZMII;
- bis->bi_phymode[2] = BI_PHYMODE_ZMII;
- bis->bi_phymode[3] = BI_PHYMODE_ZMII;
- break;
- }
-
- /* Ensure we setup mdio for this devnum and ONLY this devnum */
- zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
-
- out_be32((void *)ZMII_FER, zmiifer);
- out_be32((void *)RGMII_FER, rmiifer);
-
- return ((int)pfc1);
-}
-#endif /* CONFIG_440_GX */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
- unsigned long zmiifer=0x0;
- unsigned long pfc1;
-
- mfsdr(sdr_pfc1, pfc1);
- pfc1 &= SDR0_PFC1_SELECT_MASK;
-
- switch (pfc1) {
- case SDR0_PFC1_SELECT_CONFIG_2:
- /* 1 x GMII port */
- out_be32((void *)ZMII_FER, 0x00);
- out_be32((void *)RGMII_FER, 0x00000037);
- bis->bi_phymode[0] = BI_PHYMODE_GMII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- break;
- case SDR0_PFC1_SELECT_CONFIG_4:
- /* 2 x RGMII ports */
- out_be32((void *)ZMII_FER, 0x00);
- out_be32((void *)RGMII_FER, 0x00000055);
- bis->bi_phymode[0] = BI_PHYMODE_RGMII;
- bis->bi_phymode[1] = BI_PHYMODE_RGMII;
- break;
- case SDR0_PFC1_SELECT_CONFIG_6:
- /* 2 x SMII ports */
- out_be32((void *)ZMII_FER,
- ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
- ((ZMII_FER_SMII) << ZMII_FER_V(1)));
- out_be32((void *)RGMII_FER, 0x00000000);
- bis->bi_phymode[0] = BI_PHYMODE_SMII;
- bis->bi_phymode[1] = BI_PHYMODE_SMII;
- break;
- case SDR0_PFC1_SELECT_CONFIG_1_2:
- /* only 1 x MII supported */
- out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
- out_be32((void *)RGMII_FER, 0x00000000);
- bis->bi_phymode[0] = BI_PHYMODE_MII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- break;
- default:
- break;
- }
-
- /* Ensure we setup mdio for this devnum and ONLY this devnum */
- zmiifer = in_be32((void *)ZMII_FER);
- zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
- out_be32((void *)ZMII_FER, zmiifer);
-
- return ((int)0x0);
-}
-#endif /* CONFIG_440EPX */
-
-#if defined(CONFIG_405EX)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
- u32 rgmiifer = 0;
-
- /*
- * The 405EX(r)'s RGMII bridge can operate in one of several
- * modes, only one of which (2 x RGMII) allows the
- * simultaneous use of both EMACs on the 405EX.
- */
-
- switch (CONFIG_EMAC_PHY_MODE) {
-
- case EMAC_PHY_MODE_NONE:
- /* No ports */
- rgmiifer |= RGMII_FER_DIS << 0;
- rgmiifer |= RGMII_FER_DIS << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_NONE;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- break;
- case EMAC_PHY_MODE_NONE_RGMII:
- /* 1 x RGMII port on channel 0 */
- rgmiifer |= RGMII_FER_RGMII << 0;
- rgmiifer |= RGMII_FER_DIS << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_RGMII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- break;
- case EMAC_PHY_MODE_RGMII_NONE:
- /* 1 x RGMII port on channel 1 */
- rgmiifer |= RGMII_FER_DIS << 0;
- rgmiifer |= RGMII_FER_RGMII << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_NONE;
- bis->bi_phymode[1] = BI_PHYMODE_RGMII;
- break;
- case EMAC_PHY_MODE_RGMII_RGMII:
- /* 2 x RGMII ports */
- rgmiifer |= RGMII_FER_RGMII << 0;
- rgmiifer |= RGMII_FER_RGMII << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_RGMII;
- bis->bi_phymode[1] = BI_PHYMODE_RGMII;
- break;
- case EMAC_PHY_MODE_NONE_GMII:
- /* 1 x GMII port on channel 0 */
- rgmiifer |= RGMII_FER_GMII << 0;
- rgmiifer |= RGMII_FER_DIS << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_GMII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- break;
- case EMAC_PHY_MODE_NONE_MII:
- /* 1 x MII port on channel 0 */
- rgmiifer |= RGMII_FER_MII << 0;
- rgmiifer |= RGMII_FER_DIS << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_MII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- break;
- case EMAC_PHY_MODE_GMII_NONE:
- /* 1 x GMII port on channel 1 */
- rgmiifer |= RGMII_FER_DIS << 0;
- rgmiifer |= RGMII_FER_GMII << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_NONE;
- bis->bi_phymode[1] = BI_PHYMODE_GMII;
- break;
- case EMAC_PHY_MODE_MII_NONE:
- /* 1 x MII port on channel 1 */
- rgmiifer |= RGMII_FER_DIS << 0;
- rgmiifer |= RGMII_FER_MII << 4;
- out_be32((void *)RGMII_FER, rgmiifer);
- bis->bi_phymode[0] = BI_PHYMODE_NONE;
- bis->bi_phymode[1] = BI_PHYMODE_MII;
- break;
- default:
- break;
- }
-
- /* Ensure we setup mdio for this devnum and ONLY this devnum */
- rgmiifer = in_be32((void *)RGMII_FER);
- rgmiifer |= (1 << (19-devnum));
- out_be32((void *)RGMII_FER, rgmiifer);
-
- return ((int)0x0);
-}
-#endif /* CONFIG_405EX */
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
- u32 eth_cfg;
- u32 zmiifer; /* ZMII0_FER reg. */
- u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
- u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
- int mode;
-
- zmiifer = 0;
- rmiifer = 0;
- rmiifer1 = 0;
-
-#if defined(CONFIG_460EX)
- mode = 9;
-#else
- mode = 10;
-#endif
-
- /* TODO:
- * NOTE: 460GT has 2 RGMII bridge cores:
- * emac0 ------ RGMII0_BASE
- * |
- * emac1 -----+
- *
- * emac2 ------ RGMII1_BASE
- * |
- * emac3 -----+
- *
- * 460EX has 1 RGMII bridge core:
- * and RGMII1_BASE is disabled
- * emac0 ------ RGMII0_BASE
- * |
- * emac1 -----+
- */
-
- /*
- * Right now only 2*RGMII is supported. Please extend when needed.
- * sr - 2008-02-19
- */
- switch (mode) {
- case 1:
- /* 1 MII - 460EX */
- /* GMC0 EMAC4_0, ZMII Bridge */
- zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
- bis->bi_phymode[0] = BI_PHYMODE_MII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 2:
- /* 2 MII - 460GT */
- /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
- zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
- bis->bi_phymode[0] = BI_PHYMODE_MII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- bis->bi_phymode[2] = BI_PHYMODE_MII;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 3:
- /* 2 RMII - 460EX */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
- bis->bi_phymode[0] = BI_PHYMODE_RMII;
- bis->bi_phymode[1] = BI_PHYMODE_RMII;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 4:
- /* 4 RMII - 460GT */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
- /* ZMII Bridge */
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
- zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
- bis->bi_phymode[0] = BI_PHYMODE_RMII;
- bis->bi_phymode[1] = BI_PHYMODE_RMII;
- bis->bi_phymode[2] = BI_PHYMODE_RMII;
- bis->bi_phymode[3] = BI_PHYMODE_RMII;
- break;
- case 5:
- /* 2 SMII - 460EX */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
- bis->bi_phymode[0] = BI_PHYMODE_SMII;
- bis->bi_phymode[1] = BI_PHYMODE_SMII;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 6:
- /* 4 SMII - 460GT */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
- /* ZMII Bridge */
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
- zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
- bis->bi_phymode[0] = BI_PHYMODE_SMII;
- bis->bi_phymode[1] = BI_PHYMODE_SMII;
- bis->bi_phymode[2] = BI_PHYMODE_SMII;
- bis->bi_phymode[3] = BI_PHYMODE_SMII;
- break;
- case 7:
- /* This is the default mode that we want for board bringup - Maple */
- /* 1 GMII - 460EX */
- /* GMC0 EMAC4_0, RGMII Bridge 0 */
- rmiifer |= RGMII_FER_MDIO(0);
-
- if (devnum == 0) {
- rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
- bis->bi_phymode[0] = BI_PHYMODE_GMII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- } else {
- rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
- bis->bi_phymode[0] = BI_PHYMODE_NONE;
- bis->bi_phymode[1] = BI_PHYMODE_GMII;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- }
- break;
- case 8:
- /* 2 GMII - 460GT */
- /* GMC0 EMAC4_0, RGMII Bridge 0 */
- /* GMC1 EMAC4_2, RGMII Bridge 1 */
- rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
- rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
- rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
- rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
-
- bis->bi_phymode[0] = BI_PHYMODE_GMII;
- bis->bi_phymode[1] = BI_PHYMODE_NONE;
- bis->bi_phymode[2] = BI_PHYMODE_GMII;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 9:
- /* 2 RGMII - 460EX */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
- rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
-
- bis->bi_phymode[0] = BI_PHYMODE_RGMII;
- bis->bi_phymode[1] = BI_PHYMODE_RGMII;
- bis->bi_phymode[2] = BI_PHYMODE_NONE;
- bis->bi_phymode[3] = BI_PHYMODE_NONE;
- break;
- case 10:
- /* 4 RGMII - 460GT */
- /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
- /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
- rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
- rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
- rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
- bis->bi_phymode[0] = BI_PHYMODE_RGMII;
- bis->bi_phymode[1] = BI_PHYMODE_RGMII;
- bis->bi_phymode[2] = BI_PHYMODE_RGMII;
- bis->bi_phymode[3] = BI_PHYMODE_RGMII;
- break;
- default:
- break;
- }
-
- /* Set EMAC for MDIO */
- mfsdr(SDR0_ETH_CFG, eth_cfg);
- eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
- mtsdr(SDR0_ETH_CFG, eth_cfg);
-
- out_be32((void *)RGMII_FER, rmiifer);
-#if defined(CONFIG_460GT)
- out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
-#endif
-
- /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
- mfsdr(SDR0_ETH_CFG, eth_cfg);
- eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
- mtsdr(SDR0_ETH_CFG, eth_cfg);
-
- return 0;
-}
-#endif /* CONFIG_460EX || CONFIG_460GT */
-
-static inline void *malloc_aligned(u32 size, u32 align)
-{
- return (void *)(((u32)malloc(size + align) + align - 1) &
- ~(align - 1));
-}
-
-static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
-{
- int i;
- unsigned long reg = 0;
- unsigned long msr;
- unsigned long speed;
- unsigned long duplex;
- unsigned long failsafe;
- unsigned mode_reg;
- unsigned short devnum;
- unsigned short reg_short;
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- sys_info_t sysinfo;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- int ethgroup = -1;
-#endif
-#endif
- u32 bd_cached;
- u32 bd_uncached = 0;
-#ifdef CONFIG_4xx_DCACHE
- static u32 last_used_ea = 0;
-#endif
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- int rgmii_channel;
-#endif
-
- EMAC_4XX_HW_PST hw_p = dev->priv;
-
- /* before doing anything, figure out if we have a MAC address */
- /* if not, bail */
- if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
- printf("ERROR: ethaddr not set!\n");
- return -1;
- }
-
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- /* Need to get the OPB frequency so we can access the PHY */
- get_sys_info (&sysinfo);
-#endif
-
- msr = mfmsr ();
- mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
-
- devnum = hw_p->devnum;
-
-#ifdef INFO_4XX_ENET
- /* AS.HARNOIS
- * We should have :
- * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
- * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
- * is possible that new packets (without relationship with
- * current transfer) have got the time to arrived before
- * netloop calls eth_halt
- */
- printf ("About preceeding transfer (eth%d):\n"
- "- Sent packet number %d\n"
- "- Received packet number %d\n"
- "- Handled packet number %d\n",
- hw_p->devnum,
- hw_p->stats.pkts_tx,
- hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
-
- hw_p->stats.pkts_tx = 0;
- hw_p->stats.pkts_rx = 0;
- hw_p->stats.pkts_handled = 0;
- hw_p->print_speed = 1; /* print speed message again next time */
-#endif
-
- hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
- hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
-
- hw_p->rx_slot = 0; /* MAL Receive Slot */
- hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
- hw_p->rx_u_index = 0; /* Receive User Queue Index */
-
- hw_p->tx_slot = 0; /* MAL Transmit Slot */
- hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
- hw_p->tx_u_index = 0; /* Transmit User Queue Index */
-
-#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
- /* set RMII mode */
- /* NOTE: 440GX spec states that mode is mutually exclusive */
- /* NOTE: Therefore, disable all other EMACS, since we handle */
- /* NOTE: only one emac at a time */
- reg = 0;
- out_be32((void *)ZMII_FER, 0);
- udelay (100);
-
-#if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
- out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
-#elif defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
- ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
-#endif
-
- out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
-#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
-#if defined(CONFIG_405EX)
- ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
-#endif
-
- sync();
-
- /* provide clocks for EMAC internal loopback */
- emac_loopback_enable(hw_p);
-
- /* EMAC RESET */
- out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
-
- /* remove clocks for EMAC internal loopback */
- emac_loopback_disable(hw_p);
-
- failsafe = 1000;
- while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
- udelay (1000);
- failsafe--;
- }
- if (failsafe <= 0)
- printf("\nProblem resetting EMAC!\n");
-
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- /* Whack the M1 register */
- mode_reg = 0x0;
- mode_reg &= ~0x00000038;
- if (sysinfo.freqOPB <= 50000000);
- else if (sysinfo.freqOPB <= 66666667)
- mode_reg |= EMAC_M1_OBCI_66;
- else if (sysinfo.freqOPB <= 83333333)
- mode_reg |= EMAC_M1_OBCI_83;
- else if (sysinfo.freqOPB <= 100000000)
- mode_reg |= EMAC_M1_OBCI_100;
- else
- mode_reg |= EMAC_M1_OBCI_GT100;
-
- out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
-#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
-
- /* wait for PHY to complete auto negotiation */
- reg_short = 0;
-#ifndef CONFIG_CS8952_PHY
- switch (devnum) {
- case 0:
- reg = CONFIG_PHY_ADDR;
- break;
-#if defined (CONFIG_PHY1_ADDR)
- case 1:
- reg = CONFIG_PHY1_ADDR;
- break;
-#endif
-#if defined (CONFIG_PHY2_ADDR)
- case 2:
- reg = CONFIG_PHY2_ADDR;
- break;
-#endif
-#if defined (CONFIG_PHY3_ADDR)
- case 3:
- reg = CONFIG_PHY3_ADDR;
- break;
-#endif
- default:
- reg = CONFIG_PHY_ADDR;
- break;
- }
-
- bis->bi_phynum[devnum] = reg;
-
-#if defined(CONFIG_PHY_RESET)
- /*
- * Reset the phy, only if its the first time through
- * otherwise, just check the speeds & feeds
- */
- if (hw_p->first_init == 0) {
-#if defined(CONFIG_M88E1111_PHY)
- miiphy_write (dev->name, reg, 0x14, 0x0ce3);
- miiphy_write (dev->name, reg, 0x18, 0x4101);
- miiphy_write (dev->name, reg, 0x09, 0x0e00);
- miiphy_write (dev->name, reg, 0x04, 0x01e1);
-#endif
- miiphy_reset (dev->name, reg);
-
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
-
-#if defined(CONFIG_CIS8201_PHY)
- /*
- * Cicada 8201 PHY needs to have an extended register whacked
- * for RGMII mode.
- */
- if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
-#if defined(CONFIG_CIS8201_SHORT_ETCH)
- miiphy_write (dev->name, reg, 23, 0x1300);
-#else
- miiphy_write (dev->name, reg, 23, 0x1000);
-#endif
- /*
- * Vitesse VSC8201/Cicada CIS8201 errata:
- * Interoperability problem with Intel 82547EI phys
- * This work around (provided by Vitesse) changes
- * the default timer convergence from 8ms to 12ms
- */
- miiphy_write (dev->name, reg, 0x1f, 0x2a30);
- miiphy_write (dev->name, reg, 0x08, 0x0200);
- miiphy_write (dev->name, reg, 0x1f, 0x52b5);
- miiphy_write (dev->name, reg, 0x02, 0x0004);
- miiphy_write (dev->name, reg, 0x01, 0x0671);
- miiphy_write (dev->name, reg, 0x00, 0x8fae);
- miiphy_write (dev->name, reg, 0x1f, 0x2a30);
- miiphy_write (dev->name, reg, 0x08, 0x0000);
- miiphy_write (dev->name, reg, 0x1f, 0x0000);
- /* end Vitesse/Cicada errata */
- }
-#endif
-
-#if defined(CONFIG_ET1011C_PHY)
- /*
- * Agere ET1011c PHY needs to have an extended register whacked
- * for RGMII mode.
- */
- if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
- miiphy_read (dev->name, reg, 0x16, &reg_short);
- reg_short &= ~(0x7);
- reg_short |= 0x6; /* RGMII DLL Delay*/
- miiphy_write (dev->name, reg, 0x16, reg_short);
-
- miiphy_read (dev->name, reg, 0x17, &reg_short);
- reg_short &= ~(0x40);
- miiphy_write (dev->name, reg, 0x17, reg_short);
-
- miiphy_write(dev->name, reg, 0x1c, 0x74f0);
- }
-#endif
-
-#endif
- /* Start/Restart autonegotiation */
- phy_setup_aneg (dev->name, reg);
- udelay (1000);
- }
-#endif /* defined(CONFIG_PHY_RESET) */
-
- miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
-
- /*
- * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
- */
- if ((reg_short & PHY_BMSR_AUTN_ABLE)
- && !(reg_short & PHY_BMSR_AUTN_COMP)) {
- puts ("Waiting for PHY auto negotiation to complete");
- i = 0;
- while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
- /*
- * Timeout reached ?
- */
- if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts (" TIMEOUT !\n");
- break;
- }
-
- if ((i++ % 1000) == 0) {
- putc ('.');
- }
- udelay (1000); /* 1 ms */
- miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
-
- }
- puts (" done\n");
- udelay (500000); /* another 500 ms (results in faster booting) */
- }
-#endif /* #ifndef CONFIG_CS8952_PHY */
-
- speed = miiphy_speed (dev->name, reg);
- duplex = miiphy_duplex (dev->name, reg);
-
- if (hw_p->print_speed) {
- hw_p->print_speed = 0;
- printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
- (int) speed, (duplex == HALF) ? "HALF" : "FULL",
- hw_p->devnum);
- }
-
-#if defined(CONFIG_440) && \
- !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
- !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
- !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- mfsdr(sdr_mfr, reg);
- if (speed == 100) {
- reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
- } else {
- reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
- }
- mtsdr(sdr_mfr, reg);
-#endif
-
- /* Set ZMII/RGMII speed according to the phy link speed */
- reg = in_be32((void *)ZMII_SSR);
- if ( (speed == 100) || (speed == 1000) )
- out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
- else
- out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
-
- if ((devnum == 2) || (devnum == 3)) {
- if (speed == 1000)
- reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
- else if (speed == 100)
- reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
- else if (speed == 10)
- reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
- else {
- printf("Error in RGMII Speed\n");
- return -1;
- }
- out_be32((void *)RGMII_SSR, reg);
- }
-#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- if (devnum >= 2)
- rgmii_channel = devnum - 2;
- else
- rgmii_channel = devnum;
-
- if (speed == 1000)
- reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
- else if (speed == 100)
- reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
- else if (speed == 10)
- reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
- else {
- printf("Error in RGMII Speed\n");
- return -1;
- }
- out_be32((void *)RGMII_SSR, reg);
-#if defined(CONFIG_460GT)
- if ((devnum == 2) || (devnum == 3))
- out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
-#endif
-#endif
-
- /* set the Mal configuration reg */
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
- MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
-#else
- mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
- /* Errata 1.12: MAL_1 -- Disable MAL bursting */
- if (get_pvr() == PVR_440GP_RB) {
- mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
- }
-#endif
-
- /*
- * Malloc MAL buffer desciptors, make sure they are
- * aligned on cache line boundary size
- * (401/403/IOP480 = 16, 405 = 32)
- * and doesn't cross cache block boundaries.
- */
- if (hw_p->first_init == 0) {
- debug("*** Allocating descriptor memory ***\n");
-
- bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
- if (!bd_cached) {
- printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
- return -1;
- }
-
-#ifdef CONFIG_4xx_DCACHE
- flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
- if (!last_used_ea)
-#if defined(CFG_MEM_TOP_HIDE)
- bd_uncached = bis->bi_memsize + CFG_MEM_TOP_HIDE;
-#else
- bd_uncached = bis->bi_memsize;
-#endif
- else
- bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
-
- last_used_ea = bd_uncached;
- program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
- TLB_WORD2_I_ENABLE);
-#else
- bd_uncached = bd_cached;
-#endif
- hw_p->tx_phys = bd_cached;
- hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
- hw_p->tx = (mal_desc_t *)(bd_uncached);
- hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
- debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
- }
-
- for (i = 0; i < NUM_TX_BUFF; i++) {
- hw_p->tx[i].ctrl = 0;
- hw_p->tx[i].data_len = 0;
- if (hw_p->first_init == 0)
- hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
- L1_CACHE_BYTES);
- hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
- if ((NUM_TX_BUFF - 1) == i)
- hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
- hw_p->tx_run[i] = -1;
- debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
- }
-
- for (i = 0; i < NUM_RX_BUFF; i++) {
- hw_p->rx[i].ctrl = 0;
- hw_p->rx[i].data_len = 0;
- hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
- if ((NUM_RX_BUFF - 1) == i)
- hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
- hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
- hw_p->rx_ready[i] = -1;
- debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
- }
-
- reg = 0x00000000;
-
- reg |= dev->enetaddr[0]; /* set high address */
- reg = reg << 8;
- reg |= dev->enetaddr[1];
-
- out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
-
- reg = 0x00000000;
- reg |= dev->enetaddr[2]; /* set low address */
- reg = reg << 8;
- reg |= dev->enetaddr[3];
- reg = reg << 8;
- reg |= dev->enetaddr[4];
- reg = reg << 8;
- reg |= dev->enetaddr[5];
-
- out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
-
- switch (devnum) {
- case 1:
- /* setup MAL tx & rx channel pointers */
-#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
- mtdcr (maltxctp2r, hw_p->tx_phys);
-#else
- mtdcr (maltxctp1r, hw_p->tx_phys);
-#endif
-#if defined(CONFIG_440)
- mtdcr (maltxbattr, 0x0);
- mtdcr (malrxbattr, 0x0);
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- mtdcr (malrxctp8r, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
-#else
- mtdcr (malrxctp1r, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
-#endif
- break;
-#if defined (CONFIG_440GX)
- case 2:
- /* setup MAL tx & rx channel pointers */
- mtdcr (maltxbattr, 0x0);
- mtdcr (malrxbattr, 0x0);
- mtdcr (maltxctp2r, hw_p->tx_phys);
- mtdcr (malrxctp2r, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
- break;
- case 3:
- /* setup MAL tx & rx channel pointers */
- mtdcr (maltxbattr, 0x0);
- mtdcr (maltxctp3r, hw_p->tx_phys);
- mtdcr (malrxbattr, 0x0);
- mtdcr (malrxctp3r, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
- break;
-#endif /* CONFIG_440GX */
-#if defined (CONFIG_460GT)
- case 2:
- /* setup MAL tx & rx channel pointers */
- mtdcr (maltxbattr, 0x0);
- mtdcr (malrxbattr, 0x0);
- mtdcr (maltxctp2r, hw_p->tx_phys);
- mtdcr (malrxctp16r, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
- break;
- case 3:
- /* setup MAL tx & rx channel pointers */
- mtdcr (maltxbattr, 0x0);
- mtdcr (malrxbattr, 0x0);
- mtdcr (maltxctp3r, hw_p->tx_phys);
- mtdcr (malrxctp24r, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
- break;
-#endif /* CONFIG_460GT */
- case 0:
- default:
- /* setup MAL tx & rx channel pointers */
-#if defined(CONFIG_440)
- mtdcr (maltxbattr, 0x0);
- mtdcr (malrxbattr, 0x0);
-#endif
- mtdcr (maltxctp0r, hw_p->tx_phys);
- mtdcr (malrxctp0r, hw_p->rx_phys);
- /* set RX buffer size */
- mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
- break;
- }
-
- /* Enable MAL transmit and receive channels */
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
- mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
-#else
- mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
-#endif
- mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
-
- /* set transmit enable & receive enable */
- out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
-
- mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
-
- /* set rx-/tx-fifo size */
- mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
-
- /* set speed */
- if (speed == _1000BASET) {
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
- unsigned long pfc1;
-
- mfsdr (sdr_pfc1, pfc1);
- pfc1 |= SDR0_PFC1_EM_1000;
- mtsdr (sdr_pfc1, pfc1);
-#endif
- mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
- } else if (speed == _100BASET)
- mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
- else
- mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
- if (duplex == FULL)
- mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
-
- out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
-
- /* Enable broadcast and indvidual address */
- /* TBS: enabling runts as some misbehaved nics will send runts */
- out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
-
- /* we probably need to set the tx mode1 reg? maybe at tx time */
-
- /* set transmit request threshold register */
- out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
-
- /* set receive low/high water mark register */
-#if defined(CONFIG_440)
- /* 440s has a 64 byte burst length */
- out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
-#else
- /* 405s have a 16 byte burst length */
- out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
-#endif /* defined(CONFIG_440) */
- out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
-
- /* Set fifo limit entry in tx mode 0 */
- out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
- /* Frame gap set */
- out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
-
- /* Set EMAC IER */
- hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
- if (speed == _100BASET)
- hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
-
- out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
- out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
-
- if (hw_p->first_init == 0) {
- /*
- * Connect interrupt service routines
- */
- irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
- (interrupt_handler_t *) enetInt, dev);
- }
-
- mtmsr (msr); /* enable interrupts again */
-
- hw_p->bis = bis;
- hw_p->first_init = 1;
-
- return 0;
-}
-
-
-static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
- int len)
-{
- struct enet_frame *ef_ptr;
- ulong time_start, time_now;
- unsigned long temp_txm0;
- EMAC_4XX_HW_PST hw_p = dev->priv;
-
- ef_ptr = (struct enet_frame *) ptr;
-
- /*-----------------------------------------------------------------------+
- * Copy in our address into the frame.
- *-----------------------------------------------------------------------*/
- (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
-
- /*-----------------------------------------------------------------------+
- * If frame is too long or too short, modify length.
- *-----------------------------------------------------------------------*/
- /* TBS: where does the fragment go???? */
- if (len > ENET_MAX_MTU)
- len = ENET_MAX_MTU;
-
- /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
- memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
- flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
-
- /*-----------------------------------------------------------------------+
- * set TX Buffer busy, and send it
- *-----------------------------------------------------------------------*/
- hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
- EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
- ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
- if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
- hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
-
- hw_p->tx[hw_p->tx_slot].data_len = (short) len;
- hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
-
- sync();
-
- out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
- in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
-#ifdef INFO_4XX_ENET
- hw_p->stats.pkts_tx++;
-#endif
-
- /*-----------------------------------------------------------------------+
- * poll unitl the packet is sent and then make sure it is OK
- *-----------------------------------------------------------------------*/
- time_start = get_timer (0);
- while (1) {
- temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
- /* loop until either TINT turns on or 3 seconds elapse */
- if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
- /* transmit is done, so now check for errors
- * If there is an error, an interrupt should
- * happen when we return
- */
- time_now = get_timer (0);
- if ((time_now - time_start) > 3000) {
- return (-1);
- }
- } else {
- return (len);
- }
- }
-}
-
-int enetInt (struct eth_device *dev)
-{
- int serviced;
- int rc = -1; /* default to not us */
- u32 mal_isr;
- u32 emac_isr = 0;
- u32 mal_eob;
- u32 uic_mal;
- u32 uic_mal_err;
- u32 uic_emac;
- u32 uic_emac_b;
- EMAC_4XX_HW_PST hw_p;
-
- /*
- * Because the mal is generic, we need to get the current
- * eth device
- */
-#if defined(CONFIG_NET_MULTI)
- dev = eth_get_dev();
-#else
- dev = emac0_dev;
-#endif
-
- hw_p = dev->priv;
-
- /* enter loop that stays in interrupt code until nothing to service */
- do {
- serviced = 0;
-
- uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
- uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
- uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
- uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
-
- if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
- && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
- && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
- /* not for us */
- return (rc);
- }
-
- /* get and clear controller status interrupts */
- /* look at MAL and EMAC error interrupts */
- if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
- /* we have a MAL error interrupt */
- mal_isr = mfdcr(malesr);
- mal_err(dev, mal_isr, uic_mal_err,
- MAL_UIC_DEF, MAL_UIC_ERR);
-
- /* clear MAL error interrupt status bits */
- mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
- UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
-
- return -1;
- }
-
- /* look for EMAC errors */
- if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
- emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
- emac_err(dev, emac_isr);
-
- /* clear EMAC error interrupt status bits */
- mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
- mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
-
- return -1;
- }
-
- /* handle MAX TX EOB interrupt from a tx */
- if (uic_mal & UIC_MAL_TXEOB) {
- /* clear MAL interrupt status bits */
- mal_eob = mfdcr(maltxeobisr);
- mtdcr(maltxeobisr, mal_eob);
- mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
-
- /* indicate that we serviced an interrupt */
- serviced = 1;
- rc = 0;
- }
-
- /* handle MAL RX EOB interupt from a receive */
- /* check for EOB on valid channels */
- if (uic_mal & UIC_MAL_RXEOB) {
- mal_eob = mfdcr(malrxeobisr);
- if (mal_eob &
- (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
- /* push packet to upper layer */
- enet_rcv(dev, emac_isr);
-
- /* clear MAL interrupt status bits */
- mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
-
- /* indicate that we serviced an interrupt */
- serviced = 1;
- rc = 0;
- }
- }
- } while (serviced);
-
- return (rc);
-}
-
-/*-----------------------------------------------------------------------------+
- * MAL Error Routine
- *-----------------------------------------------------------------------------*/
-static void mal_err (struct eth_device *dev, unsigned long isr,
- unsigned long uic, unsigned long maldef,
- unsigned long mal_errr)
-{
- EMAC_4XX_HW_PST hw_p = dev->priv;
-
- mtdcr (malesr, isr); /* clear interrupt */
-
- /* clear DE interrupt */
- mtdcr (maltxdeir, 0xC0000000);
- mtdcr (malrxdeir, 0x80000000);
-
-#ifdef INFO_4XX_ENET
- printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
-#endif
-
- eth_init (hw_p->bis); /* start again... */
-}
-
-/*-----------------------------------------------------------------------------+
- * EMAC Error Routine
- *-----------------------------------------------------------------------------*/
-static void emac_err (struct eth_device *dev, unsigned long isr)
-{
- EMAC_4XX_HW_PST hw_p = dev->priv;
-
- printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
- out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
-}
-
-/*-----------------------------------------------------------------------------+
- * enet_rcv() handles the ethernet receive data
- *-----------------------------------------------------------------------------*/
-static void enet_rcv (struct eth_device *dev, unsigned long malisr)
-{
- struct enet_frame *ef_ptr;
- unsigned long data_len;
- unsigned long rx_eob_isr;
- EMAC_4XX_HW_PST hw_p = dev->priv;
-
- int handled = 0;
- int i;
- int loop_count = 0;
-
- rx_eob_isr = mfdcr (malrxeobisr);
- if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
- /* clear EOB */
- mtdcr (malrxeobisr, rx_eob_isr);
-
- /* EMAC RX done */
- while (1) { /* do all */
- i = hw_p->rx_slot;
-
- if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
- || (loop_count >= NUM_RX_BUFF))
- break;
-
- loop_count++;
- handled++;
- data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
- if (data_len) {
- if (data_len > ENET_MAX_MTU) /* Check len */
- data_len = 0;
- else {
- if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
- data_len = 0;
- hw_p->stats.rx_err_log[hw_p->
- rx_err_index]
- = hw_p->rx[i].ctrl;
- hw_p->rx_err_index++;
- if (hw_p->rx_err_index ==
- MAX_ERR_LOG)
- hw_p->rx_err_index =
- 0;
- } /* emac_erros */
- } /* data_len < max mtu */
- } /* if data_len */
- if (!data_len) { /* no data */
- hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
-
- hw_p->stats.data_len_err++; /* Error at Rx */
- }
-
- /* !data_len */
- /* AS.HARNOIS */
- /* Check if user has already eaten buffer */
- /* if not => ERROR */
- else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
- if (hw_p->is_receiving)
- printf ("ERROR : Receive buffers are full!\n");
- break;
- } else {
- hw_p->stats.rx_frames++;
- hw_p->stats.rx += data_len;
- ef_ptr = (struct enet_frame *) hw_p->rx[i].
- data_ptr;
-#ifdef INFO_4XX_ENET
- hw_p->stats.pkts_rx++;
-#endif
- /* AS.HARNOIS
- * use ring buffer
- */
- hw_p->rx_ready[hw_p->rx_i_index] = i;
- hw_p->rx_i_index++;
- if (NUM_RX_BUFF == hw_p->rx_i_index)
- hw_p->rx_i_index = 0;
-
- hw_p->rx_slot++;
- if (NUM_RX_BUFF == hw_p->rx_slot)
- hw_p->rx_slot = 0;
-
- /* AS.HARNOIS
- * free receive buffer only when
- * buffer has been handled (eth_rx)
- rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
- */
- } /* if data_len */
- } /* while */
- } /* if EMACK_RXCHL */
-}
-
-
-static int ppc_4xx_eth_rx (struct eth_device *dev)
-{
- int length;
- int user_index;
- unsigned long msr;
- EMAC_4XX_HW_PST hw_p = dev->priv;
-
- hw_p->is_receiving = 1; /* tell driver */
-
- for (;;) {
- /* AS.HARNOIS
- * use ring buffer and
- * get index from rx buffer desciptor queue
- */
- user_index = hw_p->rx_ready[hw_p->rx_u_index];
- if (user_index == -1) {
- length = -1;
- break; /* nothing received - leave for() loop */
- }
-
- msr = mfmsr ();
- mtmsr (msr & ~(MSR_EE));
-
- length = hw_p->rx[user_index].data_len & 0x0fff;
-
- /* Pass the packet up to the protocol layers. */
- /* NetReceive(NetRxPackets[rxIdx], length - 4); */
- /* NetReceive(NetRxPackets[i], length); */
- invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
- (u32)hw_p->rx[user_index].data_ptr +
- length - 4);
- NetReceive (NetRxPackets[user_index], length - 4);
- /* Free Recv Buffer */
- hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
- /* Free rx buffer descriptor queue */
- hw_p->rx_ready[hw_p->rx_u_index] = -1;
- hw_p->rx_u_index++;
- if (NUM_RX_BUFF == hw_p->rx_u_index)
- hw_p->rx_u_index = 0;
-
-#ifdef INFO_4XX_ENET
- hw_p->stats.pkts_handled++;
-#endif
-
- mtmsr (msr); /* Enable IRQ's */
- }
-
- hw_p->is_receiving = 0; /* tell driver */
-
- return length;
-}
-
-int ppc_4xx_eth_initialize (bd_t * bis)
-{
- static int virgin = 0;
- struct eth_device *dev;
- int eth_num = 0;
- EMAC_4XX_HW_PST hw = NULL;
- u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
- u32 hw_addr[4];
- u32 mal_ier;
-
-#if defined(CONFIG_440GX)
- unsigned long pfc1;
-
- mfsdr (sdr_pfc1, pfc1);
- pfc1 &= ~(0x01e00000);
- pfc1 |= 0x01200000;
- mtsdr (sdr_pfc1, pfc1);
-#endif
-
- /* first clear all mac-addresses */
- for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
- memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
-
- for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
- switch (eth_num) {
- default: /* fall through */
- case 0:
- memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
- bis->bi_enetaddr, 6);
- hw_addr[eth_num] = 0x0;
- break;
-#ifdef CONFIG_HAS_ETH1
- case 1:
- memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
- bis->bi_enet1addr, 6);
- hw_addr[eth_num] = 0x100;
- break;
-#endif
-#ifdef CONFIG_HAS_ETH2
- case 2:
- memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
- bis->bi_enet2addr, 6);
-#if defined(CONFIG_460GT)
- hw_addr[eth_num] = 0x300;
-#else
- hw_addr[eth_num] = 0x400;
-#endif
- break;
-#endif
-#ifdef CONFIG_HAS_ETH3
- case 3:
- memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
- bis->bi_enet3addr, 6);
-#if defined(CONFIG_460GT)
- hw_addr[eth_num] = 0x400;
-#else
- hw_addr[eth_num] = 0x600;
-#endif
- break;
-#endif
- }
- }
-
- /* set phy num and mode */
- bis->bi_phynum[0] = CONFIG_PHY_ADDR;
- bis->bi_phymode[0] = 0;
-
-#if defined(CONFIG_PHY1_ADDR)
- bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
- bis->bi_phymode[1] = 0;
-#endif
-#if defined(CONFIG_440GX)
- bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
- bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
- bis->bi_phymode[2] = 2;
- bis->bi_phymode[3] = 2;
-#endif
-
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_405EX)
- ppc_4xx_eth_setup_bridge(0, bis);
-#endif
-
- for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
- /*
- * See if we can actually bring up the interface,
- * otherwise, skip it
- */
- if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
- bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
- continue;
- }
-
- /* Allocate device structure */
- dev = (struct eth_device *) malloc (sizeof (*dev));
- if (dev == NULL) {
- printf ("ppc_4xx_eth_initialize: "
- "Cannot allocate eth_device %d\n", eth_num);
- return (-1);
- }
- memset(dev, 0, sizeof(*dev));
-
- /* Allocate our private use data */
- hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
- if (hw == NULL) {
- printf ("ppc_4xx_eth_initialize: "
- "Cannot allocate private hw data for eth_device %d",
- eth_num);
- free (dev);
- return (-1);
- }
- memset(hw, 0, sizeof(*hw));
-
- hw->hw_addr = hw_addr[eth_num];
- memcpy (dev->enetaddr, ethaddr[eth_num], 6);
- hw->devnum = eth_num;
- hw->print_speed = 1;
-
- sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
- dev->priv = (void *) hw;
- dev->init = ppc_4xx_eth_init;
- dev->halt = ppc_4xx_eth_halt;
- dev->send = ppc_4xx_eth_send;
- dev->recv = ppc_4xx_eth_rx;
-
- if (0 == virgin) {
- /* set the MAL IER ??? names may change with new spec ??? */
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_405EX)
- mal_ier =
- MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
- MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
-#else
- mal_ier =
- MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
- MAL_IER_OPBE | MAL_IER_PLBE;
-#endif
- mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
- mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
- mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
- mtdcr (malier, mal_ier);
-
- /* install MAL interrupt handler */
- irq_install_handler (VECNUM_MAL_SERR,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_MAL_TXEOB,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_MAL_RXEOB,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_MAL_TXDE,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_MAL_RXDE,
- (interrupt_handler_t *) enetInt,
- dev);
- virgin = 1;
- }
-
-#if defined(CONFIG_NET_MULTI)
- eth_register (dev);
-#else
- emac0_dev = dev;
-#endif
-
-#if defined(CONFIG_NET_MULTI)
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- miiphy_register (dev->name,
- emac4xx_miiphy_read, emac4xx_miiphy_write);
-#endif
-#endif
- } /* end for each supported device */
-
- return 0;
-}
-
-#if !defined(CONFIG_NET_MULTI)
-void eth_halt (void) {
- if (emac0_dev) {
- ppc_4xx_eth_halt(emac0_dev);
- free(emac0_dev);
- emac0_dev = NULL;
- }
-}
-
-int eth_init (bd_t *bis)
-{
- ppc_4xx_eth_initialize(bis);
- if (emac0_dev) {
- return ppc_4xx_eth_init(emac0_dev, bis);
- } else {
- printf("ERROR: ethaddr not set!\n");
- return -1;
- }
-}
-
-int eth_send(volatile void *packet, int length)
-{
- return (ppc_4xx_eth_send(emac0_dev, packet, length));
-}
-
-int eth_rx(void)
-{
- return (ppc_4xx_eth_rx(emac0_dev));
-}
-
-int emac4xx_miiphy_initialize (bd_t * bis)
-{
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- miiphy_register ("ppc_4xx_eth0",
- emac4xx_miiphy_read, emac4xx_miiphy_write);
-#endif
-
- return 0;
-}
-#endif /* !defined(CONFIG_NET_MULTI) */
-
-#endif
diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
new file mode 100644
index 0000000..1e3e20d
--- /dev/null
+++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -0,0 +1,1233 @@
+/*
+ * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+ * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
+ * DDR2 controller (non Denali Core). Those currently are:
+ *
+ * 405: 405EX
+ * 440/460: 440SP/440SPe/460EX/460GT/460SX
+ *
+ * (C) Copyright 2008 Applied Micro Circuits Corporation
+ * Adam Graham <agraham@amcc.com>
+ *
+ * (C) Copyright 2007-2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * COPYRIGHT AMCC CORPORATION 2004
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#undef DEBUG
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+
+/*
+ * Only compile the DDR auto-calibration code for NOR boot and
+ * not for NAND boot (NAND SPL and NAND U-Boot - NUB)
+ */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+
+#define MAXBXCF 4
+#define SDRAM_RXBAS_SHIFT_1M 20
+
+#if defined(CONFIG_SYS_DECREMENT_PATTERNS)
+#define NUMMEMTESTS 24
+#else
+#define NUMMEMTESTS 8
+#endif /* CONFIG_SYS_DECREMENT_PATTERNS */
+#define NUMLOOPS 1 /* configure as you deem approporiate */
+#define NUMMEMWORDS 16
+
+/* Private Structure Definitions */
+
+struct autocal_regs {
+ u32 rffd;
+ u32 rqfd;
+};
+
+struct ddrautocal {
+ u32 rffd;
+ u32 rffd_min;
+ u32 rffd_max;
+ u32 rffd_size;
+ u32 rqfd;
+ u32 rqfd_size;
+ u32 rdcc;
+ u32 flags;
+};
+
+struct sdram_timing {
+ u32 wrdtr;
+ u32 clktr;
+};
+
+struct sdram_timing_clks {
+ u32 wrdtr;
+ u32 clktr;
+ u32 rdcc;
+ u32 flags;
+};
+
+struct autocal_clks {
+ struct sdram_timing_clks clocks;
+ struct ddrautocal autocal;
+};
+
+/*--------------------------------------------------------------------------+
+ * Prototypes
+ *--------------------------------------------------------------------------*/
+#if defined(CONFIG_PPC4xx_DDR_METHOD_A)
+static u32 DQS_calibration_methodA(struct ddrautocal *);
+static u32 program_DQS_calibration_methodA(struct ddrautocal *);
+#else
+static u32 DQS_calibration_methodB(struct ddrautocal *);
+static u32 program_DQS_calibration_methodB(struct ddrautocal *);
+#endif
+static int short_mem_test(u32 *);
+
+/*
+ * To provide an interface for board specific config values in this common
+ * DDR setup code, we implement he "weak" default functions here. They return
+ * the default value back to the caller.
+ *
+ * Please see include/configs/yucca.h for an example fora board specific
+ * implementation.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+u32 __ddr_wrdtr(u32 default_val)
+{
+ return default_val;
+}
+u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
+
+u32 __ddr_clktr(u32 default_val)
+{
+ return default_val;
+}
+u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
+
+/*
+ * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
+ */
+void __spd_ddr_init_hang(void)
+{
+ hang();
+}
+void
+spd_ddr_init_hang(void) __attribute__((weak, alias("__spd_ddr_init_hang")));
+#endif /* defined(CONFIG_SPD_EEPROM) */
+
+ulong __ddr_scan_option(ulong default_val)
+{
+ return default_val;
+}
+ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option")));
+
+static u32 *get_membase(int bxcr_num)
+{
+ ulong bxcf;
+ u32 *membase;
+
+#if defined(SDRAM_R0BAS)
+ /* BAS from Memory Queue rank reg. */
+ membase =
+ (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
+ bxcf = 0; /* just to satisfy the compiler */
+#else
+ /* BAS from SDRAM_MBxCF mem rank reg. */
+ mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
+ membase = (u32 *)((bxcf & 0xfff80000) << 3);
+#endif
+
+ return membase;
+}
+
+static inline void ecc_clear_status_reg(void)
+{
+ mtsdram(SDRAM_ECCCR, 0xffffffff);
+#if defined(SDRAM_R0BAS)
+ mtdcr(SDRAM_ERRSTATLL, 0xffffffff);
+#endif
+}
+
+/*
+ * Reset and relock memory DLL after SDRAM_CLKTR change
+ */
+static inline void relock_memory_DLL(void)
+{
+ u32 reg;
+
+ mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE);
+
+ do {
+ mfsdram(SDRAM_MCSTAT, reg);
+ } while (!(reg & SDRAM_MCSTAT_MIC_COMP));
+
+ mfsdram(SDRAM_MCOPT2, reg);
+ mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE);
+}
+
+static int ecc_check_status_reg(void)
+{
+ u32 ecc_status;
+
+ /*
+ * Compare suceeded, now check
+ * if got ecc error. If got an
+ * ecc error, then don't count
+ * this as a passing value
+ */
+ mfsdram(SDRAM_ECCCR, ecc_status);
+ if (ecc_status != 0x00000000) {
+ /* clear on error */
+ ecc_clear_status_reg();
+ /* ecc check failure */
+ return 0;
+ }
+ ecc_clear_status_reg();
+ sync();
+
+ return 1;
+}
+
+/* return 1 if passes, 0 if fail */
+static int short_mem_test(u32 *base_address)
+{
+ int i, j, l;
+ u32 ecc_mode = 0;
+
+ ulong test[NUMMEMTESTS][NUMMEMWORDS] = {
+ /* 0 */ {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
+ /* 1 */ {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
+ /* 2 */ {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
+ /* 3 */ {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
+ /* 4 */ {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
+ /* 5 */ {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
+ /* 6 */ {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
+ /* 7 */ {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55},
+
+#if defined(CONFIG_SYS_DECREMENT_PATTERNS)
+ /* 8 */ {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff},
+ /* 9 */ {0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
+ 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
+ 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
+ 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe},
+ /* 10 */{0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
+ 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
+ 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
+ 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd},
+ /* 11 */{0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
+ 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
+ 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
+ 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc},
+ /* 12 */{0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
+ 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
+ 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
+ 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb},
+ /* 13 */{0xfffafffa, 0xfffafffa, 0xfffffffa, 0xfffafffa,
+ 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa,
+ 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa,
+ 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa},
+ /* 14 */{0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
+ 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
+ 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
+ 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9},
+ /* 15 */{0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
+ 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
+ 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
+ 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8},
+ /* 16 */{0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
+ 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
+ 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
+ 0xfff7ffff, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7},
+ /* 17 */{0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
+ 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
+ 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
+ 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7},
+ /* 18 */{0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
+ 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
+ 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
+ 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5},
+ /* 19 */{0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
+ 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
+ 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
+ 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4},
+ /* 20 */{0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
+ 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
+ 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
+ 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3},
+ /* 21 */{0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
+ 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
+ 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
+ 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2},
+ /* 22 */{0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
+ 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
+ 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
+ 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1},
+ /* 23 */{0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
+ 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
+ 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
+ 0xfff0fff0, 0xfff0fffe, 0xfff0fff0, 0xfff0fff0},
+#endif /* CONFIG_SYS_DECREMENT_PATTERNS */
+ };
+
+ mfsdram(SDRAM_MCOPT1, ecc_mode);
+ if ((ecc_mode & SDRAM_MCOPT1_MCHK_CHK_REP) ==
+ SDRAM_MCOPT1_MCHK_CHK_REP) {
+ ecc_clear_status_reg();
+ sync();
+ ecc_mode = 1;
+ } else {
+ ecc_mode = 0;
+ }
+
+ /*
+ * Run the short memory test.
+ */
+ for (i = 0; i < NUMMEMTESTS; i++) {
+ for (j = 0; j < NUMMEMWORDS; j++) {
+ base_address[j] = test[i][j];
+ ppcDcbf((ulong)&(base_address[j]));
+ }
+ sync();
+ for (l = 0; l < NUMLOOPS; l++) {
+ for (j = 0; j < NUMMEMWORDS; j++) {
+ if (base_address[j] != test[i][j]) {
+ ppcDcbf((u32)&(base_address[j]));
+ return 0;
+ } else {
+ if (ecc_mode) {
+ if (!ecc_check_status_reg())
+ return 0;
+ }
+ }
+ ppcDcbf((u32)&(base_address[j]));
+ } /* for (j = 0; j < NUMMEMWORDS; j++) */
+ sync();
+ } /* for (l=0; l<NUMLOOPS; l++) */
+ }
+
+ return 1;
+}
+
+#if defined(CONFIG_PPC4xx_DDR_METHOD_A)
+/*-----------------------------------------------------------------------------+
+| program_DQS_calibration_methodA.
++-----------------------------------------------------------------------------*/
+static u32 program_DQS_calibration_methodA(struct ddrautocal *ddrcal)
+{
+ u32 pass_result = 0;
+
+#ifdef DEBUG
+ ulong temp;
+
+ mfsdram(SDRAM_RDCC, temp);
+ debug("<%s>SDRAM_RDCC=0x%08x\n", __func__, temp);
+#endif
+
+ pass_result = DQS_calibration_methodA(ddrcal);
+
+ return pass_result;
+}
+
+/*
+ * DQS_calibration_methodA()
+ *
+ * Autocalibration Method A
+ *
+ * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros
+ * ARRAY [Entire FDBK Range] FDBK_Valid_Window; initialized to all zeros
+ * MEMWRITE(addr, expected_data);
+ * for (i = 0; i < Entire DQS Range; i++) { RQDC.RQFD
+ * for (j = 0; j < Entire FDBK Range; j++) { RFDC.RFFD
+ * MEMREAD(addr, actual_data);
+ * if (actual_data == expected_data) {
+ * DQS_Valid_Window[i] = 1; RQDC.RQFD
+ * FDBK_Valid_Window[i][j] = 1; RFDC.RFFD
+ * }
+ * }
+ * }
+ */
+static u32 DQS_calibration_methodA(struct ddrautocal *cal)
+{
+ ulong rfdc_reg;
+ ulong rffd;
+
+ ulong rqdc_reg;
+ ulong rqfd;
+
+ u32 *membase;
+ ulong bxcf;
+ int rqfd_average;
+ int bxcr_num;
+ int rffd_average;
+ int pass;
+ u32 passed = 0;
+
+ int in_window;
+ struct autocal_regs curr_win_min;
+ struct autocal_regs curr_win_max;
+ struct autocal_regs best_win_min;
+ struct autocal_regs best_win_max;
+ struct autocal_regs loop_win_min;
+ struct autocal_regs loop_win_max;
+
+#ifdef DEBUG
+ ulong temp;
+#endif
+ ulong rdcc;
+
+ char slash[] = "\\|/-\\|/-";
+ int loopi = 0;
+
+ /* start */
+ in_window = 0;
+
+ memset(&curr_win_min, 0, sizeof(curr_win_min));
+ memset(&curr_win_max, 0, sizeof(curr_win_max));
+ memset(&best_win_min, 0, sizeof(best_win_min));
+ memset(&best_win_max, 0, sizeof(best_win_max));
+ memset(&loop_win_min, 0, sizeof(loop_win_min));
+ memset(&loop_win_max, 0, sizeof(loop_win_max));
+
+ rdcc = 0;
+
+ /*
+ * Program RDCC register
+ * Read sample cycle auto-update enable
+ */
+ mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T1 | SDRAM_RDCC_RSAE_ENABLE);
+
+#ifdef DEBUG
+ mfsdram(SDRAM_RDCC, temp);
+ debug("<%s>SDRAM_RDCC=0x%x\n", __func__, temp);
+ mfsdram(SDRAM_RTSR, temp);
+ debug("<%s>SDRAM_RTSR=0x%x\n", __func__, temp);
+ mfsdram(SDRAM_FCSR, temp);
+ debug("<%s>SDRAM_FCSR=0x%x\n", __func__, temp);
+#endif
+
+ /*
+ * Program RQDC register
+ * Internal DQS delay mechanism enable
+ */
+ mtsdram(SDRAM_RQDC,
+ SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x00));
+
+#ifdef DEBUG
+ mfsdram(SDRAM_RQDC, temp);
+ debug("<%s>SDRAM_RQDC=0x%x\n", __func__, temp);
+#endif
+
+ /*
+ * Program RFDC register
+ * Set Feedback Fractional Oversample
+ * Auto-detect read sample cycle enable
+ */
+ mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE |
+ SDRAM_RFDC_RFOS_ENCODE(0) | SDRAM_RFDC_RFFD_ENCODE(0));
+
+#ifdef DEBUG
+ mfsdram(SDRAM_RFDC, temp);
+ debug("<%s>SDRAM_RFDC=0x%x\n", __func__, temp);
+#endif
+
+ putc(' ');
+ for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
+
+ mfsdram(SDRAM_RQDC, rqdc_reg);
+ rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
+ mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
+
+ putc('\b');
+ putc(slash[loopi++ % 8]);
+
+ curr_win_min.rffd = 0;
+ curr_win_max.rffd = 0;
+ in_window = 0;
+
+ for (rffd = 0, pass = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
+ mfsdram(SDRAM_RFDC, rfdc_reg);
+ rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
+ mtsdram(SDRAM_RFDC,
+ rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
+
+ for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
+ mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
+
+ /* Banks enabled */
+ if (bxcf & SDRAM_BXCF_M_BE_MASK) {
+ /* Bank is enabled */
+ membase = get_membase(bxcr_num);
+ pass = short_mem_test(membase);
+ } /* if bank enabled */
+ } /* for bxcr_num */
+
+ /* If this value passed update RFFD windows */
+ if (pass && !in_window) { /* at the start of window */
+ in_window = 1;
+ curr_win_min.rffd = curr_win_max.rffd = rffd;
+ curr_win_min.rqfd = curr_win_max.rqfd = rqfd;
+ mfsdram(SDRAM_RDCC, rdcc); /*record this value*/
+ } else if (!pass && in_window) { /* at end of window */
+ in_window = 0;
+ } else if (pass && in_window) { /* within the window */
+ curr_win_max.rffd = rffd;
+ curr_win_max.rqfd = rqfd;
+ }
+ /* else if (!pass && !in_window)
+ skip - no pass, not currently in a window */
+
+ if (in_window) {
+ if ((curr_win_max.rffd - curr_win_min.rffd) >
+ (best_win_max.rffd - best_win_min.rffd)) {
+ best_win_min.rffd = curr_win_min.rffd;
+ best_win_max.rffd = curr_win_max.rffd;
+
+ best_win_min.rqfd = curr_win_min.rqfd;
+ best_win_max.rqfd = curr_win_max.rqfd;
+ cal->rdcc = rdcc;
+ }
+ passed = 1;
+ }
+ } /* RFDC.RFFD */
+
+ /*
+ * save-off the best window results of the RFDC.RFFD
+ * for this RQDC.RQFD setting
+ */
+ /*
+ * if (just ended RFDC.RFDC loop pass window) >
+ * (prior RFDC.RFFD loop pass window)
+ */
+ if ((best_win_max.rffd - best_win_min.rffd) >
+ (loop_win_max.rffd - loop_win_min.rffd)) {
+ loop_win_min.rffd = best_win_min.rffd;
+ loop_win_max.rffd = best_win_max.rffd;
+ loop_win_min.rqfd = rqfd;
+ loop_win_max.rqfd = rqfd;
+ debug("RQFD.min 0x%08x, RQFD.max 0x%08x, "
+ "RFFD.min 0x%08x, RFFD.max 0x%08x\n",
+ loop_win_min.rqfd, loop_win_max.rqfd,
+ loop_win_min.rffd, loop_win_max.rffd);
+ }
+ } /* RQDC.RQFD */
+
+ putc('\b');
+
+ debug("\n");
+
+ if ((loop_win_min.rffd == 0) && (loop_win_max.rffd == 0) &&
+ (best_win_min.rffd == 0) && (best_win_max.rffd == 0) &&
+ (best_win_min.rqfd == 0) && (best_win_max.rqfd == 0)) {
+ passed = 0;
+ }
+
+ /*
+ * Need to program RQDC before RFDC.
+ */
+ debug("<%s> RQFD Min: 0x%x\n", __func__, loop_win_min.rqfd);
+ debug("<%s> RQFD Max: 0x%x\n", __func__, loop_win_max.rqfd);
+ rqfd_average = loop_win_max.rqfd;
+
+ if (rqfd_average < 0)
+ rqfd_average = 0;
+
+ if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
+ rqfd_average = SDRAM_RQDC_RQFD_MAX;
+
+ debug("<%s> RFFD average: 0x%08x\n", __func__, rqfd_average);
+ mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
+ SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
+
+ debug("<%s> RFFD Min: 0x%08x\n", __func__, loop_win_min.rffd);
+ debug("<%s> RFFD Max: 0x%08x\n", __func__, loop_win_max.rffd);
+ rffd_average = ((loop_win_min.rffd + loop_win_max.rffd) / 2);
+
+ if (rffd_average < 0)
+ rffd_average = 0;
+
+ if (rffd_average > SDRAM_RFDC_RFFD_MAX)
+ rffd_average = SDRAM_RFDC_RFFD_MAX;
+
+ debug("<%s> RFFD average: 0x%08x\n", __func__, rffd_average);
+ mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
+
+ /* if something passed, then return the size of the largest window */
+ if (passed != 0) {
+ passed = loop_win_max.rffd - loop_win_min.rffd;
+ cal->rqfd = rqfd_average;
+ cal->rffd = rffd_average;
+ cal->rffd_min = loop_win_min.rffd;
+ cal->rffd_max = loop_win_max.rffd;
+ }
+
+ return (u32)passed;
+}
+
+#else /* !defined(CONFIG_PPC4xx_DDR_METHOD_A) */
+
+/*-----------------------------------------------------------------------------+
+| program_DQS_calibration_methodB.
++-----------------------------------------------------------------------------*/
+static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal)
+{
+ u32 pass_result = 0;
+
+#ifdef DEBUG
+ ulong temp;
+#endif
+
+ /*
+ * Program RDCC register
+ * Read sample cycle auto-update enable
+ */
+ mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T2 | SDRAM_RDCC_RSAE_ENABLE);
+
+#ifdef DEBUG
+ mfsdram(SDRAM_RDCC, temp);
+ debug("<%s>SDRAM_RDCC=0x%08x\n", __func__, temp);
+#endif
+
+ /*
+ * Program RQDC register
+ * Internal DQS delay mechanism enable
+ */
+ mtsdram(SDRAM_RQDC,
+#if defined(CONFIG_DDR_RQDC_START_VAL)
+ SDRAM_RQDC_RQDE_ENABLE |
+ SDRAM_RQDC_RQFD_ENCODE(CONFIG_DDR_RQDC_START_VAL));
+#else
+ SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x38));
+#endif
+
+#ifdef DEBUG
+ mfsdram(SDRAM_RQDC, temp);
+ debug("<%s>SDRAM_RQDC=0x%08x\n", __func__, temp);
+#endif
+
+ /*
+ * Program RFDC register
+ * Set Feedback Fractional Oversample
+ * Auto-detect read sample cycle enable
+ */
+ mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE |
+ SDRAM_RFDC_RFOS_ENCODE(0) |
+ SDRAM_RFDC_RFFD_ENCODE(0));
+
+#ifdef DEBUG
+ mfsdram(SDRAM_RFDC, temp);
+ debug("<%s>SDRAM_RFDC=0x%08x\n", __func__, temp);
+#endif
+
+ pass_result = DQS_calibration_methodB(ddrcal);
+
+ return pass_result;
+}
+
+/*
+ * DQS_calibration_methodB()
+ *
+ * Autocalibration Method B
+ *
+ * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros
+ * ARRAY [Entire Feedback Range] FDBK_Valid_Window; initialized to all zeros
+ * MEMWRITE(addr, expected_data);
+ * Initialialize the DQS delay to 80 degrees (MCIF0_RRQDC[RQFD]=0x38).
+ *
+ * for (j = 0; j < Entire Feedback Range; j++) {
+ * MEMREAD(addr, actual_data);
+ * if (actual_data == expected_data) {
+ * FDBK_Valid_Window[j] = 1;
+ * }
+ * }
+ *
+ * Set MCIF0_RFDC[RFFD] to the middle of the FDBK_Valid_Window.
+ *
+ * for (i = 0; i < Entire DQS Range; i++) {
+ * MEMREAD(addr, actual_data);
+ * if (actual_data == expected_data) {
+ * DQS_Valid_Window[i] = 1;
+ * }
+ * }
+ *
+ * Set MCIF0_RRQDC[RQFD] to the middle of the DQS_Valid_Window.
+ */
+/*-----------------------------------------------------------------------------+
+| DQS_calibration_methodB.
++-----------------------------------------------------------------------------*/
+static u32 DQS_calibration_methodB(struct ddrautocal *cal)
+{
+ ulong rfdc_reg;
+ ulong rffd;
+
+ ulong rqdc_reg;
+ ulong rqfd;
+
+ ulong rdcc;
+
+ u32 *membase;
+ ulong bxcf;
+ int rqfd_average;
+ int bxcr_num;
+ int rffd_average;
+ int pass;
+ uint passed = 0;
+
+ int in_window;
+ u32 curr_win_min, curr_win_max;
+ u32 best_win_min, best_win_max;
+ u32 size = 0;
+
+ /*------------------------------------------------------------------
+ | Test to determine the best read clock delay tuning bits.
+ |
+ | Before the DDR controller can be used, the read clock delay needs to
+ | be set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
+ | This value cannot be hardcoded into the program because it changes
+ | depending on the board's setup and environment.
+ | To do this, all delay values are tested to see if they
+ | work or not. By doing this, you get groups of fails with groups of
+ | passing values. The idea is to find the start and end of a passing
+ | window and take the center of it to use as the read clock delay.
+ |
+ | A failure has to be seen first so that when we hit a pass, we know
+ | that it is truely the start of the window. If we get passing values
+ | to start off with, we don't know if we are at the start of the window
+ |
+ | The code assumes that a failure will always be found.
+ | If a failure is not found, there is no easy way to get the middle
+ | of the passing window. I guess we can pretty much pick any value
+ | but some values will be better than others. Since the lowest speed
+ | we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
+ | from experimentation it is safe to say you will always have a failure
+ +-----------------------------------------------------------------*/
+
+ debug("\n\n");
+
+ in_window = 0;
+ rdcc = 0;
+
+ curr_win_min = curr_win_max = 0;
+ best_win_min = best_win_max = 0;
+ for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
+ mfsdram(SDRAM_RFDC, rfdc_reg);
+ rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
+ mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
+
+ pass = 1;
+ for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
+ mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
+
+ /* Banks enabled */
+ if (bxcf & SDRAM_BXCF_M_BE_MASK) {
+ /* Bank is enabled */
+ membase = get_membase(bxcr_num);
+ pass &= short_mem_test(membase);
+ } /* if bank enabled */
+ } /* for bxcf_num */
+
+ /* If this value passed */
+ if (pass && !in_window) { /* start of passing window */
+ in_window = 1;
+ curr_win_min = curr_win_max = rffd;
+ mfsdram(SDRAM_RDCC, rdcc); /* record this value */
+ } else if (!pass && in_window) { /* end passing window */
+ in_window = 0;
+ } else if (pass && in_window) { /* within the passing window */
+ curr_win_max = rffd;
+ }
+
+ if (in_window) {
+ if ((curr_win_max - curr_win_min) >
+ (best_win_max - best_win_min)) {
+ best_win_min = curr_win_min;
+ best_win_max = curr_win_max;
+ cal->rdcc = rdcc;
+ }
+ passed = 1;
+ }
+ } /* for rffd */
+
+ if ((best_win_min == 0) && (best_win_max == 0))
+ passed = 0;
+ else
+ size = best_win_max - best_win_min;
+
+ debug("RFFD Min: 0x%x\n", best_win_min);
+ debug("RFFD Max: 0x%x\n", best_win_max);
+ rffd_average = ((best_win_min + best_win_max) / 2);
+
+ cal->rffd_min = best_win_min;
+ cal->rffd_max = best_win_max;
+
+ if (rffd_average < 0)
+ rffd_average = 0;
+
+ if (rffd_average > SDRAM_RFDC_RFFD_MAX)
+ rffd_average = SDRAM_RFDC_RFFD_MAX;
+
+ mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
+
+ rffd = rffd_average;
+ in_window = 0;
+
+ curr_win_min = curr_win_max = 0;
+ best_win_min = best_win_max = 0;
+ for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
+ mfsdram(SDRAM_RQDC, rqdc_reg);
+ rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
+ mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
+
+ pass = 1;
+ for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
+
+ mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
+
+ /* Banks enabled */
+ if (bxcf & SDRAM_BXCF_M_BE_MASK) {
+ /* Bank is enabled */
+ membase = get_membase(bxcr_num);
+ pass &= short_mem_test(membase);
+ } /* if bank enabled */
+ } /* for bxcf_num */
+
+ /* If this value passed */
+ if (pass && !in_window) {
+ in_window = 1;
+ curr_win_min = curr_win_max = rqfd;
+ } else if (!pass && in_window) {
+ in_window = 0;
+ } else if (pass && in_window) {
+ curr_win_max = rqfd;
+ }
+
+ if (in_window) {
+ if ((curr_win_max - curr_win_min) >
+ (best_win_max - best_win_min)) {
+ best_win_min = curr_win_min;
+ best_win_max = curr_win_max;
+ }
+ passed = 1;
+ }
+ } /* for rqfd */
+
+ if ((best_win_min == 0) && (best_win_max == 0))
+ passed = 0;
+
+ debug("RQFD Min: 0x%x\n", best_win_min);
+ debug("RQFD Max: 0x%x\n", best_win_max);
+ rqfd_average = ((best_win_min + best_win_max) / 2);
+
+ if (rqfd_average < 0)
+ rqfd_average = 0;
+
+ if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
+ rqfd_average = SDRAM_RQDC_RQFD_MAX;
+
+ mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
+ SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
+
+ mfsdram(SDRAM_RQDC, rqdc_reg);
+ mfsdram(SDRAM_RFDC, rfdc_reg);
+
+ /*
+ * Need to program RQDC before RFDC. The value is read above.
+ * That is the reason why auto cal not work.
+ * See, comments below.
+ */
+ mtsdram(SDRAM_RQDC, rqdc_reg);
+ mtsdram(SDRAM_RFDC, rfdc_reg);
+
+ debug("RQDC: 0x%08X\n", rqdc_reg);
+ debug("RFDC: 0x%08X\n", rfdc_reg);
+
+ /* if something passed, then return the size of the largest window */
+ if (passed != 0) {
+ passed = size;
+ cal->rqfd = rqfd_average;
+ cal->rffd = rffd_average;
+ }
+
+ return (uint)passed;
+}
+#endif /* defined(CONFIG_PPC4xx_DDR_METHOD_A) */
+
+/*
+ * Default table for DDR auto-calibration of all
+ * possible WRDTR and CLKTR values.
+ * Table format is:
+ * {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]}
+ *
+ * Table is terminated with {-1, -1} value pair.
+ *
+ * Board vendors can specify their own board specific subset of
+ * known working {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]} value
+ * pairs via a board defined ddr_scan_option() function.
+ */
+struct sdram_timing full_scan_options[] = {
+ {0, 0}, {0, 1}, {0, 2}, {0, 3},
+ {1, 0}, {1, 1}, {1, 2}, {1, 3},
+ {2, 0}, {2, 1}, {2, 2}, {2, 3},
+ {3, 0}, {3, 1}, {3, 2}, {3, 3},
+ {4, 0}, {4, 1}, {4, 2}, {4, 3},
+ {5, 0}, {5, 1}, {5, 2}, {5, 3},
+ {6, 0}, {6, 1}, {6, 2}, {6, 3},
+ {-1, -1}
+};
+
+/*---------------------------------------------------------------------------+
+| DQS_calibration.
++----------------------------------------------------------------------------*/
+u32 DQS_autocalibration(void)
+{
+ u32 wdtr;
+ u32 clkp;
+ u32 result = 0;
+ u32 best_result = 0;
+ u32 best_rdcc;
+ struct ddrautocal ddrcal;
+ struct autocal_clks tcal;
+ ulong rfdc_reg;
+ ulong rqdc_reg;
+ u32 val;
+ int verbose_lvl = 0;
+ char *str;
+ char slash[] = "\\|/-\\|/-";
+ int loopi = 0;
+ struct sdram_timing *scan_list;
+
+#if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
+ int i;
+ char tmp[64]; /* long enough for environment variables */
+#endif
+
+ memset(&tcal, 0, sizeof(tcal));
+
+ ddr_scan_option((ulong)full_scan_options);
+
+ scan_list =
+ (struct sdram_timing *)ddr_scan_option((ulong)full_scan_options);
+
+ mfsdram(SDRAM_MCOPT1, val);
+ if ((val & SDRAM_MCOPT1_MCHK_CHK_REP) == SDRAM_MCOPT1_MCHK_CHK_REP)
+ str = "ECC Auto calibration -";
+ else
+ str = "Auto calibration -";
+
+ puts(str);
+
+#if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
+ i = getenv_r("autocalib", tmp, sizeof(tmp));
+ if (i < 0)
+ strcpy(tmp, CONFIG_AUTOCALIB);
+
+ if (strcmp(tmp, "final") == 0) {
+ /* display the final autocalibration results only */
+ verbose_lvl = 1;
+ } else if (strcmp(tmp, "loop") == 0) {
+ /* display summary autocalibration info per iteration */
+ verbose_lvl = 2;
+ } else if (strcmp(tmp, "display") == 0) {
+ /* display full debug autocalibration window info. */
+ verbose_lvl = 3;
+ }
+#endif /* (DEBUG_PPC4xx_DDR_AUTOCALIBRATION) */
+
+ best_rdcc = (SDRAM_RDCC_RDSS_T4 >> 30);
+
+ while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) {
+ wdtr = scan_list->wrdtr;
+ clkp = scan_list->clktr;
+
+ mfsdram(SDRAM_WRDTR, val);
+ val &= ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK);
+ mtsdram(SDRAM_WRDTR, (val |
+ ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | (wdtr << 25))));
+
+ mtsdram(SDRAM_CLKTR, clkp << 30);
+
+ relock_memory_DLL();
+
+ putc('\b');
+ putc(slash[loopi++ % 8]);
+
+#ifdef DEBUG
+ debug("\n");
+ debug("*** --------------\n");
+ mfsdram(SDRAM_WRDTR, val);
+ debug("*** SDRAM_WRDTR set to 0x%08x\n", val);
+ mfsdram(SDRAM_CLKTR, val);
+ debug("*** SDRAM_CLKTR set to 0x%08x\n", val);
+#endif
+
+ debug("\n");
+ if (verbose_lvl > 2) {
+ printf("*** SDRAM_WRDTR (wdtr) set to %d\n", wdtr);
+ printf("*** SDRAM_CLKTR (clkp) set to %d\n", clkp);
+ }
+
+ memset(&ddrcal, 0, sizeof(ddrcal));
+
+ /*
+ * DQS calibration.
+ */
+ /*
+ * program_DQS_calibration_method[A|B]() returns 0 if no
+ * passing RFDC.[RFFD] window is found or returns the size
+ * of the best passing window; in the case of a found passing
+ * window, the ddrcal will contain the values of the best
+ * window RQDC.[RQFD] and RFDC.[RFFD].
+ */
+
+ /*
+ * Call PPC4xx SDRAM DDR autocalibration methodA or methodB.
+ * Default is methodB.
+ * Defined the autocalibration method in the board specific
+ * header file.
+ * Please see include/configs/kilauea.h for an example for
+ * a board specific implementation.
+ */
+#if defined(CONFIG_PPC4xx_DDR_METHOD_A)
+ result = program_DQS_calibration_methodA(&ddrcal);
+#else
+ result = program_DQS_calibration_methodB(&ddrcal);
+#endif
+
+ sync();
+
+ /*
+ * Clear potential errors resulting from auto-calibration.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
+ val = ddrcal.rdcc; /* RDCC from the best passing window */
+
+ udelay(100);
+
+ if (verbose_lvl > 1) {
+ char *tstr;
+ switch ((val >> 30)) {
+ case 0:
+ if (result != 0)
+ tstr = "T1";
+ else
+ tstr = "N/A";
+ break;
+ case 1:
+ tstr = "T2";
+ break;
+ case 2:
+ tstr = "T3";
+ break;
+ case 3:
+ tstr = "T4";
+ break;
+ default:
+ tstr = "unknown";
+ break;
+ }
+ printf("** WRDTR(%d) CLKTR(%d), Wind (%d), best (%d), "
+ "max-min(0x%04x)(0x%04x), RDCC: %s\n",
+ wdtr, clkp, result, best_result,
+ ddrcal.rffd_min, ddrcal.rffd_max, tstr);
+ }
+
+ /*
+ * The DQS calibration "result" is either "0"
+ * if no passing window was found, or is the
+ * size of the RFFD passing window.
+ */
+ if (result != 0) {
+ tcal.autocal.flags = 1;
+ debug("*** (%d)(%d) result passed window size: 0x%08x, "
+ "rqfd = 0x%08x, rffd = 0x%08x, rdcc = 0x%08x\n",
+ wdtr, clkp, result, ddrcal.rqfd,
+ ddrcal.rffd, ddrcal.rdcc);
+ /*
+ * Save the SDRAM_WRDTR and SDRAM_CLKTR
+ * settings for the largest returned
+ * RFFD passing window size.
+ */
+ if (result > best_result) {
+ /*
+ * want the lowest Read Sample Cycle Select
+ */
+ val = (val & SDRAM_RDCC_RDSS_MASK) >> 30;
+ debug("*** (%d) (%d) current_rdcc, best_rdcc\n",
+ val, best_rdcc);
+ if (val <= best_rdcc) {
+ best_rdcc = val;
+ tcal.clocks.wrdtr = wdtr;
+ tcal.clocks.clktr = clkp;
+ tcal.clocks.rdcc = (val << 30);
+ tcal.autocal.rqfd = ddrcal.rqfd;
+ tcal.autocal.rffd = ddrcal.rffd;
+ best_result = result;
+
+ if (verbose_lvl > 2) {
+ printf("** (%d)(%d) "
+ "best result: 0x%04x\n",
+ wdtr, clkp,
+ best_result);
+ printf("** (%d)(%d) "
+ "best WRDTR: 0x%04x\n",
+ wdtr, clkp,
+ tcal.clocks.wrdtr);
+ printf("** (%d)(%d) "
+ "best CLKTR: 0x%04x\n",
+ wdtr, clkp,
+ tcal.clocks.clktr);
+ printf("** (%d)(%d) "
+ "best RQDC: 0x%04x\n",
+ wdtr, clkp,
+ tcal.autocal.rqfd);
+ printf("** (%d)(%d) "
+ "best RFDC: 0x%04x\n",
+ wdtr, clkp,
+ tcal.autocal.rffd);
+ printf("** (%d)(%d) "
+ "best RDCC: 0x%08x\n",
+ wdtr, clkp,
+ (u32)tcal.clocks.rdcc);
+ mfsdram(SDRAM_RTSR, val);
+ printf("** (%d)(%d) best "
+ "loop RTSR: 0x%08x\n",
+ wdtr, clkp, val);
+ mfsdram(SDRAM_FCSR, val);
+ printf("** (%d)(%d) best "
+ "loop FCSR: 0x%08x\n",
+ wdtr, clkp, val);
+ }
+ } /* if (val <= best_rdcc) */
+ } /* if (result >= best_result) */
+ } /* if (result != 0) */
+ scan_list++;
+ } /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */
+
+ if (tcal.autocal.flags == 1) {
+ if (verbose_lvl > 0) {
+ printf("*** --------------\n");
+ printf("*** best_result window size: %d\n",
+ best_result);
+ printf("*** best_result WRDTR: 0x%04x\n",
+ tcal.clocks.wrdtr);
+ printf("*** best_result CLKTR: 0x%04x\n",
+ tcal.clocks.clktr);
+ printf("*** best_result RQFD: 0x%04x\n",
+ tcal.autocal.rqfd);
+ printf("*** best_result RFFD: 0x%04x\n",
+ tcal.autocal.rffd);
+ printf("*** best_result RDCC: 0x%04x\n",
+ tcal.clocks.rdcc);
+ printf("*** --------------\n");
+ printf("\n");
+ }
+
+ /*
+ * if got best passing result window, then lock in the
+ * best CLKTR, WRDTR, RQFD, and RFFD values
+ */
+ mfsdram(SDRAM_WRDTR, val);
+ mtsdram(SDRAM_WRDTR, (val &
+ ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
+ ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC |
+ (tcal.clocks.wrdtr << 25)));
+
+ mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30);
+
+ relock_memory_DLL();
+
+ mfsdram(SDRAM_RQDC, rqdc_reg);
+ rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
+ mtsdram(SDRAM_RQDC, rqdc_reg |
+ SDRAM_RQDC_RQFD_ENCODE(tcal.autocal.rqfd));
+
+ mfsdram(SDRAM_RQDC, rqdc_reg);
+ debug("*** best_result: read value SDRAM_RQDC 0x%08x\n",
+ rqdc_reg);
+
+ mfsdram(SDRAM_RFDC, rfdc_reg);
+ rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
+ mtsdram(SDRAM_RFDC, rfdc_reg |
+ SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd));
+
+ mfsdram(SDRAM_RFDC, rfdc_reg);
+ debug("*** best_result: read value SDRAM_RFDC 0x%08x\n",
+ rfdc_reg);
+ mfsdram(SDRAM_RDCC, val);
+ debug("*** SDRAM_RDCC 0x%08x\n", val);
+ } else {
+ /*
+ * no valid windows were found
+ */
+ printf("DQS memory calibration window can not be determined, "
+ "terminating u-boot.\n");
+ ppc4xx_ibm_ddr2_register_dump();
+ spd_ddr_init_hang();
+ }
+
+ blank_string(strlen(str));
+
+ return 0;
+}
+#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
+u32 DQS_autocalibration(void)
+{
+ return 0;
+}
+#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
+#endif /* defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index c28c7ac..e8871fc 100644
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -108,12 +108,12 @@ void pci_405gp_init(struct pci_controller *hose)
bd_t *bd = gd->bd;
unsigned short temp_short;
- unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
+ unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
char *ptmla_str, *ptmms_str;
#endif
- unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
- unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
+ unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
+ unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
@@ -268,25 +268,25 @@ void pci_405gp_init(struct pci_controller *hose)
/*
* Insert Subsystem Vendor and Device ID
*/
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
+ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
#ifdef CONFIG_CPCI405
if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
+ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
else
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
+ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
#else
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
+ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
#endif
/*
* Insert Class-code
*/
-#ifdef CFG_PCI_CLASSCODE
- pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
-#endif /* CFG_PCI_CLASSCODE */
+#ifdef CONFIG_SYS_PCI_CLASSCODE
+ pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
+#endif /* CONFIG_SYS_PCI_CLASSCODE */
/*--------------------------------------------------------------------------+
- * If PCI speed = 66Mhz, set 66Mhz capable bit.
+ * If PCI speed = 66MHz, set 66MHz capable bit.
*--------------------------------------------------------------------------*/
if (bd->bi_pci_busfreq >= 66000000) {
pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
@@ -405,8 +405,8 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
*/
static struct pci_config_table pci_405gp_config_table[] = {
/*if VendID is 0 it terminates the table search (ie Walnut)*/
-#ifdef CFG_PCI_SUBSYS_VENDORID
- {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
+#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
+ {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
#endif
{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
@@ -488,10 +488,10 @@ int pci_440_init (struct pci_controller *hose)
/* PCI memory space */
pci_set_region(hose->regions + reg_num++,
- CFG_PCI_TARGBASE,
- CFG_PCI_MEMBASE,
-#ifdef CFG_PCI_MEMSIZE
- CFG_PCI_MEMSIZE,
+ CONFIG_SYS_PCI_TARGBASE,
+ CONFIG_SYS_PCI_MEMBASE,
+#ifdef CONFIG_SYS_PCI_MEMSIZE
+ CONFIG_SYS_PCI_MEMSIZE,
#else
0x10000000,
#endif
@@ -523,11 +523,11 @@ int pci_440_init (struct pci_controller *hose)
/*--------------------------------------------------------------------------+
* PCI target init
*--------------------------------------------------------------------------*/
-#if defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_SYS_PCI_TARGET_INIT)
pci_target_init(hose); /* Let board setup pci target */
#else
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
+ out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif
@@ -542,9 +542,9 @@ int pci_440_init (struct pci_controller *hose)
/*--------------------------------------------------------------------------+
* PCI master init: default is one 256MB region for PCI memory:
- * 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE
+ * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
*--------------------------------------------------------------------------*/
-#if defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_SYS_PCI_MASTER_INIT)
pci_master_init(hose); /* Let board setup pci master */
#else
out32r( PCIX0_POM0SA, 0 ); /* disable */
@@ -558,7 +558,7 @@ int pci_440_init (struct pci_controller *hose)
out32r( PCIX0_POM0LAL, 0x00000000 );
out32r( PCIX0_POM0LAH, 0x00000003 );
#endif
- out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
+ out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
out32r( PCIX0_POM0PCIAH, 0x00000000 );
out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 0aadc06..fd40d8a 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -49,12 +49,12 @@ enum {
static int validate_endpoint(struct pci_controller *hose)
{
- if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE)
+ if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE)
return (is_end_point(0));
- else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE)
+ else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE)
return (is_end_point(1));
-#if CFG_PCIE_NR_PORTS > 2
- else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE)
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
+ else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE)
return (is_end_point(2));
#endif
@@ -67,13 +67,13 @@ static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
/* use local configuration space for the first bus */
if (PCI_BUS(devfn) == 0) {
- if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
- base = (u8*)CFG_PCIE0_XCFGBASE;
- if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
- base = (u8*)CFG_PCIE1_XCFGBASE;
-#if CFG_PCIE_NR_PORTS > 2
- if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
- base = (u8*)CFG_PCIE2_XCFGBASE;
+ if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE)
+ base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE;
+ if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE)
+ base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE;
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
+ if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE)
+ base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE;
#endif
}
@@ -86,7 +86,7 @@ static void pcie_dmer_disable(void)
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
#endif
@@ -98,7 +98,7 @@ static void pcie_dmer_enable(void)
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
#endif
@@ -286,7 +286,7 @@ static void ppc4xx_setup_utl(u32 port) {
mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
break;
}
- utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
+ utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
/*
* Set buffer allocations and then assert VRB and TXE.
@@ -412,21 +412,21 @@ static void ppc4xx_setup_utl(u32 port)
*/
switch (port) {
case 0:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE));
- mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE));
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE));
mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */
mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
break;
case 1:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE));
- mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE)
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)
+ 0x1000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */
mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
break;
}
- utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
+ utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
/*
* Set buffer allocations and then assert VRB and TXE.
@@ -512,20 +512,20 @@ static void ppc4xx_setup_utl(u32 port)
switch (port) {
case 0:
mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE);
mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
break;
case 1:
mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE);
mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
break;
}
- utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE;
+ utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE;
/*
* Set buffer allocations and then assert VRB and TXE.
@@ -761,9 +761,9 @@ static inline u64 ppc4xx_get_cfgaddr(int port)
{
#if defined(CONFIG_405EX)
if (port == 0)
- return (u64)CFG_PCIE0_CFGBASE;
+ return (u64)CONFIG_SYS_PCIE0_CFGBASE;
else
- return (u64)CFG_PCIE1_CFGBASE;
+ return (u64)CONFIG_SYS_PCIE1_CFGBASE;
#endif
#if defined(CONFIG_440SPE)
if (ppc440spe_revB()) {
@@ -895,7 +895,7 @@ int ppc4xx_init_pcie_port(int port, int rootport)
mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
break;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
case 2:
mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
@@ -947,20 +947,20 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
switch (port) {
case 0:
- mbase = (u32 *)CFG_PCIE0_XCFGBASE;
- rmbase = (u32 *)CFG_PCIE0_CFGBASE;
- hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
+ mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
+ rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE;
+ hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
break;
case 1:
- mbase = (u32 *)CFG_PCIE1_XCFGBASE;
- rmbase = (u32 *)CFG_PCIE1_CFGBASE;
- hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
+ mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
+ rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE;
+ hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
break;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
case 2:
- mbase = (u32 *)CFG_PCIE2_XCFGBASE;
- rmbase = (u32 *)CFG_PCIE2_CFGBASE;
- hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
+ mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
+ rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE;
+ hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
break;
#endif
}
@@ -979,19 +979,19 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
* subregions and to enable the outbound translation.
*/
out_le32(mbase + PECFG_POM0LAH, 0x00000000);
- out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE);
+ out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE +
+ port * CONFIG_SYS_PCIE_MEMSIZE);
debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
in_le32(mbase + PECFG_POM0LAL));
switch (port) {
case 0:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
+ port * CONFIG_SYS_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
- ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
@@ -999,26 +999,26 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
break;
case 1:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
+ port * CONFIG_SYS_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
- ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
break;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
case 2:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
+ port * CONFIG_SYS_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
- ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
@@ -1072,17 +1072,17 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
switch (port) {
case 0:
- mbase = (u32 *)CFG_PCIE0_XCFGBASE;
- hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
+ mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
+ hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
break;
case 1:
- mbase = (u32 *)CFG_PCIE1_XCFGBASE;
- hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
+ mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
+ hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
break;
-#if defined(CFG_PCIE2_CFGBASE)
+#if defined(CONFIG_SYS_PCIE2_CFGBASE)
case 2:
- mbase = (u32 *)CFG_PCIE2_XCFGBASE;
- hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
+ mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
+ hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
break;
#endif
}
@@ -1098,29 +1098,29 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
switch (port) {
case 0:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
+ port * CONFIG_SYS_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
- ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
break;
case 1:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
+ port * CONFIG_SYS_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
- ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
break;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
case 2:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
+ port * CONFIG_SYS_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
- ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
break;
#endif
}
@@ -1141,8 +1141,8 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
out_le32(mbase + PECFG_BAR2HMPA, 0);
out_le32(mbase + PECFG_BAR2LMPA, 0);
- out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE));
- out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE));
+ out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE));
+ out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE));
out_le32(mbase + PECFG_PIMEN, 0x1);
/* Enable I/O, Mem, and Busmaster cycles */
diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c
index 766e586..c106ac2 100644
--- a/cpu/ppc4xx/4xx_uart.c
+++ b/cpu/ppc4xx/4xx_uart.c
@@ -66,20 +66,20 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART0_BASE (CFG_PERIPHERAL_BASE + 0x00000300)
-#define UART1_BASE (CFG_PERIPHERAL_BASE + 0x00000400)
+#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
+#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400)
#else
-#define UART0_BASE (CFG_PERIPHERAL_BASE + 0x00000200)
-#define UART1_BASE (CFG_PERIPHERAL_BASE + 0x00000300)
+#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000200)
+#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
#endif
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define UART2_BASE (CFG_PERIPHERAL_BASE + 0x00000600)
+#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART2_BASE (CFG_PERIPHERAL_BASE + 0x00000500)
-#define UART3_BASE (CFG_PERIPHERAL_BASE + 0x00000600)
+#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
+#define UART3_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
#endif
#if defined(CONFIG_440GP)
@@ -147,7 +147,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define ACTING_UART1_BASE UART1_BASE
#endif
-#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
+#if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
#error "External serial clock not supported on AMCC PPC405EP!"
#endif
@@ -199,8 +199,8 @@ static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
/* Correct UART frequency in bd-info struct now that
* the UART divisor is available
*/
-#ifdef CFG_EXT_SERIAL_CLOCK
- gd->uart_clk = CFG_EXT_SERIAL_CLOCK;
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
+ gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
#else
gd->uart_clk = sys_info.freqUART / udiv;
#endif
@@ -218,7 +218,7 @@ static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
}
#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \
- !defined(CFG_EXT_SERIAL_CLOCK)
+ !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
static void serial_divs (int baudrate, unsigned long *pudiv,
unsigned short *pbdiv)
{
@@ -315,7 +315,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
mtcpr(cprperd0, reg);
*pbdiv = div / udiv;
}
-#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
+#endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */
/*
* Minimal serial functions needed to use one of the SMC ports
@@ -328,18 +328,18 @@ int serial_init_dev(unsigned long base)
unsigned long reg;
unsigned long udiv;
unsigned short bdiv;
-#ifdef CFG_EXT_SERIAL_CLOCK
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
unsigned long tmp;
#endif
MFREG(UART0_SDR, reg);
reg &= ~CR0_MASK;
-#ifdef CFG_EXT_SERIAL_CLOCK
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
tmp = gd->baudrate * 16;
- bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+ bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
#else
/* For 440, the cpu clock is on divider chain A, UART on divider
* chain B ... so cpu clock is irrelevant. Get the "optimized"
@@ -384,11 +384,11 @@ int serial_init_dev (unsigned long base)
clk = tmp = 0;
mfsdr(UART0_SDR, reg);
reg &= ~CR0_MASK;
-#ifdef CFG_EXT_SERIAL_CLOCK
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
tmp = gd->baudrate * 16;
- bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+ bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
#else
serial_divs(gd->baudrate, &udiv, &bdiv);
#endif
@@ -411,7 +411,7 @@ int serial_init_dev (unsigned long base)
#ifdef CONFIG_405EP
reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
clk = gd->cpu_clk;
- tmp = CFG_BASE_BAUD * 16;
+ tmp = CONFIG_SYS_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
@@ -420,16 +420,16 @@ int serial_init_dev (unsigned long base)
mtdcr (cpc0_ucr, reg);
#else /* CONFIG_405EP */
reg = mfdcr(cntrl0) & ~CR0_MASK;
-#ifdef CFG_EXT_SERIAL_CLOCK
- clk = CFG_EXT_SERIAL_CLOCK;
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
+ clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
udiv = 1;
reg |= CR0_EXTCLK_ENA;
#else
clk = gd->cpu_clk;
-#ifdef CFG_405_UART_ERRATA_59
+#ifdef CONFIG_SYS_405_UART_ERRATA_59
udiv = 31; /* Errata 59: stuck at 31 */
#else
- tmp = CFG_BASE_BAUD * 16;
+ tmp = CONFIG_SYS_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index c773400..96ab5c6 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -35,6 +35,9 @@ SOBJS += kgdb.o
COBJS := 40x_spd_sdram.o
COBJS += 44x_spd_ddr.o
COBJS += 44x_spd_ddr2.o
+ifdef CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+COBJS += 4xx_ibm_ddr2_autocalib.o
+endif
COBJS += 4xx_pci.o
COBJS += 4xx_pcie.o
COBJS += bedbug_405.o
@@ -57,7 +60,6 @@ COBJS += usb.o
COBJS += usb_ohci.o
COBJS += usbdev.o
ifndef CONFIG_XILINX_440
-COBJS += 4xx_enet.o
COBJS += 4xx_uart.o
COBJS += gpio.o
COBJS += miiphy.o
diff --git a/cpu/ppc4xx/cache.S b/cpu/ppc4xx/cache.S
index ceb3ec0..269716f 100644
--- a/cpu/ppc4xx/cache.S
+++ b/cpu/ppc4xx/cache.S
@@ -143,8 +143,8 @@ _GLOBAL(flush_dcache)
_GLOBAL(invalidate_dcache)
addi r6,0,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
- lis r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha /* TBS for large sized cache */
- ori r7,r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
+ lis r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha /* TBS for large sized cache */
+ ori r7,r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
..dcloop:
diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c
index 8b2954c..a1696d3 100644
--- a/cpu/ppc4xx/commproc.c
+++ b/cpu/ppc4xx/commproc.c
@@ -30,10 +30,10 @@
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
-#if defined(CFG_POST_WORD_ADDR)
-# define _POST_ADDR ((CFG_OCM_DATA_ADDR) + (CFG_POST_WORD_ADDR))
-#elif defined(CFG_POST_ALT_WORD_ADDR)
-# define _POST_ADDR (CFG_POST_ALT_WORD_ADDR)
+#if defined(CONFIG_SYS_POST_WORD_ADDR)
+# define _POST_ADDR ((CONFIG_SYS_OCM_DATA_ADDR) + (CONFIG_SYS_POST_WORD_ADDR))
+#elif defined(CONFIG_SYS_POST_ALT_WORD_ADDR)
+# define _POST_ADDR (CONFIG_SYS_POST_ALT_WORD_ADDR)
#endif
void post_word_store (ulong a)
@@ -57,7 +57,7 @@ ulong post_word_load (void)
void bootcount_store (ulong a)
{
volatile ulong *save_addr =
- (volatile ulong *)(CFG_OCM_DATA_ADDR + CFG_BOOTCOUNT_ADDR);
+ (volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR);
save_addr[0] = a;
save_addr[1] = BOOTCOUNT_MAGIC;
@@ -66,7 +66,7 @@ void bootcount_store (ulong a)
ulong bootcount_load (void)
{
volatile ulong *save_addr =
- (volatile ulong *)(CFG_OCM_DATA_ADDR + CFG_BOOTCOUNT_ADDR);
+ (volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR);
if (save_addr[1] != BOOTCOUNT_MAGIC)
return 0;
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index bc9335a..d09c4c2 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -36,11 +36,24 @@
#include <command.h>
#include <asm/cache.h>
#include <ppc4xx.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
void board_reset(void);
+/*
+ * To provide an interface to detect CPU number for boards that support
+ * more then one CPU, we implement the "weak" default functions here.
+ *
+ * Returns CPU number
+ */
+int __get_cpu_num(void)
+{
+ return NA_OR_UNKNOWN_CPU;
+}
+int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
+
#if defined(CONFIG_405GP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
@@ -274,8 +287,13 @@ int checkcpu (void)
#if !defined(CONFIG_IOP480)
char addstr[64] = "";
sys_info_t sys_info;
+ int cpu_num;
- puts ("CPU: ");
+ cpu_num = get_cpu_num();
+ if (cpu_num >= 0)
+ printf("CPU%d: ", cpu_num);
+ else
+ puts("CPU: ");
get_sys_info(&sys_info);
@@ -629,14 +647,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#if defined(CONFIG_BOARD_RESET)
board_reset();
#else
-#if defined(CFG_4xx_RESET_TYPE)
- mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
+#if defined(CONFIG_SYS_4xx_RESET_TYPE)
+ mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
#else
/*
* Initiate system reset in debug control register DBCR
*/
mtspr(dbcr0, 0x30000000);
-#endif /* defined(CFG_4xx_RESET_TYPE) */
+#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
#endif /* defined(CONFIG_BOARD_RESET) */
return 1;
@@ -676,3 +694,15 @@ void reset_4xx_watchdog(void)
mtspr(tsr, 0x40000000);
}
#endif /* CONFIG_WATCHDOG */
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_PPC4xx_EMAC)
+ ppc_4xx_eth_initialize(bis);
+#endif
+ return 0;
+}
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index dee9807..b5d81f2 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -32,8 +32,8 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
-#ifndef CFG_PLL_RECONFIG
-#define CFG_PLL_RECONFIG 0
+#ifndef CONFIG_SYS_PLL_RECONFIG
+#define CONFIG_SYS_PLL_RECONFIG 0
#endif
void reconfigure_pll(u32 new_cpu_freq)
@@ -142,32 +142,32 @@ cpu_init_f (void)
u32 val;
#endif
- reconfigure_pll(CFG_PLL_RECONFIG);
+ reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
-#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
+#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
-#if defined(CFG_GPIO0_OR)
- out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */
+#if defined(CONFIG_SYS_GPIO0_OR)
+ out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */
#endif
-#if defined(CFG_GPIO0_ODR)
- out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */
+#if defined(CONFIG_SYS_GPIO0_ODR)
+ out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */
#endif
- out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
- out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
- out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
- out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
- out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
- out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
-#if defined(CFG_GPIO0_ISR2H)
- out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
- out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
+ out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
+ out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
+ out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
+ out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
+ out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
+ out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
+#if defined(CONFIG_SYS_GPIO0_ISR2H)
+ out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
+ out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
#endif
-#if defined (CFG_GPIO0_TCR)
- out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
+#if defined (CONFIG_SYS_GPIO0_TCR)
+ out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
#endif
-#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */
+#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */
#if defined (CONFIG_405EP)
/*
@@ -181,14 +181,14 @@ cpu_init_f (void)
mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
#endif /* CONFIG_405EP */
-#if defined(CFG_4xx_GPIO_TABLE)
+#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
gpio_set_chip_configuration();
-#endif /* CFG_4xx_GPIO_TABLE */
+#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
/*
* External Bus Controller (EBC) Setup
*/
-#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
+#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_405))
@@ -209,47 +209,47 @@ cpu_init_f (void)
asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
#endif
- mtebc(pb0ap, CFG_EBC_PB0AP);
- mtebc(pb0cr, CFG_EBC_PB0CR);
+ mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);
+ mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
#endif
-#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
- mtebc(pb1ap, CFG_EBC_PB1AP);
- mtebc(pb1cr, CFG_EBC_PB1CR);
+#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
+ mtebc(pb1ap, CONFIG_SYS_EBC_PB1AP);
+ mtebc(pb1cr, CONFIG_SYS_EBC_PB1CR);
#endif
-#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
- mtebc(pb2ap, CFG_EBC_PB2AP);
- mtebc(pb2cr, CFG_EBC_PB2CR);
+#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
+ mtebc(pb2ap, CONFIG_SYS_EBC_PB2AP);
+ mtebc(pb2cr, CONFIG_SYS_EBC_PB2CR);
#endif
-#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
- mtebc(pb3ap, CFG_EBC_PB3AP);
- mtebc(pb3cr, CFG_EBC_PB3CR);
+#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
+ mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP);
+ mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR);
#endif
-#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
- mtebc(pb4ap, CFG_EBC_PB4AP);
- mtebc(pb4cr, CFG_EBC_PB4CR);
+#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
+ mtebc(pb4ap, CONFIG_SYS_EBC_PB4AP);
+ mtebc(pb4cr, CONFIG_SYS_EBC_PB4CR);
#endif
-#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
- mtebc(pb5ap, CFG_EBC_PB5AP);
- mtebc(pb5cr, CFG_EBC_PB5CR);
+#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
+ mtebc(pb5ap, CONFIG_SYS_EBC_PB5AP);
+ mtebc(pb5cr, CONFIG_SYS_EBC_PB5CR);
#endif
-#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
- mtebc(pb6ap, CFG_EBC_PB6AP);
- mtebc(pb6cr, CFG_EBC_PB6CR);
+#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
+ mtebc(pb6ap, CONFIG_SYS_EBC_PB6AP);
+ mtebc(pb6cr, CONFIG_SYS_EBC_PB6CR);
#endif
-#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
- mtebc(pb7ap, CFG_EBC_PB7AP);
- mtebc(pb7cr, CFG_EBC_PB7CR);
+#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
+ mtebc(pb7ap, CONFIG_SYS_EBC_PB7AP);
+ mtebc(pb7cr, CONFIG_SYS_EBC_PB7CR);
#endif
-#if defined (CFG_EBC_CFG)
- mtebc(EBC0_CFG, CFG_EBC_CFG);
+#if defined (CONFIG_SYS_EBC_CFG)
+ mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
#endif
#if defined(CONFIG_WATCHDOG)
@@ -261,9 +261,9 @@ cpu_init_f (void)
#else
val |= 0xf0000000; /* generate system reset after 2.684 seconds */
#endif
-#if defined(CFG_4xx_RESET_TYPE)
+#if defined(CONFIG_SYS_4xx_RESET_TYPE)
val &= ~0x30000000; /* clear WRC bits */
- val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */
+ val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
#endif
mtspr(tcr, val);
diff --git a/cpu/ppc4xx/denali_data_eye.c b/cpu/ppc4xx/denali_data_eye.c
index 967e61b..ffc3817 100644
--- a/cpu/ppc4xx/denali_data_eye.c
+++ b/cpu/ppc4xx/denali_data_eye.c
@@ -127,7 +127,7 @@ void denali_core_search_data_eye(void)
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55
};
- ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
+ ram_pointer = (volatile u32 *)(CONFIG_SYS_SDRAM_BASE);
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
/* for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) { */
diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c
index 670fc5c..4705e21 100644
--- a/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/cpu/ppc4xx/denali_spd_ddr2.c
@@ -1048,8 +1048,8 @@ phys_size_t initdram(int board_type)
* before continuing.
*/
/* switch to correct I2C bus */
- I2C_SET_BUS(CFG_SPD_BUS_NUM);
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
/*------------------------------------------------------------------
* Clear out the serial presence detect buffers.
@@ -1185,27 +1185,27 @@ phys_size_t initdram(int board_type)
* Map the first 1 MiB of memory in the TLB, and perform the data eye
* search.
*/
- program_tlb(0, CFG_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
+ program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
denali_core_search_data_eye();
denali_sdram_register_dump();
- remove_tlb(CFG_SDRAM_BASE, TLB_1MB_SIZE);
+ remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
#endif
#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
- program_tlb(0, CFG_SDRAM_BASE, dram_size, 0);
+ program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
sync();
/* Zero the memory */
debug("Zeroing SDRAM...");
-#if defined(CFG_MEM_TOP_HIDE)
- dcbz_area(CFG_SDRAM_BASE, dram_size - CFG_MEM_TOP_HIDE);
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
#else
-#error Please define CFG_MEM_TOP_HIDE (see README) in your board config file
+#error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
#endif
/* Write modified dcache lines back to memory */
- clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE);
+ clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
debug("Completed\n");
sync();
- remove_tlb(CFG_SDRAM_BASE, dram_size);
+ remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);
#if defined(CONFIG_DDR_ECC)
/*
@@ -1236,7 +1236,7 @@ phys_size_t initdram(int board_type)
#endif /* defined(CONFIG_DDR_ECC) */
#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
- program_tlb(0, CFG_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
+ program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
return dram_size;
}
diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c
index a2eb07b..3f989e7 100644
--- a/cpu/ppc4xx/ecc.c
+++ b/cpu/ppc4xx/ecc.c
@@ -68,7 +68,7 @@
*
* Output(s):
* start - A pointer to the start of memory covered by ECC with
- * CFG_ECC_PATTERN written to all locations and ECC data
+ * CONFIG_SYS_ECC_PATTERN written to all locations and ECC data
* primed.
*
* Returns:
@@ -76,7 +76,7 @@
*/
void ecc_init(unsigned long * const start, unsigned long size)
{
- const unsigned long pattern = CFG_ECC_PATTERN;
+ const unsigned long pattern = CONFIG_SYS_ECC_PATTERN;
unsigned long * const end = (unsigned long * const)((long)start + size);
unsigned long * current = start;
unsigned long mcopt1;
diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h
index aecf291..67c3bff 100644
--- a/cpu/ppc4xx/ecc.h
+++ b/cpu/ppc4xx/ecc.h
@@ -33,9 +33,9 @@
#ifndef _ECC_H_
#define _ECC_H_
-#if !defined(CFG_ECC_PATTERN)
-#define CFG_ECC_PATTERN 0x00000000
-#endif /* !defined(CFG_ECC_PATTERN) */
+#if !defined(CONFIG_SYS_ECC_PATTERN)
+#define CONFIG_SYS_ECC_PATTERN 0x00000000
+#endif /* !defined(CONFIG_SYS_ECC_PATTERN) */
/*
* Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index a97484f..c55e1cf 100644
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -37,29 +37,40 @@ DECLARE_GLOBAL_DATA_PTR;
void __ft_board_setup(void *blob, bd_t *bd)
{
- u32 val[4];
int rc;
+ int i;
+ u32 bxcr;
+ u32 ranges[EBC_NUM_BANKS * 4];
+ u32 *p = ranges;
+ char *ebc_path = "/plb/opb/ebc";
ft_cpu_setup(blob, bd);
- /* Fixup NOR mapping */
- val[0] = 0; /* chip select number */
- val[1] = 0; /* always 0 */
- val[2] = gd->bd->bi_flashstart;
- val[3] = gd->bd->bi_flashsize;
- if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0) {
- rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
- val, sizeof(val), 1);
- } else {
- /*
- * Some 405 PPC's have EBC as direct PLB child in the dts
- */
- rc = fdt_find_and_setprop(blob, "/plb/ebc", "ranges",
- val, sizeof(val), 1);
+ /*
+ * Read 4xx EBC bus bridge registers to get mappings of the
+ * peripheral banks into the OPB/PLB address space
+ */
+ for (i = 0; i < EBC_NUM_BANKS; i++) {
+ mtdcr(ebccfga, EBC_BXCR(i));
+ bxcr = mfdcr(ebccfgd);
+
+ if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
+ *p++ = i;
+ *p++ = 0;
+ *p++ = bxcr & EBC_BXCR_BAS_MASK;
+ *p++ = EBC_BXCR_BANK_SIZE(bxcr);
+ }
}
- if (rc)
- printf("Unable to update property NOR mapping, err=%s\n",
+
+ /* Some 405 PPC's have EBC as direct PLB child in the dts */
+ if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
+ strcpy(ebc_path, "/plb/ebc");
+ rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
+ (p - ranges) * sizeof(u32), 1);
+ if (rc) {
+ printf("Unable to update property EBC mappings, err=%s\n",
fdt_strerror(rc));
+ }
}
void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));
diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c
index df99f53..c0d351a 100644
--- a/cpu/ppc4xx/gpio.c
+++ b/cpu/ppc4xx/gpio.c
@@ -26,8 +26,8 @@
#include <asm/io.h>
#include <asm/gpio.h>
-#if defined(CFG_4xx_GPIO_TABLE)
-gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
+#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
+gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE;
#endif
#if defined(GPIO0_OSRL)
@@ -132,7 +132,7 @@ int gpio_read_in_bit(int pin)
return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
}
-#if defined(CFG_4xx_GPIO_TABLE)
+#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
void gpio_set_chip_configuration(void)
{
unsigned char i=0, j=0, offs=0, gpio_core;
@@ -252,4 +252,4 @@ void gpio_set_chip_configuration(void)
}
}
}
-#endif /* CFG_4xx_GPIO_TABLE */
+#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
index d8be2ce..9d416ca 100644
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -42,11 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
* runs from ROM, and we can't switch buses because we can't modify
* the global variables.
*/
-#ifdef CFG_SPD_BUS_NUM
-static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
-#else
-static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
+#ifndef CONFIG_SYS_SPD_BUS_NUM
+#define CONFIG_SYS_SPD_BUS_NUM 0
#endif
+static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
#endif /* CONFIG_I2C_MULTI_BUS */
static void _i2c_bus_reset(void)
@@ -95,14 +94,14 @@ void i2c_init(int speed, int slaveadd)
int val, divisor;
int bus;
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
/* call board specific i2c bus reset routine before accessing the */
/* environment, which might be in a chip on that bus. For details */
/* about this problem see doc/I2C_Edge_Conditions. */
i2c_init_board();
#endif
- for (bus = 0; bus < CFG_MAX_I2C_BUS; bus++) {
+ for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) {
I2C_SET_BUS(bus);
/* Handle possible failed I2C state */
@@ -161,7 +160,7 @@ void i2c_init(int speed, int slaveadd)
}
/* set to SPD bus as default bus upon powerup */
- I2C_SET_BUS(CFG_SPD_BUS_NUM);
+ I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
}
/*
@@ -361,7 +360,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
}
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -374,7 +373,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
* hidden in the chip address.
*/
if (alen > 0)
- chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
if ((ret = i2c_transfer(1, chip<<1, &xaddr[4-alen], alen, buffer, len)) != 0) {
if (gd->have_console)
@@ -401,7 +400,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
xaddr[3] = addr & 0xFF;
}
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -414,32 +413,12 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
* hidden in the chip address.
*/
if (alen > 0)
- chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
}
-/*-----------------------------------------------------------------------
- * Read a register
- */
-uchar i2c_reg_read(uchar i2c_addr, uchar reg)
-{
- uchar buf;
-
- i2c_read(i2c_addr, reg, 1, &buf, 1);
-
- return (buf);
-}
-
-/*-----------------------------------------------------------------------
- * Write a register
- */
-void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
-{
- i2c_write(i2c_addr, reg, 1, &val, 1);
-}
-
#if defined(CONFIG_I2C_MULTI_BUS)
/*
* Functions for multiple I2C bus handling
@@ -451,7 +430,7 @@ unsigned int i2c_get_bus_num(void)
int i2c_set_bus_num(unsigned int bus)
{
- if (bus >= CFG_MAX_I2C_BUS)
+ if (bus >= CONFIG_SYS_MAX_I2C_BUS)
return -1;
i2c_bus_num = bus;
@@ -463,12 +442,12 @@ int i2c_set_bus_num(unsigned int bus)
/* TODO: add 100/400k switching */
unsigned int i2c_get_bus_speed(void)
{
- return CFG_I2C_SPEED;
+ return CONFIG_SYS_I2C_SPEED;
}
int i2c_set_bus_speed(unsigned int speed)
{
- if (speed != CFG_I2C_SPEED)
+ if (speed != CONFIG_SYS_I2C_SPEED)
return -1;
return 0;
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index c882720..01710e7 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -180,8 +180,10 @@ int phy_setup_aneg (char *devname, unsigned char addr)
*
* sr: Currently on 460EX only EMAC0 works with MDIO, so we always
* return EMAC0 offset here
+ * vg: For 460EX/460GT if internal GPCS PHY address is specified
+ * return appropriate EMAC offset
*/
-unsigned int miiphy_getemac_offset (void)
+unsigned int miiphy_getemac_offset(u8 addr)
{
#if (defined(CONFIG_440) && \
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
@@ -233,6 +235,35 @@ unsigned int miiphy_getemac_offset (void)
return 0x100;
#endif
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ u32 eoffset = 0;
+
+ switch (addr) {
+#if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR)
+ case CONFIG_GPCS_PHY1_ADDR:
+ if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x100)))
+ eoffset = 0x100;
+ break;
+#endif
+#if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR)
+ case CONFIG_GPCS_PHY2_ADDR:
+ if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x300)))
+ eoffset = 0x300;
+ break;
+#endif
+#if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR)
+ case CONFIG_GPCS_PHY3_ADDR:
+ if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x400)))
+ eoffset = 0x400;
+ break;
+#endif
+ default:
+ eoffset = 0;
+ break;
+ }
+ return eoffset;
+#endif
+
return 0;
#endif
}
@@ -262,7 +293,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
u32 emac_reg;
u32 sta_reg;
- emac_reg = miiphy_getemac_offset();
+ emac_reg = miiphy_getemac_offset(addr);
/* wait for completion */
if (emac_miiphy_wait(emac_reg) != 0)
@@ -270,7 +301,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
sta_reg = reg; /* reg address */
- /* set clock (50Mhz) and read flags */
+ /* set clock (50MHz) and read flags */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
@@ -311,7 +342,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
unsigned long sta_reg;
unsigned long emac_reg;
- emac_reg = miiphy_getemac_offset ();
+ emac_reg = miiphy_getemac_offset(addr);
if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
return -1;
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index 7d96e79..3a5af12 100644
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -149,8 +149,8 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
}
#endif /* #ifndef CONFIG_NAND_SPL */
-#ifndef CFG_NAND_BCR
-#define CFG_NAND_BCR 0x80002222
+#ifndef CONFIG_SYS_NAND_BCR
+#define CONFIG_SYS_NAND_BCR 0x80002222
#endif
void board_nand_select_device(struct nand_chip *nand, int chip)
@@ -165,7 +165,7 @@ void board_nand_select_device(struct nand_chip *nand, int chip)
/* Set NandFlash Core Configuration Register */
/* 1 col x 2 rows */
out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
- out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CFG_NAND_BCR);
+ out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
}
static void ndfc_select_chip(struct mtd_info *mtd, int chip)
@@ -214,8 +214,8 @@ int board_nand_init(struct nand_chip *nand)
*/
mtebc(EBC0_CFG, 0xb8400000);
- mtebc(pb0cr, CFG_EBC_PB0CR);
- mtebc(pb0ap, CFG_EBC_PB0AP);
+ mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
+ mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);
#endif
chip++;
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index 7d60ad6..6d5f8d6 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -37,7 +37,7 @@
#ifndef CONFIG_440
-#ifndef CFG_SDRAM_TABLE
+#ifndef CONFIG_SYS_SDRAM_TABLE
sdram_conf_t mb0cf[] = {
{(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
{(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
@@ -46,72 +46,72 @@ sdram_conf_t mb0cf[] = {
{(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
};
#else
-sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
+sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
#endif
#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
-#ifdef CFG_SDRAM_CASL
+#ifdef CONFIG_SYS_SDRAM_CASL
static ulong ns2clks(ulong ns)
{
ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
}
-#endif /* CFG_SDRAM_CASL */
+#endif /* CONFIG_SYS_SDRAM_CASL */
static ulong compute_sdtr1(ulong speed)
{
-#ifdef CFG_SDRAM_CASL
+#ifdef CONFIG_SYS_SDRAM_CASL
ulong tmp;
ulong sdtr1 = 0;
/* CASL */
- if (CFG_SDRAM_CASL < 2)
+ if (CONFIG_SYS_SDRAM_CASL < 2)
sdtr1 |= (1 << SDRAM0_TR_CASL);
else
- if (CFG_SDRAM_CASL > 4)
+ if (CONFIG_SYS_SDRAM_CASL > 4)
sdtr1 |= (3 << SDRAM0_TR_CASL);
else
- sdtr1 |= ((CFG_SDRAM_CASL-1) << SDRAM0_TR_CASL);
+ sdtr1 |= ((CONFIG_SYS_SDRAM_CASL-1) << SDRAM0_TR_CASL);
/* PTA */
- tmp = ns2clks(CFG_SDRAM_PTA);
+ tmp = ns2clks(CONFIG_SYS_SDRAM_PTA);
if ((tmp >= 2) && (tmp <= 4))
sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA);
else
sdtr1 |= ((4-1) << SDRAM0_TR_PTA);
/* CTP */
- tmp = ns2clks(CFG_SDRAM_CTP);
+ tmp = ns2clks(CONFIG_SYS_SDRAM_CTP);
if ((tmp >= 2) && (tmp <= 4))
sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP);
else
sdtr1 |= ((4-1) << SDRAM0_TR_CTP);
/* LDF */
- tmp = ns2clks(CFG_SDRAM_LDF);
+ tmp = ns2clks(CONFIG_SYS_SDRAM_LDF);
if ((tmp >= 2) && (tmp <= 4))
sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF);
else
sdtr1 |= ((2-1) << SDRAM0_TR_LDF);
/* RFTA */
- tmp = ns2clks(CFG_SDRAM_RFTA);
+ tmp = ns2clks(CONFIG_SYS_SDRAM_RFTA);
if ((tmp >= 4) && (tmp <= 10))
sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA);
else
sdtr1 |= ((10-4) << SDRAM0_TR_RFTA);
/* RCD */
- tmp = ns2clks(CFG_SDRAM_RCD);
+ tmp = ns2clks(CONFIG_SYS_SDRAM_RCD);
if ((tmp >= 2) && (tmp <= 4))
sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD);
else
sdtr1 |= ((4-1) << SDRAM0_TR_RCD);
return sdtr1;
-#else /* CFG_SDRAM_CASL */
+#else /* CONFIG_SYS_SDRAM_CASL */
/*
* If no values are configured in the board config file
* use the default values, which seem to be ok for most
@@ -133,20 +133,20 @@ static ulong compute_sdtr1(ulong speed)
*/
return 0x0086400d;
}
-#endif /* CFG_SDRAM_CASL */
+#endif /* CONFIG_SYS_SDRAM_CASL */
}
/* refresh is expressed in ms */
static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
{
-#ifdef CFG_SDRAM_CASL
+#ifdef CONFIG_SYS_SDRAM_CASL
ulong tmp;
tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000);
tmp /= 1000000;
return ((tmp & 0x00003FF8) << 16);
-#else /* CFG_SDRAM_CASL */
+#else /* CONFIG_SYS_SDRAM_CASL */
if (speed > 100000000) {
/*
* 133 MHz SDRAM
@@ -158,7 +158,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
*/
return 0x05f00000;
}
-#endif /* CFG_SDRAM_CASL */
+#endif /* CONFIG_SYS_SDRAM_CASL */
}
/*
@@ -209,15 +209,15 @@ phys_size_t initdram(int board_type)
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
+ phys_size_t size = mb0cf[i].size;
+
/*
* OK, size detected. Enable second bank if
* defined (assumes same type as bank 0)
*/
#ifdef CONFIG_SDRAM_BANK1
- u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
-
mtsdram(mem_mcopt1, 0x00000000);
- mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
+ mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg);
mtsdram(mem_mcopt1, 0x80800000);
udelay(10000);
@@ -230,13 +230,19 @@ phys_size_t initdram(int board_type)
mb0cf[i].size) {
mtsdram(mem_mb1cf, 0);
mtsdram(mem_mcopt1, 0);
+ } else {
+ /*
+ * We have two identical banks, so the size
+ * is twice the bank size
+ */
+ size = 2 * size;
}
#endif
/*
* OK, size detected -> all done
*/
- return mb0cf[i].size;
+ return size;
}
}
@@ -250,17 +256,17 @@ phys_size_t initdram(int board_type)
* board config file.
*/
-#ifndef CFG_SDRAM_TABLE
+#ifndef CONFIG_SYS_SDRAM_TABLE
sdram_conf_t mb0cf[] = {
{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */
{(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */
};
#else
-sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
+sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
#endif
-#ifndef CFG_SDRAM0_TR0
-#define CFG_SDRAM0_TR0 0x41094012
+#ifndef CONFIG_SYS_SDRAM0_TR0
+#define CONFIG_SYS_SDRAM0_TR0 0x41094012
#endif
#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
@@ -379,7 +385,7 @@ phys_size_t initdram(int board_type)
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, mb0cf[i].reg);
- mtsdram(mem_tr0, CFG_SDRAM0_TR0);
+ mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0);
mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
diff --git a/cpu/ppc4xx/sdram.h b/cpu/ppc4xx/sdram.h
index 4fb9b1a..bea3376 100644
--- a/cpu/ppc4xx/sdram.h
+++ b/cpu/ppc4xx/sdram.h
@@ -47,19 +47,19 @@ typedef struct sdram_conf_s sdram_conf_t;
#define SDRAM0_TR_RFTA (31 - 29)
#define SDRAM0_TR_RCD (31 - 31)
-#ifdef CFG_SDRAM_CL
+#ifdef CONFIG_SYS_SDRAM_CL
/* SDRAM timings [ns] according to AMCC/IBM names (see SDRAM_faq.doc) */
-#define CFG_SDRAM_CASL CFG_SDRAM_CL
-#define CFG_SDRAM_PTA CFG_SDRAM_tRP
-#define CFG_SDRAM_CTP (CFG_SDRAM_tRC - CFG_SDRAM_tRCD - CFG_SDRAM_tRP)
-#define CFG_SDRAM_LDF 0
-#ifdef CFG_SDRAM_tRFC
-#define CFG_SDRAM_RFTA CFG_SDRAM_tRFC
+#define CONFIG_SYS_SDRAM_CASL CONFIG_SYS_SDRAM_CL
+#define CONFIG_SYS_SDRAM_PTA CONFIG_SYS_SDRAM_tRP
+#define CONFIG_SYS_SDRAM_CTP (CONFIG_SYS_SDRAM_tRC - CONFIG_SYS_SDRAM_tRCD - CONFIG_SYS_SDRAM_tRP)
+#define CONFIG_SYS_SDRAM_LDF 0
+#ifdef CONFIG_SYS_SDRAM_tRFC
+#define CONFIG_SYS_SDRAM_RFTA CONFIG_SYS_SDRAM_tRFC
#else
-#define CFG_SDRAM_RFTA CFG_SDRAM_tRC
+#define CONFIG_SYS_SDRAM_RFTA CONFIG_SYS_SDRAM_tRC
#endif
-#define CFG_SDRAM_RCD CFG_SDRAM_tRCD
-#endif /* #ifdef CFG_SDRAM_CL */
+#define CONFIG_SYS_SDRAM_RCD CONFIG_SYS_SDRAM_tRCD
+#endif /* #ifdef CONFIG_SYS_SDRAM_CL */
/*
* Some defines for the 440 DDR controller
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index d21bd82..ed6e55b 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -148,7 +148,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
* is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
* to make sure it is within the proper range.
* spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
- * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
+ * Note freqVCO is calculated in MHz to avoid errors introduced by rounding.
*/
if (sysInfo->pllFwdDiv == 1) {
sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 97411bd..f2b8908 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -63,6 +63,7 @@
*/
#include <config.h>
#include <ppc4xx.h>
+#include <timestamp.h>
#include <version.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
@@ -72,74 +73,75 @@
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/ppc4xx-isram.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
-#ifdef CFG_INIT_DCACHE_CS
-# if (CFG_INIT_DCACHE_CS == 0)
+#ifdef CONFIG_SYS_INIT_DCACHE_CS
+# if (CONFIG_SYS_INIT_DCACHE_CS == 0)
# define PBxAP pb0ap
# define PBxCR pb0cr
-# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
-# define PBxAP_VAL CFG_EBC_PB0AP
-# define PBxCR_VAL CFG_EBC_PB0CR
+# if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
+# define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
+# define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
# endif
# endif
-# if (CFG_INIT_DCACHE_CS == 1)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 1)
# define PBxAP pb1ap
# define PBxCR pb1cr
-# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
-# define PBxAP_VAL CFG_EBC_PB1AP
-# define PBxCR_VAL CFG_EBC_PB1CR
+# if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
+# define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
+# define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
# endif
# endif
-# if (CFG_INIT_DCACHE_CS == 2)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 2)
# define PBxAP pb2ap
# define PBxCR pb2cr
-# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
-# define PBxAP_VAL CFG_EBC_PB2AP
-# define PBxCR_VAL CFG_EBC_PB2CR
+# if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
+# define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
+# define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
# endif
# endif
-# if (CFG_INIT_DCACHE_CS == 3)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 3)
# define PBxAP pb3ap
# define PBxCR pb3cr
-# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
-# define PBxAP_VAL CFG_EBC_PB3AP
-# define PBxCR_VAL CFG_EBC_PB3CR
+# if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
+# define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
+# define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
# endif
# endif
-# if (CFG_INIT_DCACHE_CS == 4)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 4)
# define PBxAP pb4ap
# define PBxCR pb4cr
-# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
-# define PBxAP_VAL CFG_EBC_PB4AP
-# define PBxCR_VAL CFG_EBC_PB4CR
+# if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
+# define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
+# define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
# endif
# endif
-# if (CFG_INIT_DCACHE_CS == 5)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 5)
# define PBxAP pb5ap
# define PBxCR pb5cr
-# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
-# define PBxAP_VAL CFG_EBC_PB5AP
-# define PBxCR_VAL CFG_EBC_PB5CR
+# if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
+# define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
+# define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
# endif
# endif
-# if (CFG_INIT_DCACHE_CS == 6)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 6)
# define PBxAP pb6ap
# define PBxCR pb6cr
-# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
-# define PBxAP_VAL CFG_EBC_PB6AP
-# define PBxCR_VAL CFG_EBC_PB6CR
+# if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
+# define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
+# define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
# endif
# endif
-# if (CFG_INIT_DCACHE_CS == 7)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 7)
# define PBxAP pb7ap
# define PBxCR pb7cr
-# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
-# define PBxAP_VAL CFG_EBC_PB7AP
-# define PBxCR_VAL CFG_EBC_PB7CR
+# if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
+# define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
+# define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
# endif
# endif
# ifndef PBxAP_VAL
@@ -149,11 +151,11 @@
# define PBxCR_VAL 0
# endif
/*
- * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB
+ * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
* used as temporary stack pointer for the primordial stack
*/
-# ifndef CFG_INIT_DCACHE_PBxAR
-# define CFG_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
+# ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
+# define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
EBC_BXAP_TWT_ENCODE(7) | \
EBC_BXAP_BCE_DISABLE | \
EBC_BXAP_BCT_2TRANS | \
@@ -166,42 +168,42 @@
EBC_BXAP_SOR_NONDELAYED | \
EBC_BXAP_BEM_WRITEONLY | \
EBC_BXAP_PEN_DISABLED)
-# endif /* CFG_INIT_DCACHE_PBxAR */
-# ifndef CFG_INIT_DCACHE_PBxCR
-# define CFG_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR) | \
+# endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
+# ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
+# define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
EBC_BXCR_BS_64MB | \
EBC_BXCR_BU_RW | \
EBC_BXCR_BW_16BIT)
-# endif /* CFG_INIT_DCACHE_PBxCR */
-# ifndef CFG_INIT_RAM_PATTERN
-# define CFG_INIT_RAM_PATTERN 0xDEADDEAD
+# endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
+# ifndef CONFIG_SYS_INIT_RAM_PATTERN
+# define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
# endif
-#endif /* CFG_INIT_DCACHE_CS */
+#endif /* CONFIG_SYS_INIT_DCACHE_CS */
-#if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10)))
-#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END!
+#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
+#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
#endif
/*
* Unless otherwise overriden, enable two 128MB cachable instruction regions
- * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering
- * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions.
+ * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
+ * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
*/
-#if !defined(CFG_FLASH_BASE)
+#if !defined(CONFIG_SYS_FLASH_BASE)
/* If not already defined, set it to the "last" 128MByte region */
-# define CFG_FLASH_BASE 0xf8000000
+# define CONFIG_SYS_FLASH_BASE 0xf8000000
#endif
-#if !defined(CFG_ICACHE_SACR_VALUE)
-# define CFG_ICACHE_SACR_VALUE \
- (PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + ( 0 << 20)) | \
- PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \
- PPC_128MB_SACR_VALUE(CFG_FLASH_BASE))
-#endif /* !defined(CFG_ICACHE_SACR_VALUE) */
-
-#if !defined(CFG_DCACHE_SACR_VALUE)
-# define CFG_DCACHE_SACR_VALUE \
+#if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
+# define CONFIG_SYS_ICACHE_SACR_VALUE \
+ (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
+ PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
+ PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
+#endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
+
+#if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
+# define CONFIG_SYS_DCACHE_SACR_VALUE \
(0x00000000)
-#endif /* !defined(CFG_DCACHE_SACR_VALUE) */
+#endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
#define function_prolog(func_name) .text; \
.align 2; \
@@ -509,7 +511,7 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
. = EXC_OFF_SYS_RESET
@@ -609,15 +611,15 @@ _start:
/*----------------------------------------------------------------*/
/* Debug setup -- some (not very good) ice's need an event*/
- /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
+ /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
/* value you need in this case 0x8cff 0000 should do the trick */
/*----------------------------------------------------------------*/
-#if defined(CFG_INIT_DBCR)
+#if defined(CONFIG_SYS_INIT_DBCR)
lis r1,0xffff
ori r1,r1,0xffff
mtspr dbsr,r1 /* Clear all status bits */
- lis r0,CFG_INIT_DBCR@h
- ori r0,r0,CFG_INIT_DBCR@l
+ lis r0,CONFIG_SYS_INIT_DBCR@h
+ ori r0,r0,CONFIG_SYS_INIT_DBCR@l
mtspr dbcr0,r0
isync
#endif
@@ -627,12 +629,12 @@ _start:
/*----------------------------------------------------------------*/
li r0,0
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* Clear Dcache to use as RAM */
- addis r3,r0,CFG_INIT_RAM_ADDR@h
- ori r3,r3,CFG_INIT_RAM_ADDR@l
- addis r4,r0,CFG_INIT_RAM_END@h
- ori r4,r4,CFG_INIT_RAM_END@l
+ addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
+ addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
+ ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
rlwinm. r5,r4,0,27,31
rlwinm r5,r4,27,5,31
beq ..d_ran
@@ -670,82 +672,95 @@ _start:
mtspr dtv3,r1
msync
isync
-#endif /* CFG_INIT_RAM_DCACHE */
+#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
/* 440EP & 440GR are only 440er PPC's without internal SRAM */
#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
/* not all PPC's have internal SRAM usable as L2-cache */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX)
- mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
+ mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ lis r1, 0x0000
+ ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
+ mtdcr L2_CACHE_CFG,r1
#endif
lis r2,0x7fff
ori r2,r2,0xffff
- mfdcr r1,isram0_dpc
+ mfdcr r1,ISRAM0_DPC
and r1,r1,r2 /* Disable parity check */
- mtdcr isram0_dpc,r1
- mfdcr r1,isram0_pmeg
+ mtdcr ISRAM0_DPC,r1
+ mfdcr r1,ISRAM0_PMEG
and r1,r1,r2 /* Disable pwr mgmt */
- mtdcr isram0_pmeg,r1
+ mtdcr ISRAM0_PMEG,r1
lis r1,0x8000 /* BAS = 8000_0000 */
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
ori r1,r1,0x0980 /* first 64k */
- mtdcr isram0_sb0cr,r1
+ mtdcr ISRAM0_SB0CR,r1
lis r1,0x8001
ori r1,r1,0x0980 /* second 64k */
- mtdcr isram0_sb1cr,r1
+ mtdcr ISRAM0_SB1CR,r1
lis r1, 0x8002
ori r1,r1, 0x0980 /* third 64k */
- mtdcr isram0_sb2cr,r1
+ mtdcr ISRAM0_SB2CR,r1
lis r1, 0x8003
ori r1,r1, 0x0980 /* fourth 64k */
- mtdcr isram0_sb3cr,r1
-#elif defined(CONFIG_440SPE)
- lis r1,0x0000 /* BAS = 0000_0000 */
+ mtdcr ISRAM0_SB3CR,r1
+#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ lis r1,0x0000 /* BAS = X_0000_0000 */
ori r1,r1,0x0984 /* first 64k */
- mtdcr isram0_sb0cr,r1
+ mtdcr ISRAM0_SB0CR,r1
lis r1,0x0001
ori r1,r1,0x0984 /* second 64k */
- mtdcr isram0_sb1cr,r1
+ mtdcr ISRAM0_SB1CR,r1
lis r1, 0x0002
ori r1,r1, 0x0984 /* third 64k */
- mtdcr isram0_sb2cr,r1
+ mtdcr ISRAM0_SB2CR,r1
lis r1, 0x0003
ori r1,r1, 0x0984 /* fourth 64k */
- mtdcr isram0_sb3cr,r1
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
- lis r1,0x4000 /* BAS = 8000_0000 */
- ori r1,r1,0x4580 /* 16k */
- mtdcr isram0_sb0cr,r1
+ mtdcr ISRAM0_SB3CR,r1
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ lis r2,0x7fff
+ ori r2,r2,0xffff
+ mfdcr r1,ISRAM1_DPC
+ and r1,r1,r2 /* Disable parity check */
+ mtdcr ISRAM1_DPC,r1
+ mfdcr r1,ISRAM1_PMEG
+ and r1,r1,r2 /* Disable pwr mgmt */
+ mtdcr ISRAM1_PMEG,r1
+
+ lis r1,0x0004 /* BAS = 4_0004_0000 */
+ ori r1,r1,0x0984 /* 64k */
+ mtdcr ISRAM1_SB0CR,r1
+#endif
#elif defined(CONFIG_460SX)
lis r1,0x0000 /* BAS = 0000_0000 */
ori r1,r1,0x0B84 /* first 128k */
- mtdcr isram0_sb0cr,r1
+ mtdcr ISRAM0_SB0CR,r1
lis r1,0x0001
ori r1,r1,0x0B84 /* second 128k */
- mtdcr isram0_sb1cr,r1
+ mtdcr ISRAM0_SB1CR,r1
lis r1, 0x0002
ori r1,r1, 0x0B84 /* third 128k */
- mtdcr isram0_sb2cr,r1
+ mtdcr ISRAM0_SB2CR,r1
lis r1, 0x0003
ori r1,r1, 0x0B84 /* fourth 128k */
- mtdcr isram0_sb3cr,r1
+ mtdcr ISRAM0_SB3CR,r1
#elif defined(CONFIG_440GP)
ori r1,r1,0x0380 /* 8k rw */
- mtdcr isram0_sb0cr,r1
- mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
+ mtdcr ISRAM0_SB0CR,r1
+ mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
#endif
#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
/*----------------------------------------------------------------*/
/* Setup the stack in internal SRAM */
/*----------------------------------------------------------------*/
- lis r1,CFG_INIT_RAM_ADDR@h
- ori r1,r1,CFG_INIT_SP_OFFSET@l
+ lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
li r0,0
stwu r0,-4(r1)
stwu r0,-4(r1) /* Terminate call chain */
@@ -852,18 +867,18 @@ _start:
sync
/* Set-up icache cacheability. */
- lis r1, CFG_ICACHE_SACR_VALUE@h
- ori r1, r1, CFG_ICACHE_SACR_VALUE@l
+ lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
+ ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
mticcr r1
isync
/* Set-up dcache cacheability. */
- lis r1, CFG_DCACHE_SACR_VALUE@h
- ori r1, r1, CFG_DCACHE_SACR_VALUE@l
+ lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
+ ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
mtdccr r1
- addis r1,r0,CFG_INIT_RAM_ADDR@h
- ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
+ addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
@@ -908,31 +923,32 @@ _start:
bl invalidate_dcache
/* Set-up icache cacheability. */
- lis r4, CFG_ICACHE_SACR_VALUE@h
- ori r4, r4, CFG_ICACHE_SACR_VALUE@l
+ lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
+ ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
mticcr r4
isync
/* Set-up dcache cacheability. */
- lis r4, CFG_DCACHE_SACR_VALUE@h
- ori r4, r4, CFG_DCACHE_SACR_VALUE@l
+ lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
+ ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
mtdccr r4
-#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
+#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
+ && !defined (CONFIG_XILINX_405)
/*----------------------------------------------------------------------- */
/* Tune the speed and size for flash CS0 */
/*----------------------------------------------------------------------- */
bl ext_bus_cntlr_init
#endif
-#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
+#if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
/*
* For boards that don't have OCM and can't use the data cache
* for their primordial stack, setup stack here directly after the
* SDRAM is initialized in ext_bus_cntlr_init.
*/
- lis r1, CFG_INIT_RAM_ADDR@h
- ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
+ lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
@@ -946,7 +962,7 @@ _start:
ori r0, r0, RESET_VECTOR@l
stwu r1, -8(r1) /* Save back chain and move SP */
stw r0, +12(r1) /* Save return addr (underflow vect) */
-#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
+#endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
#if defined(CONFIG_405EP)
/*----------------------------------------------------------------------- */
@@ -959,25 +975,25 @@ _start:
bl ppc405ep_init /* do ppc405ep specific init */
#endif /* CONFIG_405EP */
-#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
+#if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
#if defined(CONFIG_405EZ)
/********************************************************************
* Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
*******************************************************************/
/*
* We can map the OCM on the PLB3, so map it at
- * CFG_OCM_DATA_ADDR + 0x8000
+ * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
*/
- lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
- ori r3,r3,CFG_OCM_DATA_ADDR@l
+ lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
+ ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
mtdcr ocmplb3cr1,r3 /* Set PLB Access */
ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
mtdcr ocmplb3cr2,r3 /* Set PLB Access */
isync
- lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
- ori r3,r3,CFG_OCM_DATA_ADDR@l
+ lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
+ ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
mtdcr ocmdscr1, r3 /* Set Data Side */
mtdcr ocmiscr1, r3 /* Set Instruction Side */
@@ -1003,8 +1019,8 @@ _start:
mtdcr ocmdscntl, r4 /* set data-side IRAM config */
isync
- lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
- ori r3,r3,CFG_OCM_DATA_ADDR@l
+ lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
+ ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
mtdcr ocmdsarc, r3
addis r4, 0, 0xC000 /* OCM data area enabled */
mtdcr ocmdscntl, r4
@@ -1015,26 +1031,26 @@ _start:
/*----------------------------------------------------------------------- */
/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
/*----------------------------------------------------------------------- */
-#ifdef CFG_INIT_DCACHE_CS
+#ifdef CONFIG_SYS_INIT_DCACHE_CS
li r4, PBxAP
mtdcr ebccfga, r4
- lis r4, CFG_INIT_DCACHE_PBxAR@h
- ori r4, r4, CFG_INIT_DCACHE_PBxAR@l
+ lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
+ ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
mtdcr ebccfgd, r4
addi r4, 0, PBxCR
mtdcr ebccfga, r4
- lis r4, CFG_INIT_DCACHE_PBxCR@h
- ori r4, r4, CFG_INIT_DCACHE_PBxCR@l
+ lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
+ ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
mtdcr ebccfgd, r4
/*
* Enable the data cache for the 128MB storage access control region
- * at CFG_INIT_RAM_ADDR.
+ * at CONFIG_SYS_INIT_RAM_ADDR.
*/
mfdccr r4
- oris r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
- ori r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
+ oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
+ ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
mtdccr r4
/*
@@ -1044,11 +1060,11 @@ _start:
*/
li r0, 0
- lis r3, CFG_INIT_RAM_ADDR@h
- ori r3, r3, CFG_INIT_RAM_ADDR@l
+ lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
- lis r4, CFG_INIT_RAM_END@h
- ori r4, r4, CFG_INIT_RAM_END@l
+ lis r4, CONFIG_SYS_INIT_RAM_END@h
+ ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
/*
* Convert the size, in bytes, to the number of cache lines/blocks
@@ -1072,18 +1088,18 @@ _start:
* Load the initial stack pointer and data area and convert the size,
* in bytes, to the number of words to initialize to a known value.
*/
- lis r1, CFG_INIT_RAM_ADDR@h
- ori r1, r1, CFG_INIT_SP_OFFSET@l
+ lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
- lis r4, (CFG_INIT_RAM_END >> 2)@h
- ori r4, r4, (CFG_INIT_RAM_END >> 2)@l
+ lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
+ ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
mtctr r4
- lis r2, CFG_INIT_RAM_ADDR@h
- ori r2, r2, CFG_INIT_RAM_END@l
+ lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
- lis r4, CFG_INIT_RAM_PATTERN@h
- ori r4, r4, CFG_INIT_RAM_PATTERN@l
+ lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
+ ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
..stackloop:
stwu r4, -4(r2)
@@ -1106,15 +1122,15 @@ _start:
stwu r1, -8(r1) /* Save back chain and move SP */
stw r0, +12(r1) /* Save return addr (underflow vect) */
-#elif defined(CFG_TEMP_STACK_OCM) && \
- (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
+#elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
+ (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
/*
* Stack in OCM.
*/
/* Set up Stack at top of OCM */
- lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
- ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
+ lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
+ ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
/* Set up a zeroized stack frame so that backtrace works right */
li r0, 0
@@ -1130,7 +1146,7 @@ _start:
ori r0, r0, RESET_VECTOR@l
stwu r1, -8(r1) /* Save back chain and move SP */
stw r0, +12(r1) /* Save return addr (underflow vect) */
-#endif /* CFG_INIT_DCACHE_CS */
+#endif /* CONFIG_SYS_INIT_DCACHE_CS */
#ifdef CONFIG_NAND_SPL
bl nand_boot_common /* will not return */
@@ -1341,7 +1357,7 @@ in32r:
*/
.globl relocate_code
relocate_code:
-#if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS)
+#if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
/*
* We need to flush the initial global data (gd_t) before the dcache
* will be invalidated.
@@ -1354,10 +1370,10 @@ relocate_code:
/* Flush initial global data range */
mr r3, r4
- addi r4, r4, CFG_GBL_DATA_SIZE@l
+ addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
bl flush_dcache_range
-#if defined(CFG_INIT_DCACHE_CS)
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
/*
* Undo the earlier data cache set-up for the primordial stack and
* data area. First, invalidate the data cache and then disable data
@@ -1366,19 +1382,19 @@ relocate_code:
*/
/* Invalidate the primordial stack and data area in cache */
- lis r3, CFG_INIT_RAM_ADDR@h
- ori r3, r3, CFG_INIT_RAM_ADDR@l
+ lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
- lis r4, CFG_INIT_RAM_END@h
- ori r4, r4, CFG_INIT_RAM_END@l
+ lis r4, CONFIG_SYS_INIT_RAM_END@h
+ ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
add r4, r4, r3
bl invalidate_dcache_range
/* Disable cacheability for the region */
mfdccr r3
- lis r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
- ori r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
+ lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
+ ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
and r3, r3, r4
mtdccr r3
@@ -1394,15 +1410,15 @@ relocate_code:
lis r3, PBxCR_VAL@h
ori r3, r3, PBxCR_VAL@l
mtdcr ebccfgd, r3
-#endif /* defined(CFG_INIT_DCACHE_CS) */
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
/* Restore registers */
mr r3, r9
mr r4, r10
mr r5, r11
-#endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */
+#endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/*
* Unlock the previously locked d-cache
*/
@@ -1424,7 +1440,7 @@ relocate_code:
mtspr dtv3,r6
msync
isync
-#endif /* CFG_INIT_RAM_DCACHE */
+#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
@@ -1439,11 +1455,15 @@ relocate_code:
dccci 0,0 /* Invalidate data cache, now no longer our stack */
sync
isync
-#ifdef CFG_TLB_FOR_BOOT_FLASH
- addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */
+
+ /* Clear all potential pending exceptions */
+ mfspr r1,mcsr
+ mtspr mcsr,r1
+#ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
+ addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
#else
addi r1,r0,0x0000 /* Default TLB entry is #0 */
-#endif /* CFG_TLB_FOR_BOOT_FLASH */
+#endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */
tlbre r0,r1,0x0002 /* Read contents */
ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
tlbwe r0,r1,0x0002 /* Save it out */
@@ -1455,8 +1475,8 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
li r6, L1_CACHE_BYTES /* Cache Line Size */
@@ -1464,7 +1484,7 @@ relocate_code:
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
@@ -1775,74 +1795,74 @@ ppc405ep_init:
lis r3,GPIO0_OSRH@h /* config GPIO output select */
ori r3,r3,GPIO0_OSRH@l
- lis r4,CFG_GPIO0_OSRH@h
- ori r4,r4,CFG_GPIO0_OSRH@l
+ lis r4,CONFIG_SYS_GPIO0_OSRH@h
+ ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
stw r4,0(r3)
lis r3,GPIO0_OSRL@h
ori r3,r3,GPIO0_OSRL@l
- lis r4,CFG_GPIO0_OSRL@h
- ori r4,r4,CFG_GPIO0_OSRL@l
+ lis r4,CONFIG_SYS_GPIO0_OSRL@h
+ ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
stw r4,0(r3)
lis r3,GPIO0_ISR1H@h /* config GPIO input select */
ori r3,r3,GPIO0_ISR1H@l
- lis r4,CFG_GPIO0_ISR1H@h
- ori r4,r4,CFG_GPIO0_ISR1H@l
+ lis r4,CONFIG_SYS_GPIO0_ISR1H@h
+ ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
stw r4,0(r3)
lis r3,GPIO0_ISR1L@h
ori r3,r3,GPIO0_ISR1L@l
- lis r4,CFG_GPIO0_ISR1L@h
- ori r4,r4,CFG_GPIO0_ISR1L@l
+ lis r4,CONFIG_SYS_GPIO0_ISR1L@h
+ ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
stw r4,0(r3)
lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
ori r3,r3,GPIO0_TSRH@l
- lis r4,CFG_GPIO0_TSRH@h
- ori r4,r4,CFG_GPIO0_TSRH@l
+ lis r4,CONFIG_SYS_GPIO0_TSRH@h
+ ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
stw r4,0(r3)
lis r3,GPIO0_TSRL@h
ori r3,r3,GPIO0_TSRL@l
- lis r4,CFG_GPIO0_TSRL@h
- ori r4,r4,CFG_GPIO0_TSRL@l
+ lis r4,CONFIG_SYS_GPIO0_TSRL@h
+ ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
stw r4,0(r3)
lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
ori r3,r3,GPIO0_TCR@l
- lis r4,CFG_GPIO0_TCR@h
- ori r4,r4,CFG_GPIO0_TCR@l
+ lis r4,CONFIG_SYS_GPIO0_TCR@h
+ ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
stw r4,0(r3)
li r3,pb1ap /* program EBC bank 1 for RTC access */
mtdcr ebccfga,r3
- lis r3,CFG_EBC_PB1AP@h
- ori r3,r3,CFG_EBC_PB1AP@l
+ lis r3,CONFIG_SYS_EBC_PB1AP@h
+ ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
mtdcr ebccfgd,r3
li r3,pb1cr
mtdcr ebccfga,r3
- lis r3,CFG_EBC_PB1CR@h
- ori r3,r3,CFG_EBC_PB1CR@l
+ lis r3,CONFIG_SYS_EBC_PB1CR@h
+ ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
mtdcr ebccfgd,r3
li r3,pb1ap /* program EBC bank 1 for RTC access */
mtdcr ebccfga,r3
- lis r3,CFG_EBC_PB1AP@h
- ori r3,r3,CFG_EBC_PB1AP@l
+ lis r3,CONFIG_SYS_EBC_PB1AP@h
+ ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
mtdcr ebccfgd,r3
li r3,pb1cr
mtdcr ebccfga,r3
- lis r3,CFG_EBC_PB1CR@h
- ori r3,r3,CFG_EBC_PB1CR@l
+ lis r3,CONFIG_SYS_EBC_PB1CR@h
+ ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
mtdcr ebccfgd,r3
li r3,pb4ap /* program EBC bank 4 for FPGA access */
mtdcr ebccfga,r3
- lis r3,CFG_EBC_PB4AP@h
- ori r3,r3,CFG_EBC_PB4AP@l
+ lis r3,CONFIG_SYS_EBC_PB4AP@h
+ ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
mtdcr ebccfgd,r3
li r3,pb4cr
mtdcr ebccfga,r3
- lis r3,CFG_EBC_PB4CR@h
- ori r3,r3,CFG_EBC_PB4CR@l
+ lis r3,CONFIG_SYS_EBC_PB4CR@h
+ ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
mtdcr ebccfgd,r3
#endif
@@ -2111,20 +2131,20 @@ nand_boot_common:
* First initialize SDRAM. It has to be available *before* calling
* nand_boot().
*/
- lis r3,CFG_SDRAM_BASE@h
- ori r3,r3,CFG_SDRAM_BASE@l
+ lis r3,CONFIG_SYS_SDRAM_BASE@h
+ ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
bl initdram
/*
* Now copy the 4k SPL code into SDRAM and continue execution
* from there.
*/
- lis r3,CFG_NAND_BOOT_SPL_DST@h
- ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
- lis r4,CFG_NAND_BOOT_SPL_SRC@h
- ori r4,r4,CFG_NAND_BOOT_SPL_SRC@l
- lis r5,CFG_NAND_BOOT_SPL_SIZE@h
- ori r5,r5,CFG_NAND_BOOT_SPL_SIZE@l
+ lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
+ ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
+ lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
+ ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
+ lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
+ ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
bl nand_boot_relocate
/*
diff --git a/cpu/ppc4xx/usb.c b/cpu/ppc4xx/usb.c
index cb8d5c7..592efe7 100644
--- a/cpu/ppc4xx/usb.c
+++ b/cpu/ppc4xx/usb.c
@@ -23,7 +23,7 @@
#include <common.h>
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
#ifdef CONFIG_4xx_DCACHE
#include <asm/mmu.h>
@@ -63,4 +63,4 @@ int usb_cpu_init_fail(void)
return 0;
}
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c
index 5dbd842..2607ed6 100644
--- a/cpu/ppc4xx/usb_ohci.c
+++ b/cpu/ppc4xx/usb_ohci.c
@@ -660,7 +660,7 @@ static void td_fill (ohci_t *ohci, unsigned int info,
td->index = index;
td->data = (__u32)data;
#ifdef OHCI_FILL_TRACE
- if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
+ if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
for (i = 0; i < len; i++)
printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
printf("\n");
@@ -761,7 +761,7 @@ static void dl_transfer_length(td_t * td)
tdCBP = ohci_cpu_to_le32 (td->hwCBP);
- if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
+ if (!(usb_pipecontrol(lurb_priv->pipe) &&
((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
if (tdBE != 0) {
if (td->hwCBP == 0)
@@ -1023,7 +1023,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
urb_priv.actual_length = 0;
pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
#endif
- if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+ if (usb_pipeint(pipe)) {
info("Root-Hub submit IRQ: NOT implemented");
return 0;
}
@@ -1248,7 +1248,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
/* allow more time for a BULK device to react - some are slow */
#define BULK_TO 5000 /* timeout in milliseconds */
- if (usb_pipetype (pipe) == PIPE_BULK)
+ if (usb_pipebulk(pipe))
timeout = BULK_TO;
else
timeout = 100;
@@ -1600,9 +1600,9 @@ int usb_lowlevel_init(void)
gohci.sleeping = 0;
gohci.irq = -1;
#if defined(CONFIG_440EP)
- gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
-#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST)
- gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
+ gohci.regs = (struct ohci_regs *)(CONFIG_SYS_PERIPHERAL_BASE | 0x1000);
+#elif defined(CONFIG_440EPX) || defined(CONFIG_SYS_USB_HOST)
+ gohci.regs = (struct ohci_regs *)(CONFIG_SYS_USB_HOST);
#endif
gohci.flags = 0;
diff --git a/cpu/ppc4xx/usbdev.h b/cpu/ppc4xx/usbdev.h
index 3446d98..ef6a2da 100644
--- a/cpu/ppc4xx/usbdev.h
+++ b/cpu/ppc4xx/usbdev.h
@@ -1,31 +1,31 @@
#include <config.h>
/*Common Registers*/
-#define USB2D0_INTRIN_16 (CFG_USB_DEVICE | 0x100)
-#define USB2D0_POWER_8 (CFG_USB_DEVICE | 0x102)
-#define USB2D0_FADDR_8 (CFG_USB_DEVICE | 0x103)
-#define USB2D0_INTRINE_16 (CFG_USB_DEVICE | 0x104)
-#define USB2D0_INTROUT_16 (CFG_USB_DEVICE | 0x106)
-#define USB2D0_INTRUSBE_8 (CFG_USB_DEVICE | 0x108)
-#define USB2D0_INTRUSB_8 (CFG_USB_DEVICE | 0x109)
-#define USB2D0_INTROUTE_16 (CFG_USB_DEVICE | 0x10a)
-#define USB2D0_TSTMODE_8 (CFG_USB_DEVICE | 0x10c)
-#define USB2D0_INDEX_8 (CFG_USB_DEVICE | 0x10d)
-#define USB2D0_FRAME_16 (CFG_USB_DEVICE | 0x10e)
+#define USB2D0_INTRIN_16 (CONFIG_SYS_USB_DEVICE | 0x100)
+#define USB2D0_POWER_8 (CONFIG_SYS_USB_DEVICE | 0x102)
+#define USB2D0_FADDR_8 (CONFIG_SYS_USB_DEVICE | 0x103)
+#define USB2D0_INTRINE_16 (CONFIG_SYS_USB_DEVICE | 0x104)
+#define USB2D0_INTROUT_16 (CONFIG_SYS_USB_DEVICE | 0x106)
+#define USB2D0_INTRUSBE_8 (CONFIG_SYS_USB_DEVICE | 0x108)
+#define USB2D0_INTRUSB_8 (CONFIG_SYS_USB_DEVICE | 0x109)
+#define USB2D0_INTROUTE_16 (CONFIG_SYS_USB_DEVICE | 0x10a)
+#define USB2D0_TSTMODE_8 (CONFIG_SYS_USB_DEVICE | 0x10c)
+#define USB2D0_INDEX_8 (CONFIG_SYS_USB_DEVICE | 0x10d)
+#define USB2D0_FRAME_16 (CONFIG_SYS_USB_DEVICE | 0x10e)
/*Indexed Registers*/
-#define USB2D0_INCSR0_8 (CFG_USB_DEVICE | 0x110)
-#define USB2D0_INCSR_16 (CFG_USB_DEVICE | 0x110)
-#define USB2D0_INMAXP_16 (CFG_USB_DEVICE | 0x112)
-#define USB2D0_OUTCSR_16 (CFG_USB_DEVICE | 0x114)
-#define USB2D0_OUTMAXP_16 (CFG_USB_DEVICE | 0x116)
-#define USB2D0_OUTCOUNT0_8 (CFG_USB_DEVICE | 0x11a)
-#define USB2D0_OUTCOUNT_16 (CFG_USB_DEVICE | 0x11a)
+#define USB2D0_INCSR0_8 (CONFIG_SYS_USB_DEVICE | 0x110)
+#define USB2D0_INCSR_16 (CONFIG_SYS_USB_DEVICE | 0x110)
+#define USB2D0_INMAXP_16 (CONFIG_SYS_USB_DEVICE | 0x112)
+#define USB2D0_OUTCSR_16 (CONFIG_SYS_USB_DEVICE | 0x114)
+#define USB2D0_OUTMAXP_16 (CONFIG_SYS_USB_DEVICE | 0x116)
+#define USB2D0_OUTCOUNT0_8 (CONFIG_SYS_USB_DEVICE | 0x11a)
+#define USB2D0_OUTCOUNT_16 (CONFIG_SYS_USB_DEVICE | 0x11a)
/*FIFOs*/
-#define USB2D0_FIFO_0 (CFG_USB_DEVICE | 0x120)
-#define USB2D0_FIFO_1 (CFG_USB_DEVICE | 0x124)
-#define USB2D0_FIFO_2 (CFG_USB_DEVICE | 0x128)
-#define USB2D0_FIFO_3 (CFG_USB_DEVICE | 0x12c)
+#define USB2D0_FIFO_0 (CONFIG_SYS_USB_DEVICE | 0x120)
+#define USB2D0_FIFO_1 (CONFIG_SYS_USB_DEVICE | 0x124)
+#define USB2D0_FIFO_2 (CONFIG_SYS_USB_DEVICE | 0x128)
+#define USB2D0_FIFO_3 (CONFIG_SYS_USB_DEVICE | 0x12c)
void usb_dev_init(void);
diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk
index f0b86b7..af910e2 100644
--- a/cpu/pxa/config.mk
+++ b/cpu/pxa/config.mk
@@ -32,4 +32,5 @@ PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale
#
# ========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index 0ee8180..e84cb5b 100644
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -44,7 +44,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;
diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c
index df537c4..6b72ba1 100644
--- a/cpu/pxa/i2c.c
+++ b/cpu/pxa/i2c.c
@@ -37,7 +37,7 @@
#ifdef CONFIG_HARD_I2C
/*
- * - CFG_I2C_SPEED
+ * - CONFIG_SYS_I2C_SPEED
* - I2C_PXA_SLAVE_ADDR
*/
@@ -48,7 +48,7 @@
/*#define DEBUG_I2C 1 /###* activate local debugging output */
#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */
-#if (CFG_I2C_SPEED == 400000)
+#if (CONFIG_SYS_I2C_SPEED == 400000)
#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
#else
#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
@@ -254,7 +254,7 @@ i2c_transfer_finish:
void i2c_init(int speed, int slaveaddr)
{
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
/* call board specific i2c bus reset routine before accessing the */
/* environment, which might be in a chip on that bus. For details */
/* about this problem see doc/I2C_Edge_Conditions. */
@@ -329,7 +329,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
* send memory address bytes;
* alen defines how much bytes we have to send.
*/
- /*addr &= ((1 << CFG_EEPROM_PAGE_WRITE_BITS)-1); */
+ /*addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); */
addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
@@ -455,19 +455,4 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
}
-uchar i2c_reg_read (uchar chip, uchar reg)
-{
- uchar buf;
-
- PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg));
- i2c_read(chip, reg, 1, &buf, 1);
- return (buf);
-}
-
-void i2c_reg_write(uchar chip, uchar reg, uchar val)
-{
- PRINTD(("i2c_reg_write(chip=0x%02x, reg=0x%02x, val=0x%02x)\n",chip,reg,val));
- i2c_write(chip, reg, 1, &val, 1);
-}
-
#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/interrupts.c
index 8b577e1..ec8fb9e 100644
--- a/cpu/pxa/interrupts.c
+++ b/cpu/pxa/interrupts.c
@@ -78,10 +78,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) {
tmo = usec / 1000;
- tmo *= CFG_HZ;
+ tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
} else {
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -109,6 +109,6 @@ unsigned long long get_ticks(void)
ulong get_tbclk (void)
{
ulong tbclk;
- tbclk = CFG_HZ;
+ tbclk = CONFIG_SYS_HZ;
return tbclk;
}
diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c
index 121dcbe..d735c8d 100644
--- a/cpu/pxa/mmc.c
+++ b/cpu/pxa/mmc.c
@@ -234,7 +234,7 @@ mmc_read(ulong src, uchar * dst, int size)
mmc_block_size = MMC_BLOCK_SIZE;
mmc_block_address = ~(mmc_block_size - 1);
- src -= CFG_MMC_BASE;
+ src -= CONFIG_SYS_MMC_BASE;
end = src + size;
part_start = ~mmc_block_address & src;
part_end = ~mmc_block_address & end;
@@ -310,7 +310,7 @@ mmc_write(uchar * src, ulong dst, int size)
mmc_block_size = MMC_BLOCK_SIZE;
mmc_block_address = ~(mmc_block_size - 1);
- dst -= CFG_MMC_BASE;
+ dst -= CONFIG_SYS_MMC_BASE;
end = dst + size;
part_start = ~mmc_block_address & dst;
part_end = ~mmc_block_address & end;
@@ -379,7 +379,7 @@ mmc_bread(int dev_num, ulong blknr, lbaint_t blkcnt, void *dst)
/****************************************************/
{
int mmc_block_size = MMC_BLOCK_SIZE;
- ulong src = blknr * mmc_block_size + CFG_MMC_BASE;
+ ulong src = blknr * mmc_block_size + CONFIG_SYS_MMC_BASE;
mmc_read(src, (uchar *) dst, blkcnt * mmc_block_size);
return blkcnt;
@@ -575,8 +575,8 @@ mmc_init(int verbose)
break;
}
- /* Select 3.2-3.3 and 3.3-3.4V */
- resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0020, 0,
+ /* Select 3.2-3.3V and 3.3-3.4V */
+ resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0030, 0x0000,
MMC_CMDAT_R3 | (retries < 2 ? 0
: MMC_CMDAT_INIT));
if (resp[0] & 0x80000000) {
@@ -652,8 +652,8 @@ int mmc_ident(block_dev_desc_t * dev)
int mmc2info(ulong addr)
{
- if (addr >= CFG_MMC_BASE
- && addr < CFG_MMC_BASE + (mmc_dev.lba * mmc_dev.blksz)) {
+ if (addr >= CONFIG_SYS_MMC_BASE
+ && addr < CONFIG_SYS_MMC_BASE + (mmc_dev.lba * mmc_dev.blksz)) {
return 1;
}
return 0;
diff --git a/cpu/pxa/pxafb.c b/cpu/pxa/pxafb.c
index b2caa73..97efcb6 100644
--- a/cpu/pxa/pxafb.c
+++ b/cpu/pxa/pxafb.c
@@ -60,11 +60,11 @@ vidinfo_t panel_info = {
vl_row: 480,
vl_width: 640,
vl_height: 480,
- vl_clkp: CFG_HIGH,
- vl_oep: CFG_HIGH,
- vl_hsp: CFG_HIGH,
- vl_vsp: CFG_HIGH,
- vl_dp: CFG_HIGH,
+ vl_clkp: CONFIG_SYS_HIGH,
+ vl_oep: CONFIG_SYS_HIGH,
+ vl_hsp: CONFIG_SYS_HIGH,
+ vl_vsp: CONFIG_SYS_HIGH,
+ vl_dp: CONFIG_SYS_HIGH,
vl_bpix: LCD_BPP,
vl_lbw: 0,
vl_splt: 0,
@@ -94,11 +94,11 @@ vidinfo_t panel_info = {
vl_row: 480,
vl_width: 157,
vl_height: 118,
- vl_clkp: CFG_HIGH,
- vl_oep: CFG_HIGH,
- vl_hsp: CFG_HIGH,
- vl_vsp: CFG_HIGH,
- vl_dp: CFG_HIGH,
+ vl_clkp: CONFIG_SYS_HIGH,
+ vl_oep: CONFIG_SYS_HIGH,
+ vl_hsp: CONFIG_SYS_HIGH,
+ vl_vsp: CONFIG_SYS_HIGH,
+ vl_dp: CONFIG_SYS_HIGH,
vl_bpix: LCD_BPP,
vl_lbw: 0,
vl_splt: 1,
@@ -127,11 +127,11 @@ vidinfo_t panel_info = {
vl_row: 240,
vl_width: 167,
vl_height: 109,
- vl_clkp: CFG_HIGH,
- vl_oep: CFG_HIGH,
- vl_hsp: CFG_HIGH,
- vl_vsp: CFG_HIGH,
- vl_dp: CFG_HIGH,
+ vl_clkp: CONFIG_SYS_HIGH,
+ vl_oep: CONFIG_SYS_HIGH,
+ vl_hsp: CONFIG_SYS_HIGH,
+ vl_vsp: CONFIG_SYS_HIGH,
+ vl_dp: CONFIG_SYS_HIGH,
vl_bpix: LCD_BPP,
vl_lbw: 1,
vl_splt: 0,
diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S
index 23005e2..63ab0c5 100644
--- a/cpu/pxa/start.S
+++ b/cpu/pxa/start.S
@@ -135,8 +135,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif /* CONFIG_USE_IRQ */
@@ -191,20 +191,20 @@ OSTIMER_BASE: .word 0x40a00000
/* Clock Manager Registers */
#ifdef CONFIG_CPU_MONAHANS
-# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
-# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
-# endif /* !CFG_MONAHANS_RUN_MODE_OSC_RATIO */
-# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
-# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
-# endif /* !CFG_MONAHANS_TURBO_RUN_MODE_RATIO */
+# ifndef CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
+# error "You have to define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO!!"
+# endif /* !CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO */
+# ifndef CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
+# define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
+# endif /* !CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO */
#else /* !CONFIG_CPU_MONAHANS */
-#ifdef CFG_CPUSPEED
+#ifdef CONFIG_SYS_CPUSPEED
CC_BASE: .word 0x41300000
#define CCCR 0x00
-cpuspeed: .word CFG_CPUSPEED
-#else /* !CFG_CPUSPEED */
-#error "You have to define CFG_CPUSPEED!!"
-#endif /* CFG_CPUSPEED */
+cpuspeed: .word CONFIG_SYS_CPUSPEED
+#else /* !CONFIG_SYS_CPUSPEED */
+#error "You have to define CONFIG_SYS_CPUSPEED!!"
+#endif /* CONFIG_SYS_CPUSPEED */
#endif /* CONFIG_CPU_MONAHANS */
/* takes care the CP15 update has taken place */
@@ -245,10 +245,10 @@ cpu_init_crit:
/* set clock speed */
#ifdef CONFIG_CPU_MONAHANS
ldr r0, =ACCR
- ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
+ ldr r1, =(((CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
str r1, [r0]
#else /* !CONFIG_CPU_MONAHANS */
-#ifdef CFG_CPUSPEED
+#ifdef CONFIG_SYS_CPUSPEED
ldr r0, CC_BASE
ldr r1, cpuspeed
str r1, [r0, #CCCR]
@@ -257,7 +257,7 @@ cpu_init_crit:
setspeed_done:
-#endif /* CFG_CPUSPEED */
+#endif /* CONFIG_SYS_CPUSPEED */
#endif /* CONFIG_CPU_MONAHANS */
/*
@@ -336,8 +336,8 @@ setspeed_done:
add r8, sp, #S_PC
ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
@@ -373,8 +373,8 @@ setspeed_done:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c
index aa6f4b7..bd718a6 100644
--- a/cpu/pxa/usb.c
+++ b/cpu/pxa/usb.c
@@ -23,7 +23,7 @@
#include <common.h>
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
#include <asm/arch/pxa-regs.h>
@@ -109,4 +109,4 @@ int usb_cpu_init_fail(void)
}
# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/cpu/s3c44b0/config.mk b/cpu/s3c44b0/config.mk
index 6dc9c46..01e7040 100644
--- a/cpu/s3c44b0/config.mk
+++ b/cpu/s3c44b0/config.mk
@@ -32,4 +32,5 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float
#
# ========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c
index eae6adb..2960f2f 100644
--- a/cpu/s3c44b0/cpu.c
+++ b/cpu/s3c44b0/cpu.c
@@ -188,7 +188,7 @@ int rtc_get (struct rtc_time* tm)
return 0;
}
-void rtc_set (struct rtc_time* tm)
+int rtc_set (struct rtc_time* tm)
{
if(tm->tm_year < 2000)
tm->tm_year -= 1900;
@@ -204,6 +204,8 @@ void rtc_set (struct rtc_time* tm)
BCDMIN = HEX2BCD(tm->tm_min);
BCDSEC = HEX2BCD(tm->tm_sec);
RTCCON &= 1;
+
+ return 0;
}
void rtc_reset (void)
@@ -254,7 +256,7 @@ void i2c_init(int speed, int slaveaddr)
/*
Enable ACK, IICCLK=MCLK/16, enable interrupt
- 75Mhz/16/(12+1) = 390625 Hz
+ 75MHz/16/(12+1) = 390625 Hz
*/
rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC);
IICCON = rIICCON;
diff --git a/cpu/s3c44b0/interrupts.c b/cpu/s3c44b0/interrupts.c
index ed79648..eb23e6a 100644
--- a/cpu/s3c44b0/interrupts.c
+++ b/cpu/s3c44b0/interrupts.c
@@ -80,7 +80,7 @@ void udelay (unsigned long usec)
ulong tmo;
tmo = usec / 1000;
- tmo *= CFG_HZ;
+ tmo *= CONFIG_SYS_HZ;
tmo /= 8;
tmo += get_timer (0);
@@ -120,10 +120,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) {
tmo = usec / 1000;
- tmo *= CFG_HZ;
+ tmo *= CONFIG_SYS_HZ;
tmo /= 8;
} else {
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*8);
}
diff --git a/cpu/s3c44b0/start.S b/cpu/s3c44b0/start.S
index 1d88c1c..f5a3d3a 100644
--- a/cpu/s3c44b0/start.S
+++ b/cpu/s3c44b0/start.S
@@ -157,8 +157,8 @@ vector_copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
diff --git a/cpu/sa1100/config.mk b/cpu/sa1100/config.mk
index 5be7dfb..9ef4a19 100644
--- a/cpu/sa1100/config.mk
+++ b/cpu/sa1100/config.mk
@@ -32,4 +32,5 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
#
# ========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c
index f1bd644..bb4e5a1 100644
--- a/cpu/sa1100/cpu.c
+++ b/cpu/sa1100/cpu.c
@@ -43,7 +43,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;
diff --git a/cpu/sa1100/interrupts.c b/cpu/sa1100/interrupts.c
index 53f2745..2eff045 100644
--- a/cpu/sa1100/interrupts.c
+++ b/cpu/sa1100/interrupts.c
@@ -74,10 +74,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) {
tmo = usec / 1000;
- tmo *= CFG_HZ;
+ tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
} else {
- tmo = usec * CFG_HZ;
+ tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -106,6 +106,6 @@ ulong get_tbclk (void)
{
ulong tbclk;
- tbclk = CFG_HZ;
+ tbclk = CONFIG_SYS_HZ;
return tbclk;
}
diff --git a/cpu/sa1100/start.S b/cpu/sa1100/start.S
index 910650d..278c500 100644
--- a/cpu/sa1100/start.S
+++ b/cpu/sa1100/start.S
@@ -147,8 +147,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -196,7 +196,7 @@ RST_BASE: .word 0x90030000
PWR_BASE: .word 0x90020000
#define PSPR 0x08
#define PPCR 0x14
-cpuspeed: .word CFG_CPUSPEED
+cpuspeed: .word CONFIG_SYS_CPUSPEED
cpu_init_crit:
@@ -288,8 +288,8 @@ cpu_init_crit:
add r8, sp, #S_PC
ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@@ -321,8 +321,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
diff --git a/cpu/sh2/Makefile b/cpu/sh2/Makefile
index 50f6720..e33ba0f 100644
--- a/cpu/sh2/Makefile
+++ b/cpu/sh2/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = cpu.o interrupts.o watchdog.o time.o # cache.o
+OBJS = cpu.o interrupts.o watchdog.o
all: .depend $(START) $(LIB)
diff --git a/cpu/sh2/start.S b/cpu/sh2/start.S
index c4fa688..0ab867d 100644
--- a/cpu/sh2/start.S
+++ b/cpu/sh2/start.S
@@ -73,6 +73,6 @@ loop:
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
-._gd_init: .long (_start - CFG_GBL_DATA_SIZE)
-._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16)
+._gd_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE)
+._stack_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._sh_generic_init: .long sh_generic_init
diff --git a/cpu/sh2/time.c b/cpu/sh2/time.c
deleted file mode 100644
index d6eb0cb..0000000
--- a/cpu/sh2/time.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright (C) 2007,2008 Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Renesas Solutions Corp.
- *
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-#define CMT_CMCSR_INIT 0x0001 /* PCLK/32 */
-#define CMT_CMCSR_CALIB 0x0000
-#define CMT_MAX_COUNTER (0xFFFFFFFF)
-#define CMT_TIMER_RESET (0xFFFF)
-
-static vu_long cmt0_timer;
-
-static void cmt_timer_start(unsigned int timer)
-{
- writew(readw(CMSTR) | 0x01, CMSTR);
-}
-
-static void cmt_timer_stop(unsigned int timer)
-{
- writew(readw(CMSTR) & ~0x01, CMSTR);
-}
-
-int timer_init(void)
-{
- cmt0_timer = 0;
- /* Divide clock by 32 */
- readw(CMCSR_0);
- writew(CMT_CMCSR_INIT, CMCSR_0);
-
- /* User Device 0 only */
- cmt_timer_stop(0);
- set_timer(CMT_TIMER_RESET);
- cmt_timer_start(0);
-
- return 0;
-}
-
-unsigned long long get_ticks(void)
-{
- return cmt0_timer;
-}
-
-static vu_long cmcnt;
-ulong get_timer(ulong base)
-{
- ulong data = readw(CMCNT_0);
-
- if (data >= cmcnt)
- cmcnt = data - cmcnt;
- else
- cmcnt = (CMT_TIMER_RESET - cmcnt) + data;
-
- if ((cmt0_timer + cmcnt) > CMT_MAX_COUNTER)
- cmt0_timer = ((cmt0_timer + cmcnt) - CMT_MAX_COUNTER);
- else
- cmt0_timer += cmcnt;
-
- cmcnt = data;
- return cmt0_timer - base;
-}
-
-void set_timer(ulong t)
-{
- writew((u16) t, CMCOR_0);
-}
-
-void reset_timer(void)
-{
- cmt_timer_stop(0);
- set_timer(CMT_TIMER_RESET);
- cmt0_timer = 0;
- cmt_timer_start(0);
-}
-
-void udelay(unsigned long usec)
-{
- unsigned int start = get_timer(0);
-
- while (get_timer((ulong) start) < (usec * (CFG_HZ / 1000000)))
- continue;
-}
-
-unsigned long get_tbclk(void)
-{
- return CFG_HZ;
-}
diff --git a/cpu/sh3/Makefile b/cpu/sh3/Makefile
index 587413d..35e8f51 100644
--- a/cpu/sh3/Makefile
+++ b/cpu/sh3/Makefile
@@ -32,7 +32,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
SOBJS = start.o
-COBJS = cpu.o interrupts.o watchdog.o time.o cache.o
+COBJS = cpu.o interrupts.o watchdog.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/cpu/sh3/start.S b/cpu/sh3/start.S
index ee0bcdf..c0f8326 100644
--- a/cpu/sh3/start.S
+++ b/cpu/sh3/start.S
@@ -72,6 +72,6 @@ loop:
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
-._gd_init: .long (_start - CFG_GBL_DATA_SIZE)
-._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16)
+._gd_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE)
+._stack_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._sh_generic_init: .long sh_generic_init
diff --git a/cpu/sh3/time.c b/cpu/sh3/time.c
deleted file mode 100644
index 0c273dd..0000000
--- a/cpu/sh3/time.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * (C) Copyright 2007
- * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#define TMU_MAX_COUNTER (~0UL)
-
-static void tmu_timer_start(unsigned int timer)
-{
- if (timer > 2)
- return;
-
- outb(inb(TSTR) | (1 << timer), TSTR);
-}
-
-static void tmu_timer_stop(unsigned int timer)
-{
- u8 val = inb(TSTR);
-
- if (timer > 2)
- return;
- outb(val & ~(1 << timer), TSTR);
-}
-
-int timer_init(void)
-{
- /* Divide clock by 4 */
- outw(0, TCR0);
-
- tmu_timer_stop(0);
- tmu_timer_start(0);
- return 0;
-}
-
-/*
- In theory we should return a true 64bit value (ie something that doesn't
- overflow). However, we don't. Therefore if TMU runs at fastest rate of
- 6.75 MHz this value will wrap after u-boot has been running for approx
- 10 minutes.
-*/
-unsigned long long get_ticks(void)
-{
- return (0 - inl(TCNT0));
-}
-
-unsigned long get_timer(unsigned long base)
-{
- return ((0 - inl(TCNT0)) - base);
-}
-
-void set_timer(unsigned long t)
-{
- outl(0 - t, TCNT0);
-}
-
-void reset_timer(void)
-{
- tmu_timer_stop(0);
- set_timer(0);
- tmu_timer_start(0);
-}
-
-void udelay(unsigned long usec)
-{
- unsigned int start = get_timer(0);
- unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000));
-
- while (get_timer(0) < end)
- continue;
-}
-
-unsigned long get_tbclk(void)
-{
- return CFG_HZ;
-}
diff --git a/cpu/sh4/Makefile b/cpu/sh4/Makefile
index d3c5eef..3c96a49 100644
--- a/cpu/sh4/Makefile
+++ b/cpu/sh4/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
SOBJS = start.o
-COBJS = cpu.o interrupts.o watchdog.o time.o cache.o
+COBJS = cpu.o interrupts.o watchdog.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/cpu/sh4/start.S b/cpu/sh4/start.S
index a68ebb8..711ae66 100644
--- a/cpu/sh4/start.S
+++ b/cpu/sh4/start.S
@@ -69,6 +69,6 @@ loop:
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
-._gd_init: .long (_start - CFG_GBL_DATA_SIZE)
-._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16)
+._gd_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE)
+._stack_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._sh_generic_init: .long sh_generic_init
diff --git a/cpu/sh4/time.c b/cpu/sh4/time.c
deleted file mode 100644
index 5f8a3a0..0000000
--- a/cpu/sh4/time.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * (C) Copyright 2007
- * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-#define TMU_MAX_COUNTER (~0UL)
-
-static void tmu_timer_start (unsigned int timer)
-{
- if (timer > 2)
- return;
-
- *((volatile unsigned char *) TSTR) |= (1 << timer);
-}
-
-static void tmu_timer_stop (unsigned int timer)
-{
- u8 val = *((volatile u8 *)TSTR);
- if (timer > 2)
- return;
- *((volatile unsigned char *)TSTR) = val &~(1 << timer);
-}
-
-int timer_init (void)
-{
- /* Divide clock by 4 */
- *(volatile u16 *)TCR0 = 0;
-
- tmu_timer_stop(0);
- tmu_timer_start(0);
- return 0;
-}
-
-/*
- In theory we should return a true 64bit value (ie something that doesn't
- overflow). However, we don't. Therefore if TMU runs at fastest rate of
- 6.75 MHz this value will wrap after u-boot has been running for approx
- 10 minutes.
-*/
-unsigned long long get_ticks (void)
-{
- return (0 - *((volatile u32 *) TCNT0));
-}
-
-unsigned long get_timer (unsigned long base)
-{
- return ((0 - *((volatile u32 *) TCNT0)) - base);
-}
-
-void set_timer (unsigned long t)
-{
- *((volatile unsigned int *) TCNT0) = (0 - t);
-}
-
-void reset_timer (void)
-{
- tmu_timer_stop(0);
- set_timer (0);
- tmu_timer_start(0);
-}
-
-void udelay (unsigned long usec)
-{
- unsigned int start = get_timer (0);
- unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000));
-
- while (get_timer (0) < end)
- continue;
-}
-
-unsigned long get_tbclk (void)
-{
- return CFG_HZ;
-}
diff --git a/cpu/sh4/watchdog.c b/cpu/sh4/watchdog.c
index 346e217..f692429 100644
--- a/cpu/sh4/watchdog.c
+++ b/cpu/sh4/watchdog.c
@@ -17,34 +17,55 @@
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#define WDT_BASE WTCNT
-static unsigned char cnt_read (void){
- return *((volatile unsigned char *)(WDT_BASE + 0x00));
+#define WDT_WD (1 << 6)
+#define WDT_RST_P (0)
+#define WDT_RST_M (1 << 5)
+#define WDT_ENABLE (1 << 7)
+
+#if defined(CONFIG_WATCHDOG)
+static unsigned char csr_read(void)
+{
+ return inb(WDT_BASE + 0x04);
}
-static unsigned char csr_read (void){
- return *((volatile unsigned char *)(WDT_BASE + 0x04));
+static void cnt_write(unsigned char value)
+{
+ outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
}
-static void cnt_write (unsigned char value){
- while (csr_read() & (1 << 5)) {
- /* delay */
- }
- *((volatile unsigned short *)(WDT_BASE + 0x00))
- = ((unsigned short) value) | 0x5A00;
+static void csr_write(unsigned char value)
+{
+ outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
}
-static void csr_write (unsigned char value){
- *((volatile unsigned short *)(WDT_BASE + 0x04))
- = ((unsigned short) value) | 0xA500;
+void watchdog_reset(void)
+{
+ outl(0x55000000, WDT_BASE + 0x08);
}
+int watchdog_init(void)
+{
+ /* Set overflow time*/
+ cnt_write(0);
+ /* Power on reset */
+ csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
+
+ return 0;
+}
-int watchdog_init (void){ return 0; }
+int watchdog_disable(void)
+{
+ csr_write(csr_read() & ~WDT_ENABLE);
+ return 0;
+}
+#endif
-void reset_cpu (unsigned long ignored)
+void reset_cpu(unsigned long ignored)
{
- while(1);
+ while (1)
+ ;
}