summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
authorWolfgang Denk <wd@denx.de>2009-10-24 22:25:08 +0200
committerWolfgang Denk <wd@denx.de>2009-10-24 22:25:08 +0200
commit4ee63268152594bb7af6bec2b59d53bba68082bf (patch)
tree9232060ebf7ec2aff40f007cbf099e9a58a8a96a /cpu
parent62506ae1401c69f208b6aed1111ac57d820c06a0 (diff)
parentcfc25874624a328f53ad59b1206e2103f2e62d74 (diff)
downloadu-boot-imx-4ee63268152594bb7af6bec2b59d53bba68082bf.zip
u-boot-imx-4ee63268152594bb7af6bec2b59d53bba68082bf.tar.gz
u-boot-imx-4ee63268152594bb7af6bec2b59d53bba68082bf.tar.bz2
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Diffstat (limited to 'cpu')
-rw-r--r--cpu/ppc4xx/cpu.c9
-rw-r--r--cpu/ppc4xx/cpu_init.c69
-rw-r--r--cpu/ppc4xx/fdt.c10
3 files changed, 85 insertions, 3 deletions
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index a9a0ac3..e1b00a7 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -608,10 +608,17 @@ int checkcpu (void)
break;
}
- printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
+ printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
+ strmhz(buf, clock),
sys_info.freqPLB / 1000000,
get_OPB_freq() / 1000000,
sys_info.freqEBC / 1000000);
+#if defined(CONFIG_PCI) && \
+ (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRX))
+ printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
+#endif
+ printf(")\n");
if (addstr[0] != 0)
printf(" %s\n", addstr);
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index a00da40..ccd9993 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -330,3 +330,72 @@ int cpu_init_r (void)
return 0;
}
+
+#if defined(CONFIG_PCI) && \
+ (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRX))
+/*
+ * 440EP(x)/GR(x) PCI async/sync clocking restriction:
+ *
+ * In asynchronous PCI mode, the synchronous PCI clock must meet
+ * certain requirements. The following equation describes the
+ * relationship that must be maintained between the asynchronous PCI
+ * clock and synchronous PCI clock. Select an appropriate PCI:PLB
+ * ratio to maintain the relationship:
+ *
+ * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
+ */
+static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async)
+{
+ if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000)))
+ return 0;
+ else
+ return 1;
+}
+
+int ppc4xx_pci_sync_clock_config(u32 async)
+{
+ sys_info_t sys_info;
+ u32 sync;
+ int div;
+ u32 reg;
+ u32 spcid_val[] = {
+ CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2,
+ CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 };
+
+ get_sys_info(&sys_info);
+ sync = sys_info.freqPCI;
+
+ /*
+ * First check if the equation above is met
+ */
+ if (!ppc4xx_pci_sync_clock_ok(sync, async)) {
+ /*
+ * Reconfigure PCI sync clock to meet the equation.
+ * Start with highest possible PCI sync frequency
+ * (divider 1).
+ */
+ for (div = 1; div <= 4; div++) {
+ sync = sys_info.freqPLB / div;
+ if (ppc4xx_pci_sync_clock_ok(sync, async))
+ break;
+ }
+
+ if (div <= 4) {
+ mtcpr(CPR0_SPCID, spcid_val[div]);
+
+ mfcpr(CPR0_ICFG, reg);
+ reg |= CPR0_ICFG_RLI_MASK;
+ mtcpr(CPR0_ICFG, reg);
+
+ /* do chip reset */
+ mtspr(SPRN_DBCR0, 0x20000000);
+ } else {
+ /* Impossible to configure the PCI sync clock */
+ return -1;
+ }
+ }
+
+ return 0;
+}
+#endif
diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index 496e028..15a184b 100644
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -42,7 +42,7 @@ void __ft_board_setup(void *blob, bd_t *bd)
u32 bxcr;
u32 ranges[EBC_NUM_BANKS * 4];
u32 *p = ranges;
- char *ebc_path = "/plb/opb/ebc";
+ char ebc_path[] = "/plb/opb/ebc";
ft_cpu_setup(blob, bd);
@@ -59,11 +59,17 @@ void __ft_board_setup(void *blob, bd_t *bd)
*p++ = 0;
*p++ = bxcr & EBC_BXCR_BAS_MASK;
*p++ = EBC_BXCR_BANK_SIZE(bxcr);
+
+#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+ /* Try to update reg property in nor flash node too */
+ fdt_fixup_nor_flash_size(blob, i,
+ EBC_BXCR_BANK_SIZE(bxcr));
+#endif
}
}
/* Some 405 PPC's have EBC as direct PLB child in the dts */
- if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
+ if (fdt_path_offset(blob, ebc_path) < 0)
strcpy(ebc_path, "/plb/ebc");
rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
(p - ranges) * sizeof(u32), 1);