Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xx

6 files changed, 498 insertions, 119 deletions

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 1b51078..e4bc405 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -56,49 +56,78 @@ int checkcpu(void)
 	switch(spridr) {
 	case SPR_8349E_REV10:
 	case SPR_8349E_REV11:
+	case SPR_8349E_REV31:
 		puts("MPC8349E, ");
 		break;
 	case SPR_8349_REV10:
 	case SPR_8349_REV11:
+	case SPR_8349_REV31:
 		puts("MPC8349, ");
 		break;
 	case SPR_8347E_REV10_TBGA:
 	case SPR_8347E_REV11_TBGA:
+	case SPR_8347E_REV31_TBGA:
 	case SPR_8347E_REV10_PBGA:
 	case SPR_8347E_REV11_PBGA:
+	case SPR_8347E_REV31_PBGA:
 		puts("MPC8347E, ");
 		break;
 	case SPR_8347_REV10_TBGA:
 	case SPR_8347_REV11_TBGA:
+	case SPR_8347_REV31_TBGA:
 	case SPR_8347_REV10_PBGA:
 	case SPR_8347_REV11_PBGA:
+	case SPR_8347_REV31_PBGA:
 		puts("MPC8347, ");
 		break;
 	case SPR_8343E_REV10:
 	case SPR_8343E_REV11:
+	case SPR_8343E_REV31:
 		puts("MPC8343E, ");
 		break;
 	case SPR_8343_REV10:
 	case SPR_8343_REV11:
+	case SPR_8343_REV31:
 		puts("MPC8343, ");
 		break;
 	case SPR_8360E_REV10:
 	case SPR_8360E_REV11:
 	case SPR_8360E_REV12:
+	case SPR_8360E_REV20:
 		puts("MPC8360E, ");
 		break;
 	case SPR_8360_REV10:
 	case SPR_8360_REV11:
 	case SPR_8360_REV12:
+	case SPR_8360_REV20:
 		puts("MPC8360, ");
 		break;
+	case SPR_8323E_REV10:
+	case SPR_8323E_REV11:
+		puts("MPC8323E, ");
+		break;
+	case SPR_8323_REV10:
+	case SPR_8323_REV11:
+		puts("MPC8323, ");
+		break;
+	case SPR_8321E_REV10:
+	case SPR_8321E_REV11:
+		puts("MPC8321E, ");
+		break;
+	case SPR_8321_REV10:
+	case SPR_8321_REV11:
+		puts("MPC8321, ");
+		break;
 	default:
-		puts("Rev: Unknown\n");
-		return -1;	/* Not sure what this is */
+		puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n");
+		return 0;
 	}
 
-#if defined(CONFIG_MPC8349)
-	printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock));
+#if defined(CONFIG_MPC834X)
+	/* Multiple revisons of 834x processors may have the same SPRIDR value.
+	 * So use PVR to identify the revision number.
+	 */
+	printf("Rev: %02x at %s MHz\n", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
 #else
 	printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
 #endif
@@ -250,7 +279,6 @@ unsigned long get_tbclk(void)
 #if defined(CONFIG_WATCHDOG)
 void watchdog_reset (void)
 {
-#ifdef CONFIG_MPC834X
 	int re_enable = disable_interrupts();
 
 	/* Reset the 83xx watchdog */
@@ -260,9 +288,6 @@ void watchdog_reset (void)
 
 	if (re_enable)
 		enable_interrupts ();
-#else
-	hang();
-#endif
 }
 #endif
 
@@ -292,14 +317,64 @@ ft_cpu_setup(void *blob, bd_t *bd)
 		*p = cpu_to_be32(clock);
 
 #ifdef CONFIG_MPC83XX_TSEC1
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
+
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
+	if (p != NULL)
 		memcpy(p, bd->bi_enetaddr, 6);
 #endif
 
 #ifdef CONFIG_MPC83XX_TSEC2
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet1addr, 6);
+
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
+	if (p != NULL)
 		memcpy(p, bd->bi_enet1addr, 6);
 #endif
+
+#ifdef CONFIG_UEC_ETH1
+#if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
+
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
+#elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
+
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
+#endif
+#endif
+
+#ifdef CONFIG_UEC_ETH2
+#if CFG_UEC2_UCC_NUM == 1  /* UCC2 */
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet1addr, 6);
+
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet1addr, 6);
+#elif CFG_UEC2_UCC_NUM == 3  /* UCC4 */
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet1addr, 6);
+
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet1addr, 6);
+#endif
+#endif
 }
 #endif
 
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index e5725fb..3ac9161 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -69,31 +69,53 @@ void cpu_init_f (volatile immap_t * im)
 
 #ifdef CFG_ACR_PIPE_DEP
 	/* Arbiter pipeline depth */
-	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT);
+	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
+			  (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
 #endif
 
 #ifdef CFG_SPCR_TSEC1EP
 	/* TSEC1 Emergency priority */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT);
+	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
 #endif
 
 #ifdef CFG_SPCR_TSEC2EP
 	/* TSEC2 Emergency priority */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT);
+	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
 #endif
 
+#ifdef CONFIG_MPC834X
 #ifdef CFG_SCCR_TSEC1CM
 	/* TSEC1 clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT);
+	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
 #endif
 #ifdef CFG_SCCR_TSEC2CM
 	/* TSEC2 & I2C1 clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT);
+	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
+#endif
+#ifdef CFG_SCCR_USBMPHCM
+	/* USB MPH clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
+#endif
+#endif /* CONFIG_MPC834X */
+
+#ifdef CFG_SCCR_PCICM
+	/* PCI & DMA clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
+#endif
+
+#ifdef CFG_SCCR_USBDRCM
+	/* USB DR clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
+#endif
+
+#ifdef CFG_SCCR_ENCCM
+	/* Encryption clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
 #endif
 
 #ifdef CFG_ACR_RPTCNT
 	/* Arbiter repeat count */
-	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT));
+	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
 #endif
 
 	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
@@ -119,6 +141,11 @@ void cpu_init_f (volatile immap_t * im)
 #ifdef CFG_SICRL
 	im->sysconf.sicrl = CFG_SICRL;
 #endif
+	/* DDR control driver register */
+#ifdef CFG_DDRCDR
+	im->sysconf.ddrcdr = CFG_DDRCDR;
+#endif
+
 #ifdef CONFIG_QE
 	/* Config QE ioports */
 	config_qe_ioports();
@@ -202,12 +229,12 @@ void cpu_init_f (volatile immap_t * im)
 	im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
 #endif
 #ifdef CFG_GPIO1_PRELIM
-	im->pgio[0].dir = CFG_GPIO1_DIR;
-	im->pgio[0].dat = CFG_GPIO1_DAT;
+	im->gpio[0].dir = CFG_GPIO1_DIR;
+	im->gpio[0].dat = CFG_GPIO1_DAT;
 #endif
 #ifdef CFG_GPIO2_PRELIM
-	im->pgio[1].dir = CFG_GPIO2_DIR;
-	im->pgio[1].dat = CFG_GPIO2_DAT;
+	im->gpio[1].dir = CFG_GPIO2_DIR;
+	im->gpio[1].dat = CFG_GPIO2_DAT;
 #endif
 }
 
diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c
index ebe3487..8b3937a 100644
--- a/cpu/mpc83xx/qe_io.c
+++ b/cpu/mpc83xx/qe_io.c
@@ -35,7 +35,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
 	u32			pin_1bit_mask;
 	u32			tmp_val;
 	volatile immap_t	*im = (volatile immap_t *)CFG_IMMR;
-	volatile gpio83xx_t	*par_io =(volatile gpio83xx_t *)&im->gpio;
+	volatile qepio83xx_t	*par_io = (volatile qepio83xx_t *)&im->qepio;
 
 	/* Caculate pin location and 2bit mask and dir */
 	pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 0d93f2e..d9b8753 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -106,16 +106,29 @@ long int spd_sdram()
 	volatile ddr83xx_t *ddr = &immap->ddr;
 	volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
 	spd_eeprom_t spd;
+	unsigned int n_ranks;
+	unsigned int odt_rd_cfg, odt_wr_cfg;
+	unsigned char twr_clk, twtr_clk;
+	unsigned char sdram_type;
 	unsigned int memsize;
 	unsigned int law_size;
 	unsigned char caslat, caslat_ctrl;
+	unsigned int trfc, trfc_clk, trfc_low, trfc_high;
+	unsigned int trcd_clk, trtp_clk;
+	unsigned char cke_min_clk;
+	unsigned char add_lat, wr_lat;
+	unsigned char wr_data_delay;
+	unsigned char four_act;
+	unsigned char cpo;
 	unsigned char burstlen;
+	unsigned char odt_cfg, mode_odt_enable;
 	unsigned int max_bus_clk;
 	unsigned int max_data_rate, effective_data_rate;
 	unsigned int ddrc_clk;
 	unsigned int refresh_clk;
-	unsigned sdram_cfg;
+	unsigned int sdram_cfg;
 	unsigned int ddrc_ecc_enable;
+	unsigned int pvr = get_pvr();
 
 	/* Read SPD parameters with I2C */
 	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
@@ -123,19 +136,25 @@ long int spd_sdram()
 	spd_debug(&spd);
 #endif
 	/* Check the memory type */
-	if (spd.mem_type != SPD_MEMTYPE_DDR) {
+	if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
 		printf("DDR: Module mem type is %02X\n", spd.mem_type);
 		return 0;
 	}
 
 	/* Check the number of physical bank */
-	if (spd.nrows > 2) {
-		printf("DDR: The number of physical bank is %02X\n", spd.nrows);
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		n_ranks = spd.nrows;
+	} else {
+		n_ranks = (spd.nrows & 0x7) + 1;
+	}
+
+	if (n_ranks > 2) {
+		printf("DDR: The number of physical bank is %02X\n", n_ranks);
 		return 0;
 	}
 
 	/* Check if the number of row of the module is in the range of DDRC */
-	if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
+	if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
 		printf("DDR: Row number is out of range of DDRC, row=%02X\n",
 							 spd.nrow_addr);
 		return 0;
@@ -147,20 +166,43 @@ long int spd_sdram()
 							 spd.ncol_addr);
 		return 0;
 	}
+
+#ifdef CFG_DDRCDR_VALUE
+	/*
+	 * Adjust DDR II IO voltage biasing.  It just makes it work.
+	 */
+	if(spd.mem_type == SPD_MEMTYPE_DDR2) {
+		immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+	}
+#endif
+
+	/*
+	 * ODT configuration recommendation from DDR Controller Chapter.
+	 */
+	odt_rd_cfg = 0;			/* Never assert ODT */
+	odt_wr_cfg = 0;			/* Never assert ODT */
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		odt_wr_cfg = 1;		/* Assert ODT on writes to CSn */
+	}
+
 	/* Setup DDR chip select register */
 #ifdef CFG_83XX_DDR_USES_CS0
 	ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
 	ddr->cs_config[0] = ( 1 << 31
+			    | (odt_rd_cfg << 20)
+			    | (odt_wr_cfg << 16)
 			    | (spd.nrow_addr - 12) << 8
 			    | (spd.ncol_addr - 8) );
 	debug("\n");
 	debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
 	debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
 
-	if (spd.nrows == 2) {
+	if (n_ranks == 2) {
 		ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
 				  | ((banksize(spd.row_dens) >> 23) - 1) );
 		ddr->cs_config[1] = ( 1<<31
+				    | (odt_rd_cfg << 20)
+				    | (odt_wr_cfg << 16)
 				    | (spd.nrow_addr-12) << 8
 				    | (spd.ncol_addr-8) );
 		debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
@@ -170,16 +212,20 @@ long int spd_sdram()
 #else
 	ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
 	ddr->cs_config[2] = ( 1 << 31
+			    | (odt_rd_cfg << 20)
+			    | (odt_wr_cfg << 16)
 			    | (spd.nrow_addr - 12) << 8
 			    | (spd.ncol_addr - 8) );
 	debug("\n");
 	debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
 	debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
 
-	if (spd.nrows == 2) {
+	if (n_ranks == 2) {
 		ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
 				  | ((banksize(spd.row_dens) >> 23) - 1) );
 		ddr->cs_config[3] = ( 1<<31
+				    | (odt_rd_cfg << 20)
+				    | (odt_wr_cfg << 16)
 				    | (spd.nrow_addr-12) << 8
 				    | (spd.ncol_addr-8) );
 		debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
@@ -187,15 +233,10 @@ long int spd_sdram()
 	}
 #endif
 
-	if (spd.mem_type != 0x07) {
-		puts("No DDR module found!\n");
-		return 0;
-	}
-
 	/*
 	 * Figure out memory size in Megabytes.
 	 */
-	memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
+	memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
 
 	/*
 	 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
@@ -215,24 +256,32 @@ long int spd_sdram()
 	 * in the spd.cas_lat field.  Translate it to a DDR
 	 * controller field value:
 	 *
-	 *	CAS Lat	 DDR I	   Ctrl
-	 *	Clocks	 SPD Bit   Value
-	 *	-------+--------+---------
-	 *	1.0	   0	    001
-	 *	1.5	   1	    010
-	 *	2.0	   2	    011
-	 *	2.5	   3	    100
-	 *	3.0	   4	    101
-	 *	3.5	   5	    110
-	 *	4.0	   6	    111
+	 *	CAS Lat	DDR I	DDR II	Ctrl
+	 *	Clocks	SPD Bit	SPD Bit	Value
+	 *	-------	-------	-------	-----
+	 *	1.0	0		0001
+	 *	1.5	1		0010
+	 *	2.0	2	2	0011
+	 *	2.5	3		0100
+	 *	3.0	4	3	0101
+	 *	3.5	5		0110
+	 *	4.0	6	4	0111
+	 *	4.5			1000
+	 *	5.0		5	1001
 	 */
 	caslat = __ilog2(spd.cas_lat);
-
-	if (caslat > 6 ) {
-		printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n",
-			spd.cas_lat);
+	if ((spd.mem_type == SPD_MEMTYPE_DDR)
+	    && (caslat > 6)) {
+		printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
+		return 0;
+	} else if (spd.mem_type == SPD_MEMTYPE_DDR2
+		   && (caslat < 2 || caslat > 5)) {
+		printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
+		       spd.cas_lat);
 		return 0;
 	}
+	debug("DDR: caslat SPD bit is %d\n", caslat);
+
 	max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
 			+ (spd.clk_cycle & 0x0f));
 	max_data_rate = max_bus_clk * 2;
@@ -240,10 +289,11 @@ long int spd_sdram()
 	debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
 
 	ddrc_clk = gd->ddr_clk / 1000000;
+	effective_data_rate = 0;
 
-	if (max_data_rate >= 390) { /* it is DDR 400 */
-		if (ddrc_clk <= 410 && ddrc_clk > 350) {
-			/* DDR controller clk at 350~410 */
+	if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
+		if (ddrc_clk <= 460 && ddrc_clk > 350) {
+			/* DDR controller clk at 350~460 */
 			effective_data_rate = 400; /* 5ns */
 			caslat = caslat;
 		} else if (ddrc_clk <= 350 && ddrc_clk > 280) {
@@ -258,16 +308,16 @@ long int spd_sdram()
 			effective_data_rate = 266; /* 7.5ns */
 			if (spd.clk_cycle3 == 0x75)
 				caslat = caslat - 2;
-			else if (spd.clk_cycle2 == 0x60)
+			else if (spd.clk_cycle2 == 0x75)
 				caslat = caslat - 1;
 			else
 				caslat = caslat;
 		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
 			/* DDR controller clk at 90~230 */
 			effective_data_rate = 200; /* 10ns */
-			if (spd.clk_cycle3 == 0x75)
+			if (spd.clk_cycle3 == 0xa0)
 				caslat = caslat - 2;
-			else if (spd.clk_cycle2 == 0x60)
+			else if (spd.clk_cycle2 == 0xa0)
 				caslat = caslat - 1;
 			else
 				caslat = caslat;
@@ -289,7 +339,7 @@ long int spd_sdram()
 			effective_data_rate = 200; /* 10ns */
 			if (spd.clk_cycle3 == 0xa0)
 				caslat = caslat - 2;
-			else if (spd.clk_cycle2 == 0x75)
+			else if (spd.clk_cycle2 == 0xa0)
 				caslat = caslat - 1;
 			else
 				caslat = caslat;
@@ -330,41 +380,197 @@ long int spd_sdram()
 	 * Errata DDR6 work around: input enable 2 cycles earlier.
 	 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
 	 */
-	if (caslat == 2)
-		ddr->debug_reg = 0x201c0000; /* CL=2 */
-	else if (caslat == 3)
-		ddr->debug_reg = 0x202c0000; /* CL=2.5 */
-	else if (caslat == 4)
-		ddr->debug_reg = 0x202c0000; /* CL=3.0 */
+	if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
+		if (caslat == 2)
+			ddr->debug_reg = 0x201c0000; /* CL=2 */
+		else if (caslat == 3)
+			ddr->debug_reg = 0x202c0000; /* CL=2.5 */
+		else if (caslat == 4)
+			ddr->debug_reg = 0x202c0000; /* CL=3.0 */
 
-	__asm__ __volatile__ ("sync");
+		__asm__ __volatile__ ("sync");
 
-	debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
+		debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
+	}
 
 	/*
-	 * note: caslat must also be programmed into ddr->sdram_mode
-	 * register.
-	 *
-	 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
-	 * use conservative value here.
+	 * Convert caslat clocks to DDR controller value.
+	 * Force caslat_ctrl to be DDR Controller field-sized.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		caslat_ctrl = (caslat + 1) & 0x07;
+	} else {
+		caslat_ctrl =  (2 * caslat - 1) & 0x0f;
+	}
+
+	debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
+	debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
+	      caslat, caslat_ctrl);
+
+	/*
+	 * Timing Config 0.
+	 * Avoid writing for DDR I.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		unsigned char taxpd_clk = 8;		/* By the book. */
+		unsigned char tmrd_clk = 2;		/* By the book. */
+		unsigned char act_pd_exit = 2;		/* Empirical? */
+		unsigned char pre_pd_exit = 6;		/* Empirical? */
+
+		ddr->timing_cfg_0 = (0
+			| ((act_pd_exit & 0x7) << 20)	/* ACT_PD_EXIT */
+			| ((pre_pd_exit & 0x7) << 16)	/* PRE_PD_EXIT */
+			| ((taxpd_clk & 0xf) << 8)	/* ODT_PD_EXIT */
+			| ((tmrd_clk & 0xf) << 0)	/* MRS_CYC */
+			);
+		debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
+	}
+
+	/*
+	 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
+	 * use conservative value.
+	 * For DDR II, they are bytes 36 and 37, in quarter nanos.
 	 */
-	caslat_ctrl = (caslat + 1) & 0x07; /* see as above */
+
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		twr_clk = 3;	/* Clocks */
+		twtr_clk = 1;	/* Clocks */
+	} else {
+		twr_clk = picos_to_clk(spd.twr * 250);
+		twtr_clk = picos_to_clk(spd.twtr * 250);
+	}
+
+	/*
+	 * Calculate Trfc, in picos.
+	 * DDR I:  Byte 42 straight up in ns.
+	 * DDR II: Byte 40 and 42 swizzled some, in ns.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		trfc = spd.trfc * 1000;		/* up to ps */
+	} else {
+		unsigned int byte40_table_ps[8] = {
+			0,
+			250,
+			330,
+			500,
+			660,
+			750,
+			0,
+			0
+		};
+
+		trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
+			+ byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
+	}
+	trfc_clk = picos_to_clk(trfc);
+
+	/*
+	 * Trcd, Byte 29, from quarter nanos to ps and clocks.
+	 */
+	trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
+
+	/*
+	 * Convert trfc_clk to DDR controller fields.  DDR I should
+	 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
+	 * 83xx controller has an extended REFREC field of three bits.
+	 * The controller automatically adds 8 clocks to this value,
+	 * so preadjust it down 8 first before splitting it up.
+	 */
+	trfc_low = (trfc_clk - 8) & 0xf;
+	trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
 
 	ddr->timing_cfg_1 =
-	    (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
-	     ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
-	     ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
-	     ((caslat_ctrl & 0x07) << 16 ) |
-	     (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) |
-	     ( 0x300 ) |
-	     ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
+	    (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |	/* PRETOACT */
+	     ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
+	     (trcd_clk << 20 ) |  				/* ACTTORW */
+	     (caslat_ctrl << 16 ) |				/* CASLAT */
+	     (trfc_low << 12 ) |				/* REFEC */
+	     ((twr_clk & 0x07) << 8) |				/* WRRREC */
+	     ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) |	/* ACTTOACT */
+	     ((twtr_clk & 0x07) << 0)				/* WRTORD */
+	    );
+
+	/*
+	 * Additive Latency
+	 * For DDR I, 0.
+	 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
+	 * which comes from Trcd, and also note that:
+	 *	add_lat + caslat must be >= 4
+	 */
+	add_lat = 0;
+	if (spd.mem_type == SPD_MEMTYPE_DDR2
+	    && (odt_wr_cfg || odt_rd_cfg)
+	    && (caslat < 4)) {
+		add_lat = trcd_clk - 1;
+		if ((add_lat + caslat) < 4) {
+			add_lat = 0;
+		}
+	}
 
-	ddr->timing_cfg_2 = 0x00000800;
+	/*
+	 * Write Data Delay
+	 * Historically 0x2 == 4/8 clock delay.
+	 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
+	 */
+	wr_data_delay = 2;
+
+	/*
+	 * Write Latency
+	 * Read to Precharge
+	 * Minimum CKE Pulse Width.
+	 * Four Activate Window
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		/*
+		 * This is a lie.  It should really be 1, but if it is
+		 * set to 1, bits overlap into the old controller's
+		 * otherwise unused ACSM field.  If we leave it 0, then
+		 * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
+		 */
+		wr_lat = 0;
+
+		trtp_clk = 2;		/* By the book. */
+		cke_min_clk = 1;	/* By the book. */
+		four_act = 1;		/* By the book. */
+
+	} else {
+		wr_lat = caslat - 1;
+
+		/* Convert SPD value from quarter nanos to picos. */
+		trtp_clk = picos_to_clk(spd.trtp * 250);
+
+		cke_min_clk = 3;	/* By the book. */
+		four_act = picos_to_clk(37500);	/* By the book. 1k pages? */
+	}
+
+	/*
+	 * Empirically set ~MCAS-to-preamble override for DDR 2.
+	 * Your milage will vary.
+	 */
+	cpo = 0;
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		if (effective_data_rate == 266 || effective_data_rate == 333) {
+			cpo = 0x7;		/* READ_LAT + 5/4 */
+		} else if (effective_data_rate == 400) {
+			cpo = 0x9;		/* READ_LAT + 7/4 */
+		} else {
+			/* Automatic calibration */
+			cpo = 0x1f;
+		}
+	}
+
+	ddr->timing_cfg_2 = (0
+		| ((add_lat & 0x7) << 28)		/* ADD_LAT */
+		| ((cpo & 0x1f) << 23)			/* CPO */
+		| ((wr_lat & 0x7) << 19)		/* WR_LAT */
+		| ((trtp_clk & 0x7) << 13)		/* RD_TO_PRE */
+		| ((wr_data_delay & 0x7) << 10)		/* WR_DATA_DELAY */
+		| ((cke_min_clk & 0x7) << 6)		/* CKE_PLS */
+		| ((four_act & 0x1f) << 0)		/* FOUR_ACT */
+		);
 
 	debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
 	debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
-	/* Setup init value, but not enable */
-	ddr->sdram_cfg = 0x42000000;
 
 	/* Check DIMM data bus width */
 	if (spd.dataw_lsb == 0x20) {
@@ -384,7 +590,8 @@ long int spd_sdram()
 	/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
 	   Burst type is sequential
 	 */
-	switch (caslat) {
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		switch (caslat) {
 		case 1:
 			ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
 			break;
@@ -400,9 +607,36 @@ long int spd_sdram()
 		default:
 			printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
 			return 0;
+		}
+	} else {
+		mode_odt_enable = 0x0;                  /* Default disabled */
+		if (odt_wr_cfg || odt_rd_cfg) {
+			/*
+			 * Bits 6 and 2 in Extended MRS(1)
+			 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
+			 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
+			 */
+			mode_odt_enable = 0x40;         /* 150 Ohm */
+		}
+
+		ddr->sdram_mode =
+			(0
+			 | (1 << (16 + 10))             /* DQS Differential disable */
+			 | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
+			 | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
+			 | ((twr_clk >> 1) << 9)        /* Write Recovery Autopre */
+			 | (caslat << 4)                /* caslat */
+			 | (burstlen << 0)              /* Burst length */
+			);
 	}
 	debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
 
+	/*
+	 * Clear EMRS2 and EMRS3.
+	 */
+	ddr->sdram_mode2 = 0;
+	debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
+
 	switch (spd.refresh) {
 		case 0x00:
 		case 0x80:
@@ -440,10 +674,31 @@ long int spd_sdram()
 	ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
 	debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
 
+	/*
+	 * SDRAM Cfg 2
+	 */
+	odt_cfg = 0;
+	if (odt_rd_cfg | odt_wr_cfg) {
+		odt_cfg = 0x2;		/* ODT to IOs during reads */
+	}
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		ddr->sdram_cfg2 = (0
+			    | (0 << 26)	/* True DQS */
+			    | (odt_cfg << 21)	/* ODT only read */
+			    | (1 << 12)	/* 1 refresh at a time */
+			    );
+
+		debug("DDR: sdram_cfg2  = 0x%08x\n", ddr->sdram_cfg2);
+	}
+
+#ifdef CFG_DDR_SDRAM_CLK_CNTL	/* Optional platform specific value */
+	ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+#else
 	/* SS_EN = 0, source synchronous disable
 	 * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
 	 */
 	ddr->sdram_clk_cntl = 0x00000000;
+#endif
 	debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
 
 	asm("sync;isync");
@@ -458,11 +713,22 @@ long int spd_sdram()
 	 *
 	 * sdram_cfg[0]   = 1 (ddr sdram logic enable)
 	 * sdram_cfg[1]   = 1 (self-refresh-enable)
-	 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
+	 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
+	 *			010 DDR 1 SDRAM
+	 *			011 DDR 2 SDRAM
 	 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
 	 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
 	 */
-	sdram_cfg = 0xC2000000;
+	if (spd.mem_type == SPD_MEMTYPE_DDR)
+		sdram_type = 2;
+	else
+		sdram_type = 3;
+
+	sdram_cfg = (0
+		     | (1 << 31)			/* DDR enable */
+		     | (1 << 30)			/* Self refresh */
+		     | (sdram_type << 24)		/* SDRAM type */
+		     );
 
 	/* sdram_cfg[3] = RD_EN - registered DIMM enable */
 	if (spd.mod_attr & 0x02)
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 7e53b1e..c759930 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -99,7 +99,7 @@ int get_clocks(void)
 	u32 lcrr;
 
 	u32 csb_clk;
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbmph_clk;
@@ -107,15 +107,19 @@ int get_clocks(void)
 #endif
 	u32 core_clk;
 	u32 i2c1_clk;
+#if !defined(CONFIG_MPC832X)
 	u32 i2c2_clk;
+#endif
 	u32 enc_clk;
 	u32 lbiu_clk;
 	u32 lclk_clk;
 	u32 ddr_clk;
-#if defined (CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360)
+	u32 ddr_sec_clk;
+#endif
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 	u32 qepmf;
 	u32 qepdf;
-	u32 ddr_sec_clk;
 	u32 qe_clk;
 	u32 brg_clk;
 #endif
@@ -139,12 +143,12 @@ int get_clocks(void)
 #endif
 	}
 
-	spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
+	spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
 	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
 
 	sccr = im->clk.sccr;
 
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
 	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 	case 0:
 		tsec1_clk = 0;
@@ -227,10 +231,12 @@ int get_clocks(void)
 		return -9;
 	}
 #endif
-#if defined (CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 	i2c1_clk = csb_clk;
 #endif
+#if !defined(CONFIG_MPC832X)
 	i2c2_clk = csb_clk;	/* i2c-2 clk is equal to csb clk */
+#endif
 
 	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
 	case 0:
@@ -249,12 +255,9 @@ int get_clocks(void)
 		/* unkown SCCR_ENCCM value */
 		return -6;
 	}
-#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
+
 	lbiu_clk = csb_clk *
-	           (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
-#else
-#error Unknown MPC83xx chip
-#endif
+	           (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
 	lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
 	switch (lcrr) {
 	case 2:
@@ -266,16 +269,13 @@ int get_clocks(void)
 		/* unknown lcrr */
 		return -10;
 	}
-#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
+
 	ddr_clk = csb_clk *
-		  (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
-	corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
-#if defined (CONFIG_MPC8360)
+		  (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
+	corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
+#if defined(CONFIG_MPC8360)
 	ddr_sec_clk = csb_clk * (1 +
-		       ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
-#endif
-#else
-#error Unknown MPC83xx chip
+		       ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
 #endif
 
 	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
@@ -306,15 +306,15 @@ int get_clocks(void)
 		return -12;
 	}
 
-#if defined (CONFIG_MPC8360)
-	qepmf = (im->reset.rcwl & RCWL_CEPMF) >> RCWL_CEPMF_SHIFT;
-	qepdf = (im->reset.rcwl & RCWL_CEPDF) >> RCWL_CEPDF_SHIFT;
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+	qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
+	qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
 	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
 	brg_clk = qe_clk / 2;
 #endif
 
 	gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
 	gd->tsec1_clk = tsec1_clk;
 	gd->tsec2_clk = tsec2_clk;
 	gd->usbmph_clk = usbmph_clk;
@@ -322,13 +322,17 @@ int get_clocks(void)
 #endif
 	gd->core_clk = core_clk;
 	gd->i2c1_clk = i2c1_clk;
+#if !defined(CONFIG_MPC832X)
 	gd->i2c2_clk = i2c2_clk;
+#endif
 	gd->enc_clk = enc_clk;
 	gd->lbiu_clk = lbiu_clk;
 	gd->lclk_clk = lclk_clk;
 	gd->ddr_clk = ddr_clk;
-#if defined (CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360)
 	gd->ddr_sec_clk = ddr_sec_clk;
+#endif
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 	gd->qe_clk = qe_clk;
 	gd->brg_clk = brg_clk;
 #endif
@@ -352,19 +356,22 @@ int print_clock_conf(void)
 	printf("Clock configuration:\n");
 	printf("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
 	printf("  Core:                %4d MHz\n", gd->core_clk / 1000000);
-#if defined (CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 	printf("  QE:                  %4d MHz\n", gd->qe_clk / 1000000);
+	printf("  BRG:                 %4d MHz\n", gd->brg_clk / 1000000);
 #endif
 	printf("  Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
 	printf("  Local Bus:           %4d MHz\n", gd->lclk_clk / 1000000);
 	printf("  DDR:                 %4d MHz\n", gd->ddr_clk / 1000000);
-#if defined (CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360)
 	printf("  DDR Secondary:       %4d MHz\n", gd->ddr_sec_clk / 1000000);
 #endif
 	printf("  SEC:                 %4d MHz\n", gd->enc_clk / 1000000);
 	printf("  I2C1:                %4d MHz\n", gd->i2c1_clk / 1000000);
+#if !defined(CONFIG_MPC832X)
 	printf("  I2C2:                %4d MHz\n", gd->i2c2_clk / 1000000);
-#if defined(CONFIG_MPC8349)
+#endif
+#if defined(CONFIG_MPC834X)
 	printf("  TSEC1:               %4d MHz\n", gd->tsec1_clk / 1000000);
 	printf("  TSEC2:               %4d MHz\n", gd->tsec2_clk / 1000000);
 	printf("  USB MPH:             %4d MHz\n", gd->usbmph_clk / 1000000);
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index 0f27bb6..6ee9ec9 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -77,19 +77,11 @@
 	END_GOT
 
 /*
- * Version string - must be in data segment because MPC83xx uses the
- * first 256 bytes for the Hard Reset Configuration Word table (see
- * below).  Similarly, can't have the U-Boot Magic Number as the first
- * thing in the image - don't know how this will affect the image tools,
- * but I guess I'll find out soon.
+ * The Hard Reset Configuration Word (HRCW) table is in the first 64
+ * (0x40) bytes of flash.  It has 8 bytes, but each byte is repeated 8
+ * times so the processor can fetch it out of flash whether the flash
+ * is 8, 16, 32, or 64 bits wide (hardware trickery).
  */
-	.data
-	.globl	version_string
-version_string:
-	.ascii U_BOOT_VERSION
-	.ascii " (", __DATE__, " - ", __TIME__, ")"
-	.ascii " ", CONFIG_IDENT_STRING, "\0"
-
 	.text
 #define _HRCW_TABLE_ENTRY(w)		\
 	.fill	8,1,(((w)>>24)&0xff);	\
@@ -100,6 +92,18 @@ version_string:
 	_HRCW_TABLE_ENTRY(CFG_HRCW_LOW)
 	_HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
 
+/*
+ * Magic number and version string - put it after the HRCW since it
+ * cannot be first in flash like it is in many other processors.
+ */
+	.long	0x27051956		/* U-Boot Magic Number */
+
+	.globl	version_string
+version_string:
+	.ascii U_BOOT_VERSION
+	.ascii " (", __DATE__, " - ", __TIME__, ")"
+	.ascii " ", CONFIG_IDENT_STRING, "\0"
+
 
 #ifndef CONFIG_DEFAULT_IMMR
 #error CONFIG_DEFAULT_IMMR must be defined