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authorAndy Fleming <afleming@freescale.com>2007-02-23 16:28:46 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2007-04-23 19:58:28 -0500
commit1f9a318cea14272edd10d63739e2d326c90f430e (patch)
tree7fe03e2eb50c56283ef27940308b3e7a170c76aa /cpu
parent9343dbf85bc03033f2102d8e8543567c2c1ad2d2 (diff)
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Only set ddrioovcr for 8548 rev1.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc85xx/spd_sdram.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 4b3c4eb..16a697d 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -263,13 +263,14 @@ spd_sdram(void)
}
/*
- * Adjust DDR II IO voltage biasing. It just makes it work.
+ * Adjust DDR II IO voltage biasing.
+ * Only 8548 rev 1 needs the fix
*/
- if (spd.mem_type == SPD_MEMTYPE_DDR2) {
- gur->ddrioovcr = (0
- | 0x80000000 /* Enable */
- | 0x10000000 /* VSEL to 1.8V */
- );
+ if ((SVR_VER(get_svr()) == SVR_8548_E) &&
+ (SVR_MJREV(get_svr()) == 1) &&
+ (spd.mem_type == SPD_MEMTYPE_DDR2)) {
+ gur->ddrioovcr = (0x80000000 /* Enable */
+ | 0x10000000);/* VSEL to 1.8V */
}
/*