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authorMike Frysinger <vapier@gentoo.org>2008-06-01 01:28:24 -0400
committerMike Frysinger <vapier@gentoo.org>2009-03-23 15:14:54 -0400
commit0d4f24b70f7a979f58174f3eb271874950b551b6 (patch)
tree874db5bcaa01fa9df526dae9796d692e79885912 /cpu
parent3986e981f565c08f10c7e526af8cb518d741c349 (diff)
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Blackfin: setup a sane default EBIU_SDBCTL for SDRAM controllers
If the board config does not specify an explicit EBIU_SDBCTL value, set it up with sane values based on other configuration options. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/blackfin/initcode.c33
1 files changed, 33 insertions, 0 deletions
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
index 1b58f99..1352fd6 100644
--- a/cpu/blackfin/initcode.c
+++ b/cpu/blackfin/initcode.c
@@ -203,6 +203,39 @@ static inline void serial_putc(char c)
# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
#endif
+#ifndef EBIU_RSTCTL
+/* Blackfin with SDRAM */
+#ifndef CONFIG_EBIU_SDBCTL_VAL
+# if CONFIG_MEM_SIZE == 16
+# define CONFIG_EBSZ_VAL EBSZ_16
+# elif CONFIG_MEM_SIZE == 32
+# define CONFIG_EBSZ_VAL EBSZ_32
+# elif CONFIG_MEM_SIZE == 64
+# define CONFIG_EBSZ_VAL EBSZ_64
+# elif CONFIG_MEM_SIZE == 128
+# define CONFIG_EBSZ_VAL EBSZ_128
+# elif CONFIG_MEM_SIZE == 256
+# define CONFIG_EBSZ_VAL EBSZ_256
+# elif CONFIG_MEM_SIZE == 512
+# define CONFIG_EBSZ_VAL EBSZ_512
+# else
+# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
+# endif
+# if CONFIG_MEM_ADD_WDTH == 8
+# define CONFIG_EBCAW_VAL EBCAW_8
+# elif CONFIG_MEM_ADD_WDTH == 9
+# define CONFIG_EBCAW_VAL EBCAW_9
+# elif CONFIG_MEM_ADD_WDTH == 10
+# define CONFIG_EBCAW_VAL EBCAW_10
+# elif CONFIG_MEM_ADD_WDTH == 11
+# define CONFIG_EBCAW_VAL EBCAW_11
+# else
+# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
+# endif
+# define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
+#endif
+#endif
+
BOOTROM_CALLED_FUNC_ATTR
void initcode(ADI_BOOT_DATA *bootstruct)
{