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authorBecky Bruce <becky.bruce@freescale.com>2008-11-05 14:55:34 -0600
committerJon Loeliger <jdl@freescale.com>2008-11-10 10:10:03 -0600
commitc1e1cf69547b138173f87a7f81c42a5d8dbfde3d (patch)
treea2d57f65e352a08aa94181785b3541926f4b3aff /cpu
parent6bf98b1362f0cb237620355ed3e6762fff82388d (diff)
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mpc86xx: Use SRR0/1/rfi to enable address translation, not blr
Using a mtmsr/blr means that you have to be executing at the same virtual address once you enable translation. This is unnecessarily restrictive, and is not really how this is usually done. Change it to use the more common mtspr SRR0/SRR1 and rfi method. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc86xx/start.S19
1 files changed, 8 insertions, 11 deletions
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 0d30e91..7e36801 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -244,9 +244,15 @@ in_flash:
*/
/* enable address translation */
- bl enable_addr_trans
- sync
+ mfmsr r5
+ ori r5, r5, (MSR_IR | MSR_DR)
+ lis r3,addr_trans_enabled@h
+ ori r3, r3, addr_trans_enabled@l
+ mtspr SPRN_SRR0,r3
+ mtspr SPRN_SRR1,r5
+ rfi
+addr_trans_enabled:
/* enable and invalidate the data cache */
/* bl l1dcache_enable */
bl dcache_enable
@@ -423,15 +429,6 @@ tlblp:
blt tlblp
blr
- .globl enable_addr_trans
-enable_addr_trans:
- /* enable address translation */
- mfmsr r5
- ori r5, r5, (MSR_IR | MSR_DR)
- mtmsr r5
- isync
- blr
-
.globl disable_addr_trans
disable_addr_trans:
/* disable address translation */