summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2008-09-22 14:11:10 -0500
committerWolfgang Denk <wd@denx.de>2008-10-18 21:54:04 +0200
commit54e091d3b603a3332c619199ca83a07e95960da4 (patch)
treed0bfa1b0ba3703150b2a368abb861dafa9cd0bb8 /cpu
parent6250f0f6297c5ba9aecdea6290799a95c5d4b1da (diff)
downloadu-boot-imx-54e091d3b603a3332c619199ca83a07e95960da4.zip
u-boot-imx-54e091d3b603a3332c619199ca83a07e95960da4.tar.gz
u-boot-imx-54e091d3b603a3332c619199ca83a07e95960da4.tar.bz2
85xx: Export invalidate_{i,d}cache and add flush_dcache
Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc85xx/start.S49
1 files changed, 49 insertions, 0 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 25d0390..fc3c336 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -565,6 +565,7 @@ mck_return:
/* Cache functions.
*/
+.globl invalidate_icache
invalidate_icache:
mfspr r0,L1CSR1
ori r0,r0,L1CSR1_ICFI
@@ -574,6 +575,7 @@ invalidate_icache:
isync
blr /* entire I cache */
+.globl invalidate_dcache
invalidate_dcache:
mfspr r0,L1CSR0
ori r0,r0,L1CSR0_DCFI
@@ -1019,3 +1021,50 @@ unlock_ram_in_cache:
tlbivax 0,r3
isync
blr
+
+.globl flush_dcache
+flush_dcache:
+ mfspr r3,SPRN_L1CFG0
+
+ rlwinm r5,r3,9,3 /* Extract cache block size */
+ twlgti r5,1 /* Only 32 and 64 byte cache blocks
+ * are currently defined.
+ */
+ li r4,32
+ subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
+ * log2(number of ways)
+ */
+ slw r5,r4,r5 /* r5 = cache block size */
+
+ rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
+ mulli r7,r7,13 /* An 8-way cache will require 13
+ * loads per set.
+ */
+ slw r7,r7,r6
+
+ /* save off HID0 and set DCFA */
+ mfspr r8,SPRN_HID0
+ ori r9,r8,HID0_DCFA@l
+ mtspr SPRN_HID0,r9
+ isync
+
+ lis r4,0
+ mtctr r7
+
+1: lwz r3,0(r4) /* Load... */
+ add r4,r4,r5
+ bdnz 1b
+
+ msync
+ lis r4,0
+ mtctr r7
+
+1: dcbf 0,r4 /* ...and flush. */
+ add r4,r4,r5
+ bdnz 1b
+
+ /* restore HID0 */
+ mtspr SPRN_HID0,r8
+ isync
+
+ blr