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authorKumar Gala <galak@kernel.crashing.org>2009-03-19 02:46:19 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-09-24 12:05:29 -0500
commit39aaca1f66a0e5b1204b0789f6c0097938c00ad1 (patch)
tree1b3549f4d791647ef26f87aa98ad3c2e1bfedcb4 /cpu
parent3c2a67eec8a0facc865b400caca52e7f6b7adf01 (diff)
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ppc/p4080: Determine various chip frequencies on CoreNet platforms
The means to determine the core, bus, and DDR frequencies are completely new on CoreNet style platforms. Additionally on p4080 we can have different frequencies for FMAN and PME IP blocks. We need to keep track of the FMAN & PME frequencies since they are used for time stamping capabilities inside each block. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc85xx/cpu.c45
-rw-r--r--cpu/mpc85xx/speed.c86
2 files changed, 127 insertions, 4 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 25c0416..0cc6e03 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -46,11 +46,20 @@ int checkcpu (void)
char buf1[32], buf2[32];
#ifdef CONFIG_DDR_CLK_FREQ
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_FSL_CORENET
+ u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
+ >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
+#else
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+#endif
+#else
+#ifdef CONFIG_FSL_CORENET
+ u32 ddr_sync = 0;
#else
u32 ddr_ratio = 0;
#endif
+#endif /* CONFIG_DDR_CLK_FREQ */
int i;
svr = get_svr();
@@ -111,6 +120,19 @@ int checkcpu (void)
}
printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
+#ifdef CONFIG_FSL_CORENET
+ if (ddr_sync == 1) {
+ printf(" DDR:%-4s MHz (%s MT/s data rate) "
+ "(Synchronous), ",
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
+ } else {
+ printf(" DDR:%-4s MHz (%s MT/s data rate) "
+ "(Asynchronous), ",
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
+ }
+#else
switch (ddr_ratio) {
case 0x0:
printf(" DDR:%-4s MHz (%s MT/s data rate), ",
@@ -118,22 +140,26 @@ int checkcpu (void)
strmhz(buf2, sysinfo.freqDDRBus));
break;
case 0x7:
- printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
+ printf(" DDR:%-4s MHz (%s MT/s data rate) "
+ "(Synchronous), ",
strmhz(buf1, sysinfo.freqDDRBus/2),
strmhz(buf2, sysinfo.freqDDRBus));
break;
default:
- printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
+ printf(" DDR:%-4s MHz (%s MT/s data rate) "
+ "(Asynchronous), ",
strmhz(buf1, sysinfo.freqDDRBus/2),
strmhz(buf2, sysinfo.freqDDRBus));
break;
}
+#endif
- if (sysinfo.freqLocalBus > LCRR_CLKDIV)
+ if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
- else
+ } else {
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
sysinfo.freqLocalBus);
+ }
#ifdef CONFIG_CPM2
printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
@@ -143,6 +169,17 @@ int checkcpu (void)
printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
#endif
+#ifdef CONFIG_SYS_DPAA_FMAN
+ for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
+ printf(" FMAN%d: %s MHz\n", i,
+ strmhz(buf1, sysinfo.freqFMan[i]));
+ }
+#endif
+
+#ifdef CONFIG_SYS_DPAA_PME
+ printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
+#endif
+
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
return 0;
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 2fdcefb..0244b5c 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -1,5 +1,6 @@
/*
* Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ *
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
@@ -37,6 +38,90 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info (sys_info_t * sysInfo)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_FSL_CORENET
+ volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+
+ const u8 core_cplx_PLL[16] = {
+ [ 0] = 0, /* CC1 PPL / 1 */
+ [ 1] = 0, /* CC1 PPL / 2 */
+ [ 2] = 0, /* CC1 PPL / 4 */
+ [ 4] = 1, /* CC2 PPL / 1 */
+ [ 5] = 1, /* CC2 PPL / 2 */
+ [ 6] = 1, /* CC2 PPL / 4 */
+ [ 8] = 2, /* CC3 PPL / 1 */
+ [ 9] = 2, /* CC3 PPL / 2 */
+ [10] = 2, /* CC3 PPL / 4 */
+ [12] = 3, /* CC4 PPL / 1 */
+ [13] = 3, /* CC4 PPL / 2 */
+ [14] = 3, /* CC4 PPL / 4 */
+ };
+
+ const u8 core_cplx_PLL_div[16] = {
+ [ 0] = 1, /* CC1 PPL / 1 */
+ [ 1] = 2, /* CC1 PPL / 2 */
+ [ 2] = 4, /* CC1 PPL / 4 */
+ [ 4] = 1, /* CC2 PPL / 1 */
+ [ 5] = 2, /* CC2 PPL / 2 */
+ [ 6] = 4, /* CC2 PPL / 4 */
+ [ 8] = 1, /* CC3 PPL / 1 */
+ [ 9] = 2, /* CC3 PPL / 2 */
+ [10] = 4, /* CC3 PPL / 4 */
+ [12] = 1, /* CC4 PPL / 1 */
+ [13] = 2, /* CC4 PPL / 2 */
+ [14] = 4, /* CC4 PPL / 4 */
+ };
+ uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
+ unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+ sysInfo->freqSystemBus = sysclk;
+ sysInfo->freqDDRBus = sysclk;
+ freqCC_PLL[0] = sysclk;
+ freqCC_PLL[1] = sysclk;
+ freqCC_PLL[2] = sysclk;
+ freqCC_PLL[3] = sysclk;
+
+ sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf;
+ sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf);
+ freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
+ freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
+ freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
+ freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+
+ rcw_tmp = in_be32(&gur->rcwsr[3]);
+ for (i = 0; i < cpu_numcores(); i++) {
+ u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
+ u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+
+ sysInfo->freqProcessor[i] =
+ freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
+ }
+
+#define PME_CLK_SEL 0x80000000
+#define FM1_CLK_SEL 0x40000000
+#define FM2_CLK_SEL 0x20000000
+ rcw_tmp = in_be32(&gur->rcwsr[7]);
+
+#ifdef CONFIG_SYS_DPAA_PME
+ if (rcw_tmp & PME_CLK_SEL)
+ sysInfo->freqPME = freqCC_PLL[2] / 2;
+ else
+ sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ if (rcw_tmp & FM1_CLK_SEL)
+ sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
+ else
+ sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+#if (CONFIG_SYS_NUM_FMAN) == 2
+ if (rcw_tmp & FM2_CLK_SEL)
+ sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
+ else
+ sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+#endif
+#endif
+
+#else
uint plat_ratio,e500_ratio,half_freqSystemBus;
uint lcrr_div;
int i;
@@ -67,6 +152,7 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
}
#endif
+#endif
#ifdef CONFIG_QE
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)