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authorTsiChung <tcliew@Goku.(none)>2007-07-10 15:45:43 -0500
committerJohn Rigby <jrigby@freescale.com>2007-07-10 14:29:10 -0600
commit0dca874db62718e41253659e60f3a1de7eb418ce (patch)
tree358165147025f019ff3b71149749b46dd44fd717 /cpu
parent52b017604a8f4d4a795880ef6e7861d7f2f1b005 (diff)
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Cache update and added CFG_UNIFY_CACHE
Enabled cache in cpu_init_f() for faster flash to mem allocation. Updated cache handling in start.S. Applied cache invalidate in fec_send() and fec_recv(). Added CFG_UNIFY_CACHE for CF V3 only. Signed-off-by: TsiChung <tcliew@Goku.(none)>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mcf532x/cpu_init.c3
-rw-r--r--cpu/mcf532x/start.S12
2 files changed, 7 insertions, 8 deletions
diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c
index b056fbe..32711a1 100644
--- a/cpu/mcf532x/cpu_init.c
+++ b/cpu/mcf532x/cpu_init.c
@@ -113,6 +113,8 @@ void cpu_init_f(void)
fbcs->cscr5 = CFG_CS5_CTRL;
fbcs->csmr5 = CFG_CS5_MASK;
#endif
+
+ icache_enable();
}
/*
@@ -120,6 +122,5 @@ void cpu_init_f(void)
*/
int cpu_init_r(void)
{
- icache_enable();
return (0);
}
diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index acd3494..ac44aaa 100644
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -270,8 +270,6 @@ icache_enable:
movec %d0, %CACR /* Invalidate cache */
move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
- move.l #(CFG_CS0_BASE + 0x0000), %d0 /* Setup cache mask */
- movec %d0, %ACR1 /* Enable cache */
move.l #0x80000200, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
@@ -284,11 +282,11 @@ icache_enable:
.globl icache_disable
icache_disable:
- move.l #0x00000100, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
+ move.l #0x01000000, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Disable cache */
clr.l %d0 /* Setup cache mask */
- movec %d0, %ACR0 /* Enable cache */
- movec %d0, %ACR1 /* Enable cache */
+ movec %d0, %ACR0
+ movec %d0, %ACR1
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
moveq #0, %d0
@@ -303,7 +301,7 @@ icache_status:
.globl icache_invalid
icache_invalid:
- move.l #0x01000000, %d0 /* Setup cache mask */
+ move.l #0x81000200, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
rts