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authorWolfgang Denk <wd@pollux.denx.de>2006-03-13 00:46:05 +0100
committerWolfgang Denk <wd@pollux.denx.de>2006-03-13 00:46:05 +0100
commitb38dbd4622a2abeedf9fcb1806958d9afac0bbd4 (patch)
tree5141e4352c2db17593f8c30b0f19cb6ab3ba354d /cpu
parentf07217c9e2912af5b2f05d61829f62cc865b481f (diff)
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Fix bug in [id]cache_status commands for MPC85xx processors;
should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc85xx/start.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 7ac6573..f96a4c3 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -715,7 +715,7 @@ icache_disable:
.globl icache_status
icache_status:
mfspr r3,L1CSR1
- srwi r3, r3, 31 /* >>31 => select bit 0 */
+ andi. r3,r3,1
blr
.globl dcache_enable
@@ -748,7 +748,7 @@ dcache_disable:
.globl dcache_status
dcache_status:
mfspr r3,L1CSR0
- srwi r3, r3, 31 /* >>31 => select bit 0 */
+ andi. r3,r3,1
blr
.globl get_pir