summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
authorStefan Roese <sr@denx.de>2007-06-01 13:45:00 +0200
committerStefan Roese <sr@denx.de>2007-06-01 13:45:00 +0200
commit7187db73491c8de0fb56efb5e5134ba5ec443089 (patch)
tree54e82b89a7cd04f1a082e59fdd350922b7dd5f8c /cpu
parent19bf91f9628f80a55d4f171df71041574882b3d6 (diff)
downloadu-boot-imx-7187db73491c8de0fb56efb5e5134ba5ec443089.zip
u-boot-imx-7187db73491c8de0fb56efb5e5134ba5ec443089.tar.gz
u-boot-imx-7187db73491c8de0fb56efb5e5134ba5ec443089.tar.bz2
ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)
Add config option for 180 degree advance clock control as needed for the AMCC Luan eval board. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/ppc4xx/44x_spd_ddr2.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 2ecd3e4..48b9ee2 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -465,7 +465,11 @@ long int initdram(int board_type)
* Set the SDRAM Clock Timing Register
*-----------------------------------------------------------------*/
mfsdram(SDRAM_CLKTR, val);
+#ifdef CFG_44x_DDR2_CKTR_180
+ mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV);
+#else
mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
+#endif
/*------------------------------------------------------------------
* Program the BxCF registers.
@@ -1117,7 +1121,8 @@ static void program_codt(unsigned long *dimm_populated,
modt3 = 0x00000000;
}
if (total_rank == 4) {
- codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | CALC_ODT_R(2) | CALC_ODT_R(3);
+ codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
+ CALC_ODT_R(2) | CALC_ODT_R(3);
modt0 = CALC_ODT_RW(2);
modt1 = 0x00000000;
modt2 = CALC_ODT_RW(0);