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authorTsiChung Liew <Tsi-Chung.Liew@freescale.com>2008-07-09 16:20:23 -0500
committerJohn Rigby <jrigby@freescale.com>2008-07-11 10:45:59 -0600
commit47bf9c71ae838305a3ea3161af8d14e6f3fc2c82 (patch)
tree0768c1f95aa63e5a759d486bd9ff7ee24fd88da8 /cpu
parentbc3ccb139f0836f0a834cfd370a120a00ad7e63a (diff)
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ColdFire: Fix FB CS not setup properly for Mcf5282
Remove all CFG_CSn_RO in cpu/mcf52x2/cpu_init.c. If CFG_CSn_RO is defined as 0, the chipselect will not be assigned. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mcf52x2/cpu_init.c12
1 files changed, 4 insertions, 8 deletions
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 207a37e..344bcee 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -419,8 +419,7 @@ void cpu_init_f(void)
else is doing it! */
#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
- defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
- defined(CFG_CS0_WS)
+ defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
@@ -447,8 +446,7 @@ void cpu_init_f(void)
#endif
#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
- defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
- defined(CFG_CS1_WS)
+ defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
@@ -476,8 +474,7 @@ void cpu_init_f(void)
#endif
#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
- defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
- defined(CFG_CS2_WS)
+ defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
@@ -505,8 +502,7 @@ void cpu_init_f(void)
#endif
#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
- defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
- defined(CFG_CS3_WS)
+ defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;