Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:

	cpu/arm920t/ep93xx/timer.c

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

10 files changed, 216 insertions, 46 deletions

diff --git a/cpu/arm920t/ep93xx/Makefile b/cpu/arm920t/ep93xx/Makefile
index 30e12af..01a2f55 100644
--- a/cpu/arm920t/ep93xx/Makefile
+++ b/cpu/arm920t/ep93xx/Makefile
@@ -53,4 +53,3 @@ include $(SRCTREE)/rules.mk
 sinclude $(obj).depend
 
 #########################################################################
-
diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c
index 4a0ce4d..31304b7 100644
--- a/cpu/arm920t/ep93xx/timer.c
+++ b/cpu/arm920t/ep93xx/timer.c
@@ -1,7 +1,8 @@
 /*
  * Cirrus Logic EP93xx timer support.
  *
- * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
+ * Copyright (C) 2009, 2010
+ * Matthias Kaehlcke <matthias@kaehlcke.net>
  *
  * Copyright (C) 2004, 2005
  * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
@@ -41,9 +42,17 @@
 static struct ep93xx_timer
 {
 	unsigned long long ticks;
-	unsigned long last_read;
+	unsigned long last_update;
 } timer;
 
+static inline unsigned long clk_to_systicks(unsigned long long clk_ticks)
+{
+	unsigned long long sys_ticks = (clk_ticks * CONFIG_SYS_HZ);
+	do_div(sys_ticks, TIMER_FREQ);
+
+	return (unsigned long)sys_ticks;
+}
+
 static inline unsigned long long usecs_to_ticks(unsigned long usecs)
 {
 	unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
@@ -52,18 +61,11 @@ static inline unsigned long long usecs_to_ticks(unsigned long usecs)
 	return ticks;
 }
 
-static inline void read_timer(void)
+static inline unsigned long read_timer(void)
 {
-	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
-	const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
-
-	if (now >= timer.last_read)
-		timer.ticks += now - timer.last_read;
-	else
-		/* an overflow occurred */
-		timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
+	struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
 
-	timer.last_read = now;
+	return TIMER_MAX_VAL - readl(&timer->timer3.value);
 }
 
 /*
@@ -71,14 +73,17 @@ static inline void read_timer(void)
  */
 unsigned long long get_ticks(void)
 {
-	unsigned long long sys_ticks;
+	const unsigned long now = read_timer();
 
-	read_timer();
+	if (now >= timer.last_update)
+		timer.ticks += now - timer.last_update;
+	else
+		/* an overflow occurred */
+		timer.ticks += TIMER_MAX_VAL - timer.last_update + now;
 
-	sys_ticks = timer.ticks * CONFIG_SYS_HZ;
-	do_div(sys_ticks, TIMER_FREQ);
+	timer.last_update = now;
 
-	return sys_ticks;
+	return clk_to_systicks(timer.ticks);
 }
 
 unsigned long get_timer_masked(void)
@@ -93,7 +98,7 @@ unsigned long get_timer(unsigned long base)
 
 void reset_timer_masked(void)
 {
-	read_timer();
+	timer.last_update = read_timer();
 	timer.ticks = 0;
 }
 
@@ -104,29 +109,28 @@ void reset_timer(void)
 
 void __udelay(unsigned long usec)
 {
-	unsigned long long target;
-
-	read_timer();
+	/* read the timer and update timer.ticks */
+	get_ticks();
 
-	target = timer.ticks + usecs_to_ticks(usec);
+	const unsigned long long target = timer.ticks + usecs_to_ticks(usec);
 
 	while (timer.ticks < target)
-		read_timer();
+		get_ticks();
 }
 
 int timer_init(void)
 {
-	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+	struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
 
-	/* use timer 3 with 508KHz and free running, not enabled now */
-	writel(TIMER_CLKSEL, &timer_regs->timer3.control);
+	/* use timer 3 with 508KHz and free running */
+	writel(TIMER_CLKSEL, &timer->timer3.control);
 
-	/* set initial timer value */
-	writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
+	/* set initial timer value 3 */
+	writel(TIMER_MAX_VAL, &timer->timer3.load);
 
 	/* Enable the timer */
 	writel(TIMER_ENABLE | TIMER_CLKSEL,
-		&timer_regs->timer3.control);
+		&timer->timer3.control);
 
 	reset_timer_masked();
 
diff --git a/cpu/arm926ejs/spear/Makefile b/cpu/arm926ejs/spear/Makefile
index bf8dfa8..bf8dfa8 100755..100644
--- a/cpu/arm926ejs/spear/Makefile
+++ b/cpu/arm926ejs/spear/Makefile
diff --git a/cpu/arm926ejs/spear/reset.c b/cpu/arm926ejs/spear/reset.c
index 73ad86d..73ad86d 100755..100644
--- a/cpu/arm926ejs/spear/reset.c
+++ b/cpu/arm926ejs/spear/reset.c
diff --git a/cpu/arm926ejs/spear/timer.c b/cpu/arm926ejs/spear/timer.c
index 06858b4..06858b4 100755..100644
--- a/cpu/arm926ejs/spear/timer.c
+++ b/cpu/arm926ejs/spear/timer.c
diff --git a/cpu/arm926ejs/versatile/timer.c b/cpu/arm926ejs/versatile/timer.c
index 563db36..563db36 100755..100644
--- a/cpu/arm926ejs/versatile/timer.c
+++ b/cpu/arm926ejs/versatile/timer.c
diff --git a/cpu/arm_cortexa8/mx51/lowlevel_init.S b/cpu/arm_cortexa8/mx51/lowlevel_init.S
index 700506e..31af9e2 100644
--- a/cpu/arm_cortexa8/mx51/lowlevel_init.S
+++ b/cpu/arm_cortexa8/mx51/lowlevel_init.S
@@ -33,11 +33,11 @@
 	mcr 15, 0, r0, c1, c0, 1
 
 	/* reconfigure L2 cache aux control reg */
-	mov r0, #0xC0                   /* tag RAM */
-	add r0, r0, #0x4                /* data RAM */
-	orr r0, r0, #(1 << 24)          /* disable write allocate delay */
-	orr r0, r0, #(1 << 23)          /* disable write allocate combine */
-	orr r0, r0, #(1 << 22)          /* disable write allocate */
+	mov r0, #0xC0			/* tag RAM */
+	add r0, r0, #0x4		/* data RAM */
+	orr r0, r0, #(1 << 24)		/* disable write allocate delay */
+	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
+	orr r0, r0, #(1 << 22)		/* disable write allocate */
 
 	cmp r3, #0x10    /* r3 contains the silicon rev */
 
@@ -157,7 +157,7 @@
 
 	/* Switch peripheral to PLL 3 */
 	ldr r0, =CCM_BASE_ADDR
-        ldr r1, =0x000010C0
+	ldr r1, =0x000010C0
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]
@@ -255,17 +255,17 @@ lowlevel_init:
 	str r1, [r0, #0x4]
 
 #ifdef ENABLE_IMPRECISE_ABORT
-	mrs r1, spsr            /* save old spsr */
-	mrs r0, cpsr            /* read out the cpsr */
-	bic r0, r0, #0x100      /* clear the A bit */
-	msr spsr, r0            /* update spsr */
-	add lr, pc, #0x8        /* update lr */
-	movs pc, lr             /* update cpsr */
+	mrs r1, spsr		/* save old spsr */
+	mrs r0, cpsr		/* read out the cpsr */
+	bic r0, r0, #0x100	/* clear the A bit */
+	msr spsr, r0		/* update spsr */
+	add lr, pc, #0x8	/* update lr */
+	movs pc, lr		/* update cpsr */
 	nop
 	nop
 	nop
 	nop
-	msr spsr, r1            /* restore old spsr */
+	msr spsr, r1		/* restore old spsr */
 #endif
 
 	init_l2cc
diff --git a/cpu/mpc512x/diu.c b/cpu/mpc512x/diu.c
index a24f395..ca459a1 100644
--- a/cpu/mpc512x/diu.c
+++ b/cpu/mpc512x/diu.c
@@ -145,10 +145,10 @@ void *video_hw_init(void)
 	struct fb_info *info;
 
 	if (mpc5121_diu_init() < 0)
-		return;
+		return NULL;
 
 	/* fill in Graphic device struct */
-	sprintf(pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz",
+	sprintf(pGD->modeIdent, "%dx%dx%d %dkHz %dHz",
 		xres, yres, 32, 64, 60);
 
 	pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
diff --git a/cpu/mpc824x/.gitignore b/cpu/mpc824x/.gitignore
new file mode 100644
index 0000000..2d79931
--- /dev/null
+++ b/cpu/mpc824x/.gitignore
@@ -0,0 +1 @@
+/bedbug_603e.c
diff --git a/cpu/nios2/serial.c b/cpu/nios2/serial.c
index 8bbb803..6c835af 100644
--- a/cpu/nios2/serial.c
+++ b/cpu/nios2/serial.c
@@ -2,6 +2,9 @@
  * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
  * Scott McNutt <smcnutt@psyent.com>
  *
+ * YANU Support:
+ * Copyright 2010, Renato Andreola <renato.andreola@imagos.it>
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -26,6 +29,7 @@
 #include <watchdog.h>
 #include <asm/io.h>
 #include <nios2-io.h>
+#include <nios2-yanu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -74,10 +78,172 @@ int serial_getc (void)
 	return (c);
 }
 
+#elif defined(CONFIG_CONSOLE_YANU)
+/*-----------------------------------------------------------------*/
+/* YANU Imagos serial port */
+/*-----------------------------------------------------------------*/
+
+static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE;
+
+#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
+
+/* Everything's already setup for fixed-baud PTF assignment*/
+
+void serial_setbrg (void)
+{
+	int n, k;
+	const unsigned max_uns = 0xFFFFFFFF;
+	unsigned best_n, best_m, baud;
+
+	/* compute best N and M couple */
+	best_n = YANU_MAX_PRESCALER_N;
+	for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) {
+		if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >=
+		    (unsigned)CONFIG_BAUDRATE) {
+			best_n = n;
+			break;
+		}
+	}
+	for (k = 0;; k++) {
+		if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k)))
+			break;
+	}
+	best_m =
+	    ((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) /
+	    ((unsigned)CONFIG_SYS_CLK_FREQ >> k);
+
+	baud = best_m + best_n * YANU_BAUDE;
+	writel(&uart->baud, baud);
+
+	return;
+}
+
+#else
+
+void serial_setbrg (void)
+{	
+	int n, k;
+	const unsigned max_uns = 0xFFFFFFFF;
+	unsigned best_n, best_m, baud;
+
+	/* compute best N and M couple */
+	best_n = YANU_MAX_PRESCALER_N;
+	for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) {
+		if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >=
+		    gd->baudrate) {
+			best_n = n;
+			break;
+		}
+	}
+	for (k = 0;; k++) {
+		if (gd->baudrate <= (max_uns >> (15+n-k)))
+			break;
+	}
+	best_m =
+	    (gd->baudrate * (1 << (15 + n - k))) /
+	    ((unsigned)CONFIG_SYS_CLK_FREQ >> k);
+
+	baud = best_m + best_n * YANU_BAUDE;
+	writel(&uart->baud, baud);
+
+	return;
+}
+
+
+#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
+
+int serial_init (void)
+{
+	unsigned action,control;
+
+	/* status register cleanup */
+	action =  YANU_ACTION_RRRDY     |
+		YANU_ACTION_RTRDY       |
+		YANU_ACTION_ROE         |
+		YANU_ACTION_RBRK        |
+		YANU_ACTION_RFE         |
+		YANU_ACTION_RPE         |
+	    YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR;
+
+	writel(&uart->action, action);
+	
+	/*  control register cleanup */
+	/* no interrupts enabled */
+	/* one stop bit */
+	/* hardware flow control disabled */
+	/* 8 bits */
+	control = (0x7 << YANU_CONTROL_BITS_POS);
+	/* enven parity just to be clean */
+	control |= YANU_CONTROL_PAREVEN;
+	/* we set threshold for fifo */
+	control |= YANU_CONTROL_RDYDLY * YANU_RXFIFO_DLY;
+	control |= YANU_CONTROL_TXTHR *  YANU_TXFIFO_THR;
+
+	writel(&uart->control, control);
+
+	/* to set baud rate */
+	serial_setbrg();
+
+	return (0);
+}
+
+
+/*-----------------------------------------------------------------------
+ * YANU CONSOLE
+ *---------------------------------------------------------------------*/
+void serial_putc (char c)
+{
+	int tx_chars;
+	unsigned status;
+
+	if (c == '\n')
+		serial_putc ('\r');
+	
+	while (1) {
+		status = readl(&uart->status);
+		tx_chars = (status>>YANU_TFIFO_CHARS_POS)
+			& ((1<<YANU_TFIFO_CHARS_N)-1);
+		if (tx_chars < YANU_TXFIFO_SIZE-1)
+			break;
+		WATCHDOG_RESET ();
+	}
+
+	writel(&uart->data, (unsigned char)c);
+}
+
+void serial_puts (const char *s)
+{
+	while (*s != 0) {
+		serial_putc (*s++);
+	}
+}
+
+
+int serial_tstc(void)
+{
+	unsigned status ;
+
+	status = readl(&uart->status);
+	return (((status >> YANU_RFIFO_CHARS_POS) &
+		 ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0);
+}	
+
+int serial_getc (void)
+{
+	while (serial_tstc() == 0)
+		WATCHDOG_RESET ();
+	
+	/* first we pull the char */
+	writel(&uart->action, YANU_ACTION_RFIFO_PULL);
+
+	return(readl(&uart->data) & YANU_DATA_CHAR_MASK);
+}
+
+#else /*CONFIG_CONSOLE_YANU*/
+
 /*------------------------------------------------------------------
  * UART the serial port
  *-----------------------------------------------------------------*/
-#else
 
 static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE;