summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2009-09-01 22:01:54 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-09-08 09:10:04 -0500
commit2abbd31da6d900473ed678ca50789ee58bc9bb00 (patch)
tree04faa2d9df989a87f184b745848e657dd03ff634 /cpu
parent13d46ab2572c0283d34f93bebc9a41295ef84ca5 (diff)
downloadu-boot-imx-2abbd31da6d900473ed678ca50789ee58bc9bb00.zip
u-boot-imx-2abbd31da6d900473ed678ca50789ee58bc9bb00.tar.gz
u-boot-imx-2abbd31da6d900473ed678ca50789ee58bc9bb00.tar.bz2
ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist
The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc85xx/ddr-gen3.c1
-rw-r--r--cpu/mpc8xxx/ddr/ctrl_regs.c23
2 files changed, 0 insertions, 24 deletions
diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c
index 8ac3d5f..0691ca4 100644
--- a/cpu/mpc85xx/ddr-gen3.c
+++ b/cpu/mpc85xx/ddr-gen3.c
@@ -74,7 +74,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
- out_be32(&ddr->ddr_pd_cntl, regs->ddr_pd_cntl);
out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 1689d68..5e63c5d 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1066,28 +1066,6 @@ static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
}
-/* DDR Pre-Drive Conditioning Control (DDR_PD_CNTL) */
-static void set_ddr_pd_cntl(fsl_ddr_cfg_regs_t *ddr)
-{
- /* Termination value during pre-drive conditioning */
- unsigned int tvpd = 0;
- unsigned int pd_en = 0; /* Pre-Drive Conditioning Enable */
- unsigned int pdar = 0; /* Pre-Drive After Read */
- unsigned int pdaw = 0; /* Pre-Drive After Write */
- unsigned int pd_on = 0; /* Pre-Drive Conditioning On */
- unsigned int pd_off = 0; /* Pre-Drive Conditioning Off */
-
- ddr->ddr_pd_cntl = (0
- | ((pd_en & 0x1) << 31)
- | ((tvpd & 0x7) << 28)
- | ((pdar & 0x7F) << 20)
- | ((pdaw & 0x7F) << 12)
- | ((pd_on & 0x1F) << 6)
- | ((pd_off & 0x1F) << 0)
- );
-}
-
-
/* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */
static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr)
{
@@ -1355,7 +1333,6 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_ddr_zq_cntl(ddr, zq_en);
set_ddr_wrlvl_cntl(ddr, wrlvl_en);
- set_ddr_pd_cntl(ddr);
set_ddr_sr_cntr(ddr, sr_it);
set_ddr_sdram_rcw_1(ddr);