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| author | Lepcha Suchit <Suchit.Lepcha@freescale.com> | 2008-10-16 13:38:00 -0500 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2008-10-17 10:39:18 -0500 |
| commit | fa7b1c07e9371aea8f87ee6d3c2ea5564bd8cc8d (patch) | |
| tree | d379de1b2b11e4d21ac02fd54b06c4e80930e78f /cpu | |
| parent | bf29e0ea0af03d593c64614136acc723a7a022a2 (diff) | |
| download | u-boot-imx-fa7b1c07e9371aea8f87ee6d3c2ea5564bd8cc8d.zip u-boot-imx-fa7b1c07e9371aea8f87ee6d3c2ea5564bd8cc8d.tar.gz u-boot-imx-fa7b1c07e9371aea8f87ee6d3c2ea5564bd8cc8d.tar.bz2 | |
83xx NAND boot: wait for LTESR[CC]
At least some revisions of the 8313, and possibly other chips, do not
wait for all pages of the initial 4K NAND region to be loaded before
beginning execution; thus, we wait for it before branching out of the
first NAND page.
This fixes warm reset problems when booting from NAND on 8313erdb.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc83xx/start.S | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 14bfbda..6ff6682 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -167,6 +167,18 @@ boot_warm: /* time t 5 */ /* Initialise the E300 processor core */ /*------------------------------------------*/ +#ifdef CONFIG_NAND_SPL + /* The FCM begins execution after only the first page + * is loaded. Wait for the rest before branching + * to another flash page. + */ + addi r7, r3, 0x50b0 +1: dcbi 0, r7 + lwz r6, 0(r7) + andi. r6, r6, 1 + beq 1b +#endif + bl init_e300_core #ifdef CFG_FLASHBOOT |