summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
authorStefano Babic <sbabic@denx.de>2010-03-05 17:54:37 +0100
committerTom Rix <Tom.Rix@windriver.com>2010-03-07 12:36:36 -0600
commite4d34492017c95e4041ea0c581e1ab8d1d49381b (patch)
tree3badc8c1ab6433507c7c9d6993ad7aaacb47bf4f /cpu
parent9d69e33d8d0f112fe3a089101d023e87431684d1 (diff)
downloadu-boot-imx-e4d34492017c95e4041ea0c581e1ab8d1d49381b.zip
u-boot-imx-e4d34492017c95e4041ea0c581e1ab8d1d49381b.tar.gz
u-boot-imx-e4d34492017c95e4041ea0c581e1ab8d1d49381b.tar.bz2
MX51: removed warnings for the mx51evk
The patch removes warnings at compile time and provides some cleanup code: - Removed comment on NAND (not yet supported) from lowlevel_init.S - Removed NFMS bit definition from imx-regs.h The bit is only related to MX.25/35 and can lead to confusion - Moved is_soc_rev() to soc specific code (removed from mx51evk.c) Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/arm_cortexa8/mx51/clock.c3
-rw-r--r--cpu/arm_cortexa8/mx51/iomux.c1
-rw-r--r--cpu/arm_cortexa8/mx51/lowlevel_init.S1
-rw-r--r--cpu/arm_cortexa8/mx51/soc.c7
-rw-r--r--cpu/arm_cortexa8/mx51/speed.c1
5 files changed, 10 insertions, 3 deletions
diff --git a/cpu/arm_cortexa8/mx51/clock.c b/cpu/arm_cortexa8/mx51/clock.c
index 3c6f0c0..38480ac 100644
--- a/cpu/arm_cortexa8/mx51/clock.c
+++ b/cpu/arm_cortexa8/mx51/clock.c
@@ -28,6 +28,7 @@
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
enum pll_clocks {
PLL1_CLOCK = 0,
@@ -42,7 +43,7 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
[PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
};
-struct mxc_ccm_reg *mxc_ccm = MXC_CCM_BASE;
+struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
/*
* Calculate the frequency of this pll.
diff --git a/cpu/arm_cortexa8/mx51/iomux.c b/cpu/arm_cortexa8/mx51/iomux.c
index fc39e8a..62b2954 100644
--- a/cpu/arm_cortexa8/mx51/iomux.c
+++ b/cpu/arm_cortexa8/mx51/iomux.c
@@ -25,6 +25,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx51_pins.h>
#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
/* IOMUX register (base) addresses */
enum iomux_reg_addr {
diff --git a/cpu/arm_cortexa8/mx51/lowlevel_init.S b/cpu/arm_cortexa8/mx51/lowlevel_init.S
index 680a90e..700506e 100644
--- a/cpu/arm_cortexa8/mx51/lowlevel_init.S
+++ b/cpu/arm_cortexa8/mx51/lowlevel_init.S
@@ -276,7 +276,6 @@ lowlevel_init:
init_clock
- /* return from mxc_nand_load */
/* r12 saved upper lr*/
mov pc,lr
diff --git a/cpu/arm_cortexa8/mx51/soc.c b/cpu/arm_cortexa8/mx51/soc.c
index 5e69301..2a139b2 100644
--- a/cpu/arm_cortexa8/mx51/soc.c
+++ b/cpu/arm_cortexa8/mx51/soc.c
@@ -25,9 +25,14 @@
#include <common.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
#include <asm/errno.h>
#include <asm/io.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
u32 get_cpu_rev(void)
{
int reg;
@@ -65,7 +70,7 @@ int print_cpuinfo(void)
printf("CPU: Freescale i.MX51 family %d.%dV at %d MHz\n",
(cpurev & 0xF0) >> 4,
(cpurev & 0x0F) >> 4,
- get_mcu_main_clk() / 1000000);
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
return 0;
}
#endif
diff --git a/cpu/arm_cortexa8/mx51/speed.c b/cpu/arm_cortexa8/mx51/speed.c
index 10acbbf..a444def 100644
--- a/cpu/arm_cortexa8/mx51/speed.c
+++ b/cpu/arm_cortexa8/mx51/speed.c
@@ -26,6 +26,7 @@
#include <common.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
int get_clocks(void)
{