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authorStefan Roese <sr@denx.de>2008-09-08 10:35:49 +0200
committerStefan Roese <sr@denx.de>2008-09-08 10:35:49 +0200
commitc351575c226eaad85f12b0d346e762260b263531 (patch)
treec2c1748a95c589278cbf048c191728fd5a9ea753 /cpu
parentac53ee8318678190bf3c68da477a84a657d86fb0 (diff)
parent302e52e0b1d4c7f994991709d0cb6c3ea612cdb5 (diff)
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Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc8xxx/ddr/ctrl_regs.c6
-rw-r--r--cpu/s3c44b0/cpu.c4
2 files changed, 7 insertions, 3 deletions
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index ca67551..e6c2a5c 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -520,7 +520,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
unsigned int wr; /* Write Recovery */
unsigned int dll_res; /* DLL Reset */
unsigned int mode; /* Normal=0 or Test=1 */
- unsigned int caslat; /* CAS# latency */
+ unsigned int caslat = 0;/* CAS# latency */
/* BT: Burst Type (0=Sequential, 1=Interleaved) */
unsigned int bt;
unsigned int bl; /* BL: Burst Length */
@@ -572,7 +572,9 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
0x6, /* 2.5 clocks */
0x3 /* 3.0 clocks */
};
- caslat = mode_caslat_table[cas_latency - 1];
+ caslat = mode_caslat_table[cas_latency - 1];
+ } else {
+ printf("Warning: unknown cas_latency %d\n", cas_latency);
}
#elif defined(CONFIG_FSL_DDR2)
caslat = cas_latency;
diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c
index eae6adb..fd09bf9 100644
--- a/cpu/s3c44b0/cpu.c
+++ b/cpu/s3c44b0/cpu.c
@@ -188,7 +188,7 @@ int rtc_get (struct rtc_time* tm)
return 0;
}
-void rtc_set (struct rtc_time* tm)
+int rtc_set (struct rtc_time* tm)
{
if(tm->tm_year < 2000)
tm->tm_year -= 1900;
@@ -204,6 +204,8 @@ void rtc_set (struct rtc_time* tm)
BCDMIN = HEX2BCD(tm->tm_min);
BCDSEC = HEX2BCD(tm->tm_sec);
RTCCON &= 1;
+
+ return 0;
}
void rtc_reset (void)