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authorPeter Tyser <ptyser@xes-inc.com>2008-11-11 10:17:10 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-12-03 22:46:42 -0600
commita2cd50ed6ef0ac6b127b3d6db756979a8336718d (patch)
treea8064eb08a501fdecadfb50af56f646c90be0f3a /cpu
parente57f0fa1333cdf3ca36110aac2900712a5f82976 (diff)
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85xx: Add CPU 2 errata workaround to all 8548 boards
All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc85xx/cpu_init.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 3a8aef2..5862bd6 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -174,6 +174,19 @@ void cpu_init_f (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
extern void m8560_cpm_reset (void);
+#ifdef CONFIG_MPC8548
+ ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ uint svr = get_svr();
+
+ /*
+ * CPU2 errata workaround: A core hang possible while executing
+ * a msync instruction and a snoopable transaction from an I/O
+ * master tagged to make quick forward progress is present.
+ * Fixed in silicon rev 2.1.
+ */
+ if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
+ out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
+#endif
disable_tlb(14);
disable_tlb(15);