summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
authorStefan Roese <sr@denx.de>2007-06-15 07:39:43 +0200
committerStefan Roese <sr@denx.de>2007-06-15 07:39:43 +0200
commit85f737376d5ff3d5f0d45a8b657686326d175307 (patch)
tree5f3393f5cfbaccb32051cba390a4b1bc9bce7cb0 /cpu
parentdbca208518e5e7f01a6420588d1cd6e60db74c2b (diff)
downloadu-boot-imx-85f737376d5ff3d5f0d45a8b657686326d175307.zip
u-boot-imx-85f737376d5ff3d5f0d45a8b657686326d175307.tar.gz
u-boot-imx-85f737376d5ff3d5f0d45a8b657686326d175307.tar.bz2
[ppc4xx] Extend 44x GPIO setup with default output state
The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup is extended with the default GPIO output state (level). Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/ppc4xx/gpio.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c
index fb0f575..5235203 100644
--- a/cpu/ppc4xx/gpio.c
+++ b/cpu/ppc4xx/gpio.c
@@ -103,6 +103,18 @@ void gpio_write_bit(int pin, int val)
out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin));
}
+int gpio_read_out_bit(int pin)
+{
+ u32 offs = 0;
+
+ if (pin >= GPIO_MAX) {
+ offs = 0x100;
+ pin -= GPIO_MAX;
+ }
+
+ return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
+}
+
#if defined(CFG_440_GPIO_TABLE)
void gpio_set_chip_configuration(void)
{
@@ -157,11 +169,37 @@ void gpio_set_chip_configuration(void)
switch (gpio_tab[gpio_core][i].alt_nb) {
case GPIO_SEL:
if (gpio_core == GPIO0) {
+ /*
+ * Setup output value
+ * 1 -> high level
+ * 0 -> low level
+ * else -> don't touch
+ */
+ reg = in32(GPIO0_OR);
+ if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
+ reg |= (0x80000000 >> (i));
+ else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
+ reg &= ~(0x80000000 >> (i));
+ out32(GPIO0_OR, reg);
+
reg = in32(GPIO0_TCR) | (0x80000000 >> (i));
out32(GPIO0_TCR, reg);
}
if (gpio_core == GPIO1) {
+ /*
+ * Setup output value
+ * 1 -> high level
+ * 0 -> low level
+ * else -> don't touch
+ */
+ reg = in32(GPIO0_OR);
+ if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
+ reg |= (0x80000000 >> (i));
+ else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
+ reg &= ~(0x80000000 >> (i));
+ out32(GPIO0_OR, reg);
+
reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
out32(GPIO1_TCR, reg);
}