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authorMike Frysinger <vapier@gentoo.org>2009-04-04 08:10:22 -0400
committerMike Frysinger <vapier@gentoo.org>2009-04-06 17:37:48 -0400
commit48ab1509254a4c175e4f65c478a978928ffe09ec (patch)
tree16a43aec668305a3dce6e08be4fc5f1387574cfe /cpu
parentce1fe4ba6bb9df7c57351436fa17d1af8bbe7916 (diff)
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Blackfin: add workaround for anomaly 05000242
DESCRIPTION: If the DF bit is set prior to a hardware reset, the PLL will continue to divide CLKIN by 2 after the hardware reset, but the DF bit itself will be cleared in the PLL_CTL register. WORKAROUND: Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by 2 after reset. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/blackfin/initcode.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
index d44c6a6..7f54860 100644
--- a/cpu/blackfin/initcode.c
+++ b/cpu/blackfin/initcode.c
@@ -401,7 +401,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)
/* Only reprogram when needed to avoid triggering unnecessary
* PLL relock sequences.
*/
- if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
+ if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
serial_putc('!');
bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
asm("idle;");