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authorDave Liu <daveliu@freescale.com>2009-12-16 10:24:39 -0600
committerKumar Gala <galak@kernel.crashing.org>2010-01-05 13:50:07 -0600
commit3e731aaba30c7011edf6391072eee845ed1b816f (patch)
treeff32b3e1f2bbec7abfcd740f4dda254bd92cf0ab /cpu
parent1aa3d08a0244506b94031522e54fe06ee7a5ae0e (diff)
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fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave
In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc8xxx/ddr/ctrl_regs.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 3be7e22..adc4f6e 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1197,7 +1197,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
/* Don't set up boundaries for other CS
* other than CS0, if bank interleaving
* is enabled and not CS2+CS3 interleaved.
+ * But we need to set the ODT_RD_CFG and
+ * ODT_WR_CFG for CS1_CONFIG here.
*/
+ set_csn_config(i, ddr, popts, dimm_params);
break;
}