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authorDave Liu <r63238@freescale.com>2007-08-04 13:37:39 +0800
committerKim Phillips <kim.phillips@freescale.com>2007-08-10 01:12:40 -0500
commit036575c544cf1b69654d8fb334bda69c6ff3da36 (patch)
treec3719a305ecd8ce8a0f3c016ae70bd763dbbb0ac /cpu
parent1c274c4e05b6dc9b24edc8aa618b02f607ee6eed (diff)
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mpc83xx: Correct the burst length for DDR2 with 32 bits
The burst length should be 4 for DDR2 with 32 bits bus Signed-off-by: Dave Liu <daveliu@freescale.com>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc83xx/spd_sdram.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 647813f..2c17cee 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -574,7 +574,10 @@ long int spd_sdram()
/* Check DIMM data bus width */
if (spd.dataw_lsb == 0x20) {
- burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
+ if (spd.mem_type == SPD_MEMTYPE_DDR)
+ burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
+ if (spd.mem_type == SPD_MEMTYPE_DDR2)
+ burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
printf("\n DDR DIMM: data bus width is 32 bit");
} else {
burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
@@ -730,8 +733,12 @@ long int spd_sdram()
sdram_cfg |= 0x10000000;
/* The DIMM is 32bit width */
- if (spd.dataw_lsb == 0x20)
- sdram_cfg |= 0x000C0000;
+ if (spd.dataw_lsb == 0x20) {
+ if (spd.mem_type == SPD_MEMTYPE_DDR)
+ sdram_cfg |= 0x000C0000;
+ if (spd.mem_type == SPD_MEMTYPE_DDR2)
+ sdram_cfg |= 0x00080000;
+ }
ddrc_ecc_enable = 0;