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authorXinyu Chen <xinyu.chen@freescale.com>2012-07-26 14:27:31 +0800
committerXinyu Chen <xinyu.chen@freescale.com>2012-07-26 14:27:31 +0800
commitd52f815a0dca515559d8239109fbc07a2dd99929 (patch)
treec820c88f98fcb2d6db4665807dc76ad9b1d1a822 /cpu
parent2dbfc63a4a0206d31e419d9e595828e6408dce48 (diff)
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ENGR00217401 common: fix build warning
Fix the build warning in uboot build. Fix bug of incorrect dereference to periph2 clock pre divider. Fix incorrect type of maxpackage size assign, even it's not used at all in fastboot. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/arm_cortexa8/mx6/generic.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c
index c844594..55e6b78 100644
--- a/cpu/arm_cortexa8/mx6/generic.c
+++ b/cpu/arm_cortexa8/mx6/generic.c
@@ -330,7 +330,7 @@ static u32 __get_ddr_clk(void)
>> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) {
+ MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
case 0:
freq = __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ);
break;