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| author | Wolfgang Denk <wd@pollux.denx.de> | 2006-08-27 18:10:01 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.denx.de> | 2006-08-27 18:10:01 +0200 |
| commit | 16850919ff8666f20d047cb83b4ee77581336515 (patch) | |
| tree | 7101d27231e24b9b1173fc76b1353beb0a5ffd50 /cpu | |
| parent | 3b0ff842bf70baf1f370c8e76e8f33a0f9904c1b (diff) | |
| download | u-boot-imx-16850919ff8666f20d047cb83b4ee77581336515.zip u-boot-imx-16850919ff8666f20d047cb83b4ee77581336515.tar.gz u-boot-imx-16850919ff8666f20d047cb83b4ee77581336515.tar.bz2 | |
Code cleanup
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/i386/sc520.c | 2 | ||||
| -rw-r--r-- | cpu/i386/sc520_asm.S | 12 | ||||
| -rw-r--r-- | cpu/ppc4xx/440spe_pcie.c | 2 |
3 files changed, 8 insertions, 8 deletions
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c index 1c4370b..d0a7341 100644 --- a/cpu/i386/sc520.c +++ b/cpu/i386/sc520.c @@ -149,7 +149,7 @@ unsigned long init_sc520_dram(void) /* these memory control registers are set up in the assember part, * in sc520_asm.S, during 'mem_init'. If we muck with them here, * after we are running a stack in RAM, we have troubles. Besides, - * these refresh and delay values are better ? simply specified + * these refresh and delay values are better ? simply specified * outright in the include/configs/{cfg} file since the HW designer * simply dictates it. */ diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S index e1fa37a..8fc713d 100644 --- a/cpu/i386/sc520_asm.S +++ b/cpu/i386/sc520_asm.S @@ -462,7 +462,7 @@ emptybank: #if defined CFG_SDRAM_DRCTMCTL /* just have your hardware desinger _GIVE_ you what you need here! */ - movl $DRCTMCTL, %edi + movl $DRCTMCTL, %edi movb $CFG_SDRAM_DRCTMCTL,%al movb (%edi), %al #else @@ -477,7 +477,7 @@ emptybank: #ifdef CFG_SDRAM_CAS_LATENCY_3T orb $0x10, %al #endif - movb %al, (%edi) + movb %al, (%edi) #endif #endif movl $DRCCTL, %edi /* DRAM Control register */ @@ -537,7 +537,7 @@ bank0: movl (%edi), %eax movl %eax, %ebx -done: +done: movl %ebx, %eax #if CFG_SDRAM_ECC_ENABLE @@ -547,7 +547,7 @@ done: movl $0x1, %edi memtest0: movb $0xa5, (%edi) - cmpb $0xa5, (%edi) + cmpb $0xa5, (%edi) jne out shrl $1, %ecx andl %ecx,%ecx @@ -571,11 +571,11 @@ set_ecc: /* enable NMI mapping for ECC */ movl $ECCINT, %edi mov $0x10, %al - movb %al, (%edi) + movb %al, (%edi) /* Turn on ECC */ movl $ECCCTL, %edi mov $0x05, %al - movb %al, (%edi) + movb %al, (%edi) #endif out: movl %ebx, %eax diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index 2e920aa..b2621c2 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -169,7 +169,7 @@ static void ppc440spe_setup_utl(u32 port) { break; } utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port); - + /* * Set buffer allocations and then assert VRB and TXE. */ |