Merge branch 'master' of rsync://rsync.denx.de/git/u-boot

90 files changed, 584 insertions, 291 deletions

diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c
index 629ed66..706c880 100644
--- a/cpu/74xx_7xx/cpu.c
+++ b/cpu/74xx_7xx/cpu.c
@@ -49,6 +49,8 @@
 #include "../board/MAI/AmigaOneG3SE/memio.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 cpu_t
 get_cpu_type(void)
 {
@@ -111,8 +113,6 @@ get_cpu_type(void)
 #if !defined(CONFIG_BAB7xx)
 int checkcpu (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	uint type   = get_cpu_type();
 	uint pvr    = get_pvr();
 	ulong clock = gd->cpu_clk;
@@ -258,8 +258,6 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #ifdef CONFIG_AMIGAONEG3SE
 unsigned long get_tbclk(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	return (gd->bus_clk / 4);
 }
 #else	/* ! CONFIG_AMIGAONEG3SE */
diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c
index f94ff78..2dc5107 100644
--- a/cpu/74xx_7xx/speed.c
+++ b/cpu/74xx_7xx/speed.c
@@ -29,6 +29,8 @@
 #include "../board/MAI/AmigaOneG3SE/via686.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static const int hid1_multipliers_x_10[] = {
 	25,	/* 0000 - 2.5x */
 	75,	/* 0001 - 7.5x */
@@ -85,7 +87,6 @@ static const int hid1_fx_multipliers_x_10[] = {
 
 int get_clocks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	ulong clock = 0;
 
 	/* calculate the clock frequency based upon the CPU type */
diff --git a/cpu/74xx_7xx/traps.c b/cpu/74xx_7xx/traps.c
index ac5f8bf..50c5eeb 100644
--- a/cpu/74xx_7xx/traps.c
+++ b/cpu/74xx_7xx/traps.c
@@ -36,6 +36,10 @@
 #include <command.h>
 #include <asm/processor.h>
 
+#ifdef CONFIG_AMIGAONEG3SE
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 int (*debugger_exception_handler)(struct pt_regs *) = 0;
 #endif
@@ -58,9 +62,6 @@ extern unsigned long search_exception_table(unsigned long);
 void
 print_backtrace(unsigned long *sp)
 {
-#ifdef CONFIG_AMIGAONEG3SE
-	DECLARE_GLOBAL_DATA_PTR;
-#endif
 	int cnt = 0;
 	unsigned long i;
 
diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
index 85a4849..fa78eaa 100644
--- a/cpu/arm1136/cpu.c
+++ b/cpu/arm1136/cpu.c
@@ -37,6 +37,10 @@
 #include <asm/arch/omap2420.h>
 #endif
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -88,8 +92,6 @@ int cpu_init (void)
 	 * setup up stacks if necessary
 	 */
 #ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
 	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c
index 0f99979..054bab9 100644
--- a/cpu/arm720t/serial.c
+++ b/cpu/arm720t/serial.c
@@ -34,10 +34,10 @@
 
 #include <clps7111.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned int reg = 0;
 
 	switch (gd->baudrate) {
diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c
index 5ad98f0..bc6bf30 100644
--- a/cpu/arm720t/serial_netarm.c
+++ b/cpu/arm720t/serial_netarm.c
@@ -34,6 +34,8 @@
 
 #include <asm/hardware.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PORTA	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA))
 #if !defined(CONFIG_NETARM_NS7520)
 #define PORTB	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB))
@@ -67,9 +69,6 @@ extern void _netarm_led_FAIL1(void);
  */
 void serial_setbrg (void)
 {
-	/* get the gd pointer */
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* set 0 ... make sure pins are configured for serial */
 #if !defined(CONFIG_NETARM_NS7520)
 	PORTA = PORTB =
diff --git a/cpu/arm920t/at91rm9200/serial.c b/cpu/arm920t/at91rm9200/serial.c
index a281932..d563445 100644
--- a/cpu/arm920t/at91rm9200/serial.c
+++ b/cpu/arm920t/at91rm9200/serial.c
@@ -33,6 +33,8 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
 #error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
 #endif
@@ -50,7 +52,6 @@ AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US1;
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int baudrate;
 
 	if ((baudrate = gd->baudrate) <= 0)
diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c
index 2f7963d..f93bf57 100644
--- a/cpu/arm920t/cpu.c
+++ b/cpu/arm920t/cpu.c
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <arm920t.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -91,8 +95,6 @@ int cpu_init (void)
 	 * setup up stacks if necessary
 	 */
 #ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
 	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
diff --git a/cpu/arm920t/ks8695/serial.c b/cpu/arm920t/ks8695/serial.c
index 0dd91e7..aacd1be 100644
--- a/cpu/arm920t/ks8695/serial.c
+++ b/cpu/arm920t/ks8695/serial.c
@@ -25,6 +25,8 @@
 #error "Bad: you didn't configure serial ..."
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  *	Define the UART hardware register access structure.
  */
@@ -54,7 +56,6 @@ int serial_console = 1;
 
 void serial_setbrg(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
 
 	/* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/
diff --git a/cpu/arm920t/s3c24x0/serial.c b/cpu/arm920t/s3c24x0/serial.c
index 8327443..36851ad 100644
--- a/cpu/arm920t/s3c24x0/serial.c
+++ b/cpu/arm920t/s3c24x0/serial.c
@@ -27,6 +27,8 @@
 #include <s3c2410.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_SERIAL1
 #define UART_NR	S3C24X0_UART0
 
@@ -48,7 +50,6 @@
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
 	int i;
 	unsigned int reg = 0;
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 4603cf5..346f0d0 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -237,6 +237,7 @@ _start_armboot:	.word start_armboot
  */
 
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -264,7 +265,7 @@ cpu_init_crit:
 	bl	lowlevel_init
 	mov	lr, ip
 	mov	pc, lr
-
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
 /*
  *************************************************************************
diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c
index c1c6b03..d85b7fa 100644
--- a/cpu/arm925t/cpu.c
+++ b/cpu/arm925t/cpu.c
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <arm925t.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -91,8 +95,6 @@ int cpu_init (void)
 	 * setup up stacks if necessary
 	 */
 #ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
 	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index f57c5a5..722732e 100644
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <arm926ejs.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -91,8 +95,6 @@ int cpu_init (void)
 	 * setup up stacks if necessary
 	 */
 #ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
 	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c
index ba0a4e4..4c63a8d 100644
--- a/cpu/arm946es/cpu.c
+++ b/cpu/arm946es/cpu.c
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <arm946es.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -91,8 +95,6 @@ int cpu_init (void)
 	 * setup up stacks if necessary
 	 */
 #ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
 	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c
index d03b09d..e2309f8 100644
--- a/cpu/arm_intcm/cpu.c
+++ b/cpu/arm_intcm/cpu.c
@@ -33,14 +33,16 @@
 #include <common.h>
 #include <command.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 int cpu_init (void)
 {
 	/*
 	 * setup up stacks if necessary
 	 */
 #ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
 	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c
index 84ae9d9..7b43ffd 100644
--- a/cpu/bf533/serial.c
+++ b/cpu/bf533/serial.c
@@ -51,6 +51,8 @@
 #include <asm/uaccess.h>
 #include "bf533_serial.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 unsigned long pll_div_fact;
 
 void calc_baud(void)
@@ -72,7 +74,6 @@ void calc_baud(void)
 void serial_setbrg(void)
 {
 	int i;
-	DECLARE_GLOBAL_DATA_PTR;
 
 	calc_baud();
 
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 689e775..c83f0bb 100644
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -36,6 +36,8 @@
 #include <asm/pci.h>
 #include <asm/ic/sc520.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * utility functions for boards based on the AMD sc520
  *
@@ -93,8 +95,6 @@ u32 read_mmcr_long(u16 mmcr)
 
 void init_sc520(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* Set the UARTxCTL register at it's slower,
 	 * baud clock giving us a 1.8432 MHz reference
 	 */
@@ -139,7 +139,6 @@ void init_sc520(void)
 
 unsigned long init_sc520_dram(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	bd_t *bd = gd->bd;
 
 	u32 dram_present=0;
diff --git a/cpu/i386/serial.c b/cpu/i386/serial.c
index db13008..e7299a7 100644
--- a/cpu/i386/serial.c
+++ b/cpu/i386/serial.c
@@ -55,6 +55,8 @@
 #include <malloc.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define UART_RBR    0x00
 #define UART_THR    0x00
 #define UART_IER    0x01
@@ -126,13 +128,9 @@ static int serial_div(int baudrate)
 
 int serial_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile char val;
-
 	int bdiv = serial_div(gd->baudrate);
 
-
 	outb(0x80, UART0_BASE + UART_LCR);	/* set DLAB bit */
 	outb(bdiv, UART0_BASE + UART_DLL);	/* set baudrate divisor */
 	outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */
@@ -150,8 +148,6 @@ int serial_init(void)
 
 void serial_setbrg(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned short bdiv;
 
 	bdiv = serial_div(gd->baudrate);
@@ -410,8 +406,6 @@ int serial_buffered_tstc(void)
 #if (CONFIG_KGDB_SER_INDEX & 2)
 void kgdb_serial_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile char val;
 	bdiv = serial_div (CONFIG_KGDB_BAUDRATE);
 
diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c
index 9383473..2a2bd50 100644
--- a/cpu/ixp/cpu.c
+++ b/cpu/ixp/cpu.c
@@ -34,14 +34,16 @@
 #include <command.h>
 #include <asm/arch/ixp425.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 int cpu_init (void)
 {
 	/*
 	 * setup up stacks if necessary
 	 */
 #ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
 	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
diff --git a/cpu/ixp/serial.c b/cpu/ixp/serial.c
index aea0cf8..2015958 100644
--- a/cpu/ixp/serial.c
+++ b/cpu/ixp/serial.c
@@ -31,10 +31,10 @@
 #include <common.h>
 #include <asm/arch/ixp425.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned int quot = 0;
 	int uart = CFG_IXP425_CONSOLE;
 
diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c
index 718f253..578eb73 100644
--- a/cpu/lh7a40x/cpu.c
+++ b/cpu/lh7a40x/cpu.c
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <arm920t.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -90,8 +94,6 @@ int cpu_init (void)
 	 * setup up stacks if necessary
 	 */
 #ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
 	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
diff --git a/cpu/lh7a40x/serial.c b/cpu/lh7a40x/serial.c
index ff5b2d8..2132c05 100644
--- a/cpu/lh7a40x/serial.c
+++ b/cpu/lh7a40x/serial.c
@@ -21,6 +21,8 @@
 #include <common.h>
 #include <lh7a40x.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_CONSOLE_UART1)
 # define UART_CONSOLE 1
 #elif defined(CONFIG_CONSOLE_UART2)
@@ -33,7 +35,6 @@
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
 	int i;
 	unsigned int reg = 0;
diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c
index c730922..79628d0 100644
--- a/cpu/mcf52x2/serial.c
+++ b/cpu/mcf52x2/serial.c
@@ -38,6 +38,8 @@
 #include <asm/m5249.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_M5249
 #define DoubleClock(a) ((double)(CFG_CLK/2) / 32.0 / (double)(a))
 #else
@@ -134,12 +136,10 @@ int rs_get_char(void)
 }
 
 void serial_setbrg(void) {
-	DECLARE_GLOBAL_DATA_PTR;
 	rs_serial_setbaudrate(0,gd->bd->bi_baudrate);
 }
 
 int serial_init(void) {
-	DECLARE_GLOBAL_DATA_PTR;
 	rs_serial_init(0,gd->baudrate);
 	return 0;
 }
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index 519c992..ac860b2 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -24,13 +24,13 @@
 #include <common.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * get_clocks() fills in gd->cpu_clock and gd->bus_clk
  */
 int get_clocks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->cpu_clk = CFG_CLK;
 #ifdef CONFIG_M5249
 	gd->bus_clk = gd->cpu_clk / 2;
diff --git a/cpu/mpc5xx/cpu.c b/cpu/mpc5xx/cpu.c
index 0c22a31..4bef90c 100644
--- a/cpu/mpc5xx/cpu.c
+++ b/cpu/mpc5xx/cpu.c
@@ -34,6 +34,7 @@
 #include <command.h>
 #include <mpc5xx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 #if (defined(CONFIG_MPC555))
 #  define	ID_STR	"MPC555/556"
@@ -62,8 +63,6 @@ static int check_cpu_version (long clock, uint pvr, uint immr)
  */
 int checkcpu (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	ulong clock = gd->cpu_clk;
 	uint immr = get_immr (0);	/* Return full IMMR contents */
 	uint pvr = get_pvr ();		/* Retrieve PVR register */
@@ -104,7 +103,6 @@ void reset_5xx_watchdog (volatile immap_t * immr)
  */
 unsigned long get_tbclk (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	volatile immap_t *immr = (volatile immap_t *) CFG_IMMR;
 	ulong oscclk, factor;
 
diff --git a/cpu/mpc5xx/serial.c b/cpu/mpc5xx/serial.c
index 4868782..ac5556f 100644
--- a/cpu/mpc5xx/serial.c
+++ b/cpu/mpc5xx/serial.c
@@ -34,6 +34,7 @@
 #include <command.h>
 #include <mpc5xx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Local function prototypes
@@ -128,7 +129,6 @@ int serial_tstc()
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	volatile immap_t *immr = (immap_t *)CFG_IMMR;
 	short scxbr;
 
diff --git a/cpu/mpc5xx/speed.c b/cpu/mpc5xx/speed.c
index f6097f5..6a1fa15 100644
--- a/cpu/mpc5xx/speed.c
+++ b/cpu/mpc5xx/speed.c
@@ -31,12 +31,13 @@
 #include <mpc5xx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Get cpu and bus clock
  */
 int get_clocks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 
 #ifndef	CONFIG_5xx_GCLK_FREQ
diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index 2d695d1..6b6f828 100644
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -31,14 +31,14 @@
 #include <mpc5xxx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkcpu (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	ulong clock = gd->cpu_clk;
 	char buf[32];
 #ifndef CONFIG_MGT5100
-	uint svr;
+	uint svr, pvr;
 #endif
 
 	puts ("CPU:   ");
@@ -47,7 +47,8 @@ int checkcpu (void)
 	puts   (CPU_ID_STR);
 	printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID);
 #else
-	svr = get_svr ();
+	svr = get_svr();
+	pvr = get_pvr();
 	switch (SVR_VER (svr)) {
 	case SVR_MPC5200:
 		printf ("MPC5200");
@@ -57,11 +58,10 @@ int checkcpu (void)
 		break;
 	}
 
-	printf (" v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr));
+	printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
+		PVR_MAJ(pvr), PVR_MIN(pvr));
 #endif
-
 	printf (" at %s MHz\n", strmhz (buf, clock));
-
 	return 0;
 }
 
@@ -94,8 +94,6 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
  */
 unsigned long get_tbclk (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	ulong tbclk;
 
 	tbclk = (gd->bus_clk + 3L) / 4L;
diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index 3df0050..b7e00b3 100644
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -24,6 +24,8 @@
 #include <common.h>
 #include <mpc5xxx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Breath some life into the CPU...
  *
@@ -32,8 +34,6 @@
  */
 void cpu_init_f (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned long addecr = (1 << 25); /* Boot_CS */
 #if defined(CFG_RAMBOOT) && defined(CONFIG_MGT5100)
 	addecr |= (1 << 22); /* SDRAM enable */
@@ -152,6 +152,10 @@ void cpu_init_f (void)
 	/* enable timebase */
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
 
+	/* Enable snooping for RAM */
+	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
+	*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
+
 # if defined(CFG_IPBSPEED_133)
 	/* Motorola reports IPB should better run at 133 MHz. */
 	*(vu_long *)MPC5XXX_ADDECR |= 1;
diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index 2e8e549..19737ce 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -14,6 +14,8 @@
 #include "sdma.h"
 #include "fec.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* #define DEBUG	0x28 */
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
@@ -242,7 +244,6 @@ static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
 /********************************************************************/
 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
 	struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
 
@@ -393,7 +394,6 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 /********************************************************************/
 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
 	const uint8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
 
diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c
index 044db46..0f02e78 100644
--- a/cpu/mpc5xxx/i2c.c
+++ b/cpu/mpc5xxx/i2c.c
@@ -23,6 +23,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_HARD_I2C
 
 #include <mpc5xxx.h>
@@ -228,7 +230,6 @@ void i2c_init(int speed, int saddr)
 
 static int mpc_get_fdr(int speed)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	static int fdr = -1;
 
 	if (fdr == -1) {
diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c
index 1af794c..29b99f6 100644
--- a/cpu/mpc5xxx/ide.c
+++ b/cpu/mpc5xxx/ide.c
@@ -27,6 +27,8 @@
 #ifdef CFG_CMD_IDE
 #include <mpc5xxx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define CALC_TIMING(t) (t + period - 1) / period
 
 #ifdef CONFIG_IDE_RESET
@@ -35,7 +37,6 @@ extern void init_ide_reset (void);
 
 int ide_preinit (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	long period, t0, t1, t2_8, t2_16, t4, ta;
 	vu_long reg;
 	struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;
diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index 1d90345..2f01d5c 100644
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -135,10 +135,6 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
 	*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
 	*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
 
-	/* Enable snooping for RAM */
-	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
-	*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d;
-
 	/* Park XLB on PCI */
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c
index 91e1def..cacb9f0 100644
--- a/cpu/mpc5xxx/serial.c
+++ b/cpu/mpc5xxx/serial.c
@@ -33,6 +33,8 @@
 #include <common.h>
 #include <mpc5xxx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_PSC_CONSOLE)
 
 #if CONFIG_PSC_CONSOLE == 1
@@ -55,8 +57,6 @@
 
 int serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
 	unsigned long baseclk;
 	int div;
@@ -146,8 +146,6 @@ serial_tstc(void)
 void
 serial_setbrg(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
 	unsigned long baseclk, div;
 
diff --git a/cpu/mpc5xxx/speed.c b/cpu/mpc5xxx/speed.c
index 4f4e814..7847adc 100644
--- a/cpu/mpc5xxx/speed.c
+++ b/cpu/mpc5xxx/speed.c
@@ -25,6 +25,8 @@
 #include <mpc5xxx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /* Bus-to-Core Multipliers */
@@ -43,8 +45,6 @@ static int bus2core[] = {
 
 int get_clocks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	ulong val, vco;
 
 #if !defined(CFG_MPC5XXX_CLKIN)
@@ -81,8 +81,6 @@ int get_clocks (void)
 
 int prt_mpc5xxx_clks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	printf("       Bus %ld MHz, IPB %ld MHz, PCI %ld MHz\n",
 			gd->bus_clk / 1000000, gd->ipb_clk / 1000000,
 			gd->pci_clk / 1000000);
diff --git a/cpu/mpc8220/cpu.c b/cpu/mpc8220/cpu.c
index 0cfe808..be274cd 100644
--- a/cpu/mpc8220/cpu.c
+++ b/cpu/mpc8220/cpu.c
@@ -31,10 +31,10 @@
 #include <mpc8220.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkcpu (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	ulong clock = gd->cpu_clk;
 	char buf[32];
 
@@ -81,8 +81,6 @@ int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
  */
 unsigned long get_tbclk (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	ulong tbclk;
 
 	tbclk = (gd->bus_clk + 3L) / 4L;
diff --git a/cpu/mpc8220/cpu_init.c b/cpu/mpc8220/cpu_init.c
index 8c358a8..3cf5f66 100644
--- a/cpu/mpc8220/cpu_init.c
+++ b/cpu/mpc8220/cpu_init.c
@@ -24,6 +24,8 @@
 #include <common.h>
 #include <mpc8220.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Breath some life into the CPU...
  *
@@ -32,8 +34,6 @@
  */
 void cpu_init_f (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile flexbus8220_t *flexbus = (volatile flexbus8220_t *) MMAP_FB;
 	volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
 	volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB;
diff --git a/cpu/mpc8220/dramSetup.c b/cpu/mpc8220/dramSetup.c
index 1d0d384..08e3172 100644
--- a/cpu/mpc8220/dramSetup.c
+++ b/cpu/mpc8220/dramSetup.c
@@ -32,6 +32,8 @@ characteristics to initialize the dram on MPC8220
 #include "i2cCore.h"
 #include "dramSetup.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define SPD_SIZE	CFG_SDRAM_SPD_SIZE
 #define DRAM_SPD	(CFG_SDRAM_SPD_I2C_ADDR)<<1	/* on Board SPD eeprom */
 #define TOTAL_BANK	CFG_SDRAM_TOTAL_BANKS
@@ -91,8 +93,6 @@ int spd_readbyte (volatile i2c8220_t * pi2c, u8 * readb, int *index)
 
 int readSpdData (u8 * spdData)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile i2c8220_t *pi2cReg;
 	volatile pcfg8220_t *pcfg;
 	u8 slvAdr = DRAM_SPD;
@@ -403,8 +403,6 @@ u8 checkMuxSetting (u8 rows, u8 columns)
 
 u32 dramSetup (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	draminfo_t DramInfo[TOTAL_BANK];
 	draminfo_t *pDramInfo;
 	u32 size, temp, cfg_value, mode_value, refresh;
diff --git a/cpu/mpc8220/i2c.c b/cpu/mpc8220/i2c.c
index 62f7c0f..d67936d 100644
--- a/cpu/mpc8220/i2c.c
+++ b/cpu/mpc8220/i2c.c
@@ -23,6 +23,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_HARD_I2C
 
 #include <mpc8220.h>
@@ -235,7 +237,6 @@ void i2c_init (int speed, int saddr)
 
 static int mpc_get_fdr (int speed)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	static int fdr = -1;
 
 	if (fdr == -1) {
diff --git a/cpu/mpc8220/speed.c b/cpu/mpc8220/speed.c
index 8346efe..200a762 100644
--- a/cpu/mpc8220/speed.c
+++ b/cpu/mpc8220/speed.c
@@ -25,6 +25,8 @@
 #include <mpc8220.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 typedef struct pllmultiplier {
 	u8 hid1;
 	int multi;
@@ -39,8 +41,6 @@ typedef struct pllmultiplier {
 
 int get_clocks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	pllcfg_t bus2core[] = {
 		{0x02, 2, 8},	/* 1 */
 		{0x01, 2, 4},
@@ -109,8 +109,6 @@ int get_clocks (void)
 
 int prt_mpc8220_clks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	printf ("       Bus %ld MHz, CPU %ld MHz, PCI %ld MHz, VCO %ld MHz\n",
 		gd->bus_clk / 1000000, gd->cpu_clk / 1000000,
 		gd->pci_clk / 1000000, gd->vco_clk / 1000000);
diff --git a/cpu/mpc8220/uart.c b/cpu/mpc8220/uart.c
index 5f54aac..0c4b536 100644
--- a/cpu/mpc8220/uart.c
+++ b/cpu/mpc8220/uart.c
@@ -30,12 +30,13 @@
 #include <common.h>
 #include <mpc8220.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PSC_BASE   MMAP_PSC1
 
 #if defined(CONFIG_PSC_CONSOLE)
 int serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
 	u32 counter;
 
@@ -106,8 +107,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
 	u32 counter;
 
diff --git a/cpu/mpc824x/cpu.c b/cpu/mpc824x/cpu.c
index 312dfe2..0a45cc8 100644
--- a/cpu/mpc824x/cpu.c
+++ b/cpu/mpc824x/cpu.c
@@ -26,10 +26,10 @@
 #include <common.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkcpu (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned int pvr = get_pvr ();
 	unsigned int version = pvr >> 16;
 	unsigned char revision;
diff --git a/cpu/mpc824x/speed.c b/cpu/mpc824x/speed.c
index a37a087..fdcb972 100644
--- a/cpu/mpc824x/speed.c
+++ b/cpu/mpc824x/speed.c
@@ -29,6 +29,8 @@
 #include <mpc824x.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 /* NOTE: This describes the proper use of this file.
  *
@@ -107,8 +109,6 @@ short pllratio_to_factor[] = {
 /* compute the CPU and memory bus clock frequencies */
 int get_clocks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	uint hid1 = mfspr(HID1);
 	hid1 = (hid1 >> (32-5)) & 0x1f;
 	gd->cpu_clk = (pllratio_to_factor[hid1] * get_bus_freq(0) + 5)
diff --git a/cpu/mpc8260/commproc.c b/cpu/mpc8260/commproc.c
index e5c5fcf..8777e77 100644
--- a/cpu/mpc8260/commproc.c
+++ b/cpu/mpc8260/commproc.c
@@ -20,11 +20,11 @@
 #include <common.h>
 #include <asm/cpm_8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void
 m8260_cpm_reset(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *)CFG_IMMR;
 	volatile ulong count;
 
@@ -54,8 +54,6 @@ m8260_cpm_reset(void)
 uint
 m8260_cpm_dpalloc(uint size, uint align)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *)CFG_IMMR;
 	uint	retloc;
 	uint	align_mask, off;
@@ -112,8 +110,6 @@ m8260_cpm_hostalloc(uint size, uint align)
 void
 m8260_cpm_setbrg(uint brg, uint rate)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *)CFG_IMMR;
 	volatile uint	*bp;
 	uint cd = BRG_UART_CLK / rate;
@@ -137,8 +133,6 @@ m8260_cpm_setbrg(uint brg, uint rate)
 void
 m8260_cpm_fastbrg(uint brg, uint rate, int div16)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *)CFG_IMMR;
 	volatile uint	*bp;
 
diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c
index 5d97933..4f23012 100644
--- a/cpu/mpc8260/cpu.c
+++ b/cpu/mpc8260/cpu.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -47,10 +47,10 @@
 #include <asm/processor.h>
 #include <asm/cpm_8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkcpu (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	ulong clock = gd->cpu_clk;
 	uint pvr = get_pvr ();
@@ -264,8 +264,6 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
  */
 unsigned long get_tbclk (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	ulong tbclk;
 
 	tbclk = (gd->bus_clk + 3L) / 4L;
diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c
index babcce4..640026b 100644
--- a/cpu/mpc8260/cpu_init.c
+++ b/cpu/mpc8260/cpu_init.c
@@ -26,6 +26,8 @@
 #include <asm/cpm_8260.h>
 #include <ioports.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static void config_8260_ioports (volatile immap_t * immr)
 {
 	int portnum;
@@ -97,7 +99,6 @@ static void config_8260_ioports (volatile immap_t * immr)
  */
 void cpu_init_f (volatile immap_t * immr)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 #if !defined(CONFIG_COGENT)		/* done in start.S for the cogent */
 	uint sccr;
 #endif
@@ -222,8 +223,6 @@ void cpu_init_f (volatile immap_t * immr)
  */
 int cpu_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base;
 
 	immr->im_cpm.cp_rccr = CFG_RCCR;
@@ -236,8 +235,6 @@ int cpu_init_r (void)
  */
 int prt_8260_rsr (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	static struct {
 		ulong mask;
 		char *desc;
diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c
index ed3515f..584c40f 100644
--- a/cpu/mpc8260/ether_fcc.c
+++ b/cpu/mpc8260/ether_fcc.c
@@ -51,6 +51,8 @@
 #include <miiphy.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
 	defined(CONFIG_NET_MULTI)
 
@@ -644,8 +646,6 @@ swap16 (unsigned short x)
 void
 eth_loopback_test (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *)CFG_IMMR;
 	volatile cpm8260_t *cp = &(immr->im_cpm);
 	int c, nclosed;
diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c
index ea97ab8..34bd389 100644
--- a/cpu/mpc8260/i2c.c
+++ b/cpu/mpc8260/i2c.c
@@ -34,6 +34,8 @@
 /* define to enable debug messages */
 #undef  DEBUG_I2C
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* uSec to wait between polls of the i2c */
 #define DELAY_US	100
 /* uSec to wait for the CPM to start processing the buffer */
@@ -213,8 +215,6 @@ static int i2c_setrate(int hz, int speed)
 
 void i2c_init(int speed, int slaveadd)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immap = (immap_t *)CFG_IMMR ;
 	volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
 	volatile i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
diff --git a/cpu/mpc8260/interrupts.c b/cpu/mpc8260/interrupts.c
index b2e4d83..56e9a72 100644
--- a/cpu/mpc8260/interrupts.c
+++ b/cpu/mpc8260/interrupts.c
@@ -29,6 +29,8 @@
 #include <mpc8260_irq.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /****************************************************************************/
 
 struct irq_action {
@@ -140,8 +142,6 @@ static int m8260_get_irq (struct pt_regs *regs)
 
 int interrupt_init_cpu (unsigned *decrementer_count)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 
 	*decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index 44576de..ea5514f 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -33,6 +33,11 @@
 #include <mpc8260.h>
 #include <asm/m8260_pci.h>
 #include <asm/io.h>
+
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /*
  *   Local->PCI map (from CPU)				   controlled by
  *   MPC826x master window
@@ -234,9 +239,6 @@ static inline void pci_outl (u32 addr, u32 data)
 
 void pci_mpc8250_init (struct pci_controller *hose)
 {
-#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
-	DECLARE_GLOBAL_DATA_PTR;
-#endif
 	u16 tempShort;
 
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
diff --git a/cpu/mpc8260/serial_scc.c b/cpu/mpc8260/serial_scc.c
index 32016f2..3a6eaf0 100644
--- a/cpu/mpc8260/serial_scc.c
+++ b/cpu/mpc8260/serial_scc.c
@@ -32,6 +32,8 @@
 #include <mpc8260.h>
 #include <asm/cpm_8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_CONS_ON_SCC)
 
 #if CONFIG_CONS_INDEX == 1	/* Console on SCC1 */
@@ -181,8 +183,6 @@ int serial_init (void)
 void
 serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 #if defined(CONFIG_CONS_USE_EXTC)
 	m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate,
 		CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
diff --git a/cpu/mpc8260/serial_smc.c b/cpu/mpc8260/serial_smc.c
index b486f83..f3dffeb 100644
--- a/cpu/mpc8260/serial_smc.c
+++ b/cpu/mpc8260/serial_smc.c
@@ -34,6 +34,8 @@
 #include <mpc8260.h>
 #include <asm/cpm_8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_CONS_ON_SMC)
 
 #if CONFIG_CONS_INDEX == 1	/* Console on SMC1 */
@@ -170,8 +172,6 @@ int serial_init (void)
 void
 serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 #if defined(CONFIG_CONS_USE_EXTC)
 	m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate,
 		CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c
index 99afe76..360404f 100644
--- a/cpu/mpc8260/speed.c
+++ b/cpu/mpc8260/speed.c
@@ -25,6 +25,8 @@
 #include <mpc8260.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /* Bus-to-Core Multiplier */
@@ -101,8 +103,6 @@ corecnf_t corecnf_tab[] = {
 
 int get_clocks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	ulong clkin;
 	ulong sccr, dfbrg;
@@ -159,8 +159,6 @@ int get_clocks (void)
 
 int prt_8260_clks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	ulong sccr, dfbrg;
 	ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf;
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index f24d3a4..20bba6c 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -38,10 +38,11 @@
 #include <ft_build.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 
 int checkcpu(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	ulong clock = gd->cpu_clk;
 	u32 pvr = get_pvr();
 	char buf[32];
@@ -138,8 +139,6 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 unsigned long get_tbclk(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	ulong tbclk;
 
 	tbclk = (gd->bus_clk + 3L) / 4L;
@@ -261,7 +260,7 @@ int dma_xfer(void *dest, u32 count, void *src)
 	dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
 			DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
 			DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
-	
+
 	dma->dmamr0 = swab32(dmamr0);
 
 	__asm__ __volatile__ ("sync");
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index acf6862..6ed0992 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -29,6 +29,8 @@
 #include <mpc83xx.h>
 #include <ioports.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Breathe some life into the CPU...
  *
@@ -38,8 +40,6 @@
  */
 void cpu_init_f (volatile immap_t * im)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 
diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c
index dfd51c1..5a0babf 100644
--- a/cpu/mpc83xx/interrupts.c
+++ b/cpu/mpc83xx/interrupts.c
@@ -35,6 +35,8 @@
 #include <mpc83xx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 struct irq_action {
 	interrupt_handler_t *handler;
 	void *arg;
@@ -43,8 +45,6 @@ struct irq_action {
 
 int interrupt_init_cpu (unsigned *decrementer_count)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *) CFG_IMMRBAR;
 
 	*decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index b4012a8..48624fe 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -1,7 +1,7 @@
 /*
  * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * 
+ *
  * Copyright 2004 Freescale Semiconductor.
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
@@ -426,7 +426,7 @@ static __inline__ unsigned long get_tbms (void)
 /*
  * Initialize all of memory for ECC, then enable errors.
  */
-//#define CONFIG_DDR_ECC_INIT_VIA_DMA
+/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
 void ddr_enable_ecc(unsigned int dram_size)
 {
 	uint *p;
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 1368fc3..ad6b3f6 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -32,6 +32,8 @@
 #include <mpc83xx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ----------------------------------------------------------------- */
 
 typedef enum {
@@ -92,7 +94,6 @@ corecnf_t corecnf_tab[] = {
  */
 int get_clocks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
 	u32 pci_sync_in;
 	u8  spmf;
@@ -342,14 +343,11 @@ int get_clocks (void)
  *********************************************/
 ulong get_bus_freq (ulong dummy)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	return gd->csb_clk;
 }
 
 int print_clock_conf (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	printf("Clock configuration:\n");
 	printf("  Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
 	printf("  Core:                %4d MHz\n",gd->core_clk/1000000);
diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c
index c7a5638..44345af 100644
--- a/cpu/mpc83xx/traps.c
+++ b/cpu/mpc83xx/traps.c
@@ -40,6 +40,8 @@
 #include <asm/processor.h>
 #include <asm/mpc8349_pci.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Returns 0 if exception not found and fixup otherwise.  */
 extern unsigned long search_exception_table(unsigned long);
 
@@ -52,7 +54,6 @@ extern unsigned long search_exception_table(unsigned long);
 void
 print_backtrace(unsigned long *sp)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int cnt = 0;
 	unsigned long i;
 
diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c
index aa8a5a5..3504d50 100644
--- a/cpu/mpc85xx/commproc.c
+++ b/cpu/mpc85xx/commproc.c
@@ -24,6 +24,8 @@
 #include <common.h>
 #include <asm/cpm_85xx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_CPM2)
 /*
  * because we have stack and init data in dual port ram
@@ -35,8 +37,6 @@
 void
 m8560_cpm_reset(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *)CFG_IMMR;
 	volatile ulong count;
 
@@ -64,8 +64,6 @@ m8560_cpm_reset(void)
 uint
 m8560_cpm_dpalloc(uint size, uint align)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *)CFG_IMMR;
 	uint	retloc;
 	uint	align_mask, off;
@@ -122,8 +120,6 @@ m8560_cpm_hostalloc(uint size, uint align)
 void
 m8560_cpm_setbrg(uint brg, uint rate)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *)CFG_IMMR;
 	volatile uint	*bp;
 
@@ -146,8 +142,6 @@ m8560_cpm_setbrg(uint brg, uint rate)
 void
 m8560_cpm_fastbrg(uint brg, uint rate, int div16)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *)CFG_IMMR;
 	volatile uint	*bp;
 
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index efde9cc..c12b47b 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -30,6 +30,8 @@
 #include <ioports.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_CPM2
 static void config_8560_ioports (volatile immap_t * immr)
 {
@@ -103,7 +105,6 @@ static void config_8560_ioports (volatile immap_t * immr)
 
 void cpu_init_f (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
 	volatile ccsr_lbc_t *memctl = &immap->im_lbc;
 	extern void m8560_cpm_reset (void);
diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c
index cf060d6..4e925f8 100644
--- a/cpu/mpc85xx/serial_scc.c
+++ b/cpu/mpc85xx/serial_scc.c
@@ -35,6 +35,8 @@
 #include <common.h>
 #include <asm/cpm_85xx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_CPM2)
 #if defined(CONFIG_CONS_ON_SCC)
 
@@ -186,8 +188,6 @@ int serial_init (void)
 void
 serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 #if defined(CONFIG_CONS_USE_EXTC)
 	m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
 		CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index d736742..ca81ee7 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -29,6 +29,8 @@
 #include <ppc_asm.tmpl>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* --------------------------------------------------------------- */
 
 void get_sys_info (sys_info_t * sysInfo)
@@ -80,7 +82,6 @@ void get_sys_info (sys_info_t * sysInfo)
 
 int get_clocks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	sys_info_t sys_info;
 #if defined(CONFIG_CPM2)
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c
index a87eed2..904f052 100644
--- a/cpu/mpc85xx/traps.c
+++ b/cpu/mpc85xx/traps.c
@@ -39,6 +39,8 @@
 #include <command.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 int (*debugger_exception_handler)(struct pt_regs *) = 0;
 #endif
@@ -83,7 +85,6 @@ extern void do_bedbug_breakpoint(struct pt_regs *);
 void
 print_backtrace(unsigned long *sp)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int cnt = 0;
 	unsigned long i;
 
diff --git a/cpu/mpc8xx/commproc.c b/cpu/mpc8xx/commproc.c
index 75740e0..07c763c 100644
--- a/cpu/mpc8xx/commproc.c
+++ b/cpu/mpc8xx/commproc.c
@@ -24,12 +24,12 @@
 #include <common.h>
 #include <commproc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CFG_ALLOC_DPRAM
 
 int dpram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* Reclaim the DP memory for our use. */
 	gd->dp_alloc_base = CPM_DATAONLY_BASE;
 	gd->dp_alloc_top  = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE;
@@ -43,7 +43,6 @@ int dpram_init (void)
  */
 uint dpram_alloc (uint size)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	uint addr = gd->dp_alloc_base;
 
 	if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top)
@@ -56,8 +55,6 @@ uint dpram_alloc (uint size)
 
 uint dpram_base (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	return gd->dp_alloc_base;
 }
 
@@ -67,8 +64,6 @@ uint dpram_base (void)
  */
 uint dpram_alloc_align (uint size, uint align)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	uint addr, mask = align - 1;
 
 	addr = (gd->dp_alloc_base + mask) & ~mask;
@@ -83,8 +78,6 @@ uint dpram_alloc_align (uint size, uint align)
 
 uint dpram_base_align (uint align)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	uint mask = align - 1;
 
 	return (gd->dp_alloc_base + mask) & ~mask;
diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c
index c4a0cba..97112f0 100644
--- a/cpu/mpc8xx/cpu.c
+++ b/cpu/mpc8xx/cpu.c
@@ -39,6 +39,8 @@
 #include <mpc8xx.h>
 #include <asm/cache.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static char *cpu_warning = "\n         " \
 	"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
 
@@ -349,8 +351,6 @@ static int check_CPU (long clock, uint pvr, uint immr)
 
 int checkcpu (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	ulong clock = gd->cpu_clk;
 	uint immr = get_immr (0);	/* Return full IMMR contents */
 	uint pvr = get_pvr ();
@@ -539,8 +539,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  */
 unsigned long get_tbclk (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	uint immr = get_immr (0);	/* Return full IMMR contents */
 	volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
 	ulong oscclk, factor, pll;
diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c
index b2c59c6..1a7111f 100644
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -27,6 +27,10 @@
 #include <mpc8xx.h>
 #include <commproc.h>
 
+#if defined(CFG_RTCSC) || defined(CFG_RMDS)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 #if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
 void cpm_load_patch (volatile immap_t * immr);
 #endif
@@ -259,8 +263,6 @@ void cpu_init_f (volatile immap_t * immr)
 int cpu_init_r (void)
 {
 #if defined(CFG_RTCSC) || defined(CFG_RMDS)
-	DECLARE_GLOBAL_DATA_PTR;
-
 	bd_t *bd = gd->bd;
 	volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
 #endif
diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index d2f5d88..6006478 100644
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -27,6 +27,8 @@
 #include <net.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef	ET_DEBUG
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET) && \
@@ -371,7 +373,6 @@ static inline void fec_half_duplex(struct eth_device *dev)
 
 static void fec_pin_init(int fecidx)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	bd_t           *bd = gd->bd;
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 	volatile fec_t *fecp;
diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c
index 682db53..6c59374 100644
--- a/cpu/mpc8xx/i2c.c
+++ b/cpu/mpc8xx/i2c.c
@@ -37,6 +37,8 @@
 #include <watchdog.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* define to enable debug messages */
 #undef	DEBUG_I2C
 
@@ -205,8 +207,6 @@ i2c_setrate (int hz, int speed)
 void
 i2c_init(int speed, int slaveaddr)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immap = (immap_t *)CFG_IMMR ;
 	volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 	volatile i2c8xx_t *i2c	= (i2c8xx_t *)&immap->im_i2c;
@@ -615,8 +615,6 @@ int i2c_probe(uchar chip)
 
 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	i2c_state_t state;
 	uchar xaddr[4];
 	int rc;
@@ -671,8 +669,6 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 
 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	i2c_state_t state;
 	uchar xaddr[4];
 	int rc;
diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c
index fa0405f..26a82cc 100644
--- a/cpu/mpc8xx/serial.c
+++ b/cpu/mpc8xx/serial.c
@@ -27,6 +27,8 @@
 #include <serial.h>
 #include <watchdog.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if !defined(CONFIG_8xx_CONS_NONE)	/* No Console at all */
 
 #if defined(CONFIG_8xx_CONS_SMC1)	/* Console on SMC1 */
@@ -65,7 +67,6 @@
 
 static void serial_setdivisor(volatile cpm8xx_t *cp)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
 
 	if(divisor/16>0x1000) {
@@ -268,8 +269,6 @@ smc_putc(const char c)
 	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
 
 #ifdef CONFIG_MODEM_SUPPORT
-	DECLARE_GLOBAL_DATA_PTR;
-
 	if (gd->be_quiet)
 		return;
 #endif
@@ -553,8 +552,6 @@ scc_putc(const char c)
 	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
 
 #ifdef CONFIG_MODEM_SUPPORT
-	DECLARE_GLOBAL_DATA_PTR;
-
 	if (gd->be_quiet)
 		return;
 #endif
@@ -649,13 +646,11 @@ struct serial_device serial_scc_device =
 #ifdef CONFIG_MODEM_SUPPORT
 void disable_putc(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	gd->be_quiet = 1;
 }
 
 void enable_putc(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	gd->be_quiet = 0;
 }
 #endif
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index f038316..57f91c0 100644
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -25,6 +25,8 @@
 #include <mpc8xx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG)
 
 #define PITC_SHIFT 16
@@ -181,8 +183,6 @@ unsigned long measure_gclk(void)
  */
 int get_clocks (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	uint immr = get_immr (0);	/* Return full IMMR contents */
 	volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
 	uint sccr = immap->im_clkrst.car_sccr;
@@ -238,8 +238,6 @@ static long init_pll_866 (long clk);
  */
 int get_clocks_866 (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 	char		  tmp[64];
 	long		  cpuclk = 0;
@@ -277,8 +275,6 @@ int get_clocks_866 (void)
  */
 int sdram_adjust_866 (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 	long		  mamr;
 
@@ -371,8 +367,6 @@ static long init_pll_866 (long clk)
  */
 int adjust_sdram_tbs_8xx (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 	long		  mamr;
 	long              sccr;
diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c
index ee60477..918de67 100644
--- a/cpu/mpc8xx/video.c
+++ b/cpu/mpc8xx/video.c
@@ -39,6 +39,8 @@
 
 #ifdef CONFIG_VIDEO
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /************************************************************************/
 /* ** DEBUG SETTINGS							*/
 /************************************************************************/
@@ -1164,7 +1166,6 @@ static void *video_logo (void)
 	u16 *screen = video_fb_address, width = VIDEO_COLS;
 #ifdef VIDEO_INFO
 # ifndef CONFIG_FADS
-	DECLARE_GLOBAL_DATA_PTR;
 	char temp[32];
 # endif
 	char info[80];
@@ -1282,8 +1283,6 @@ static int video_init (void *videobase)
 
 int drv_video_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int error, devices = 1;
 
 	device_t videodev;
diff --git a/cpu/nios/serial.c b/cpu/nios/serial.c
index 4bdda25..5ecdc6d 100644
--- a/cpu/nios/serial.c
+++ b/cpu/nios/serial.c
@@ -26,6 +26,8 @@
 #include <watchdog.h>
 #include <nios-io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*------------------------------------------------------------------
  * JTAG acts as the serial port
  *-----------------------------------------------------------------*/
@@ -83,7 +85,6 @@ int serial_init (void) { return (0);}
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned div;
 
 	div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
diff --git a/cpu/nios2/serial.c b/cpu/nios2/serial.c
index 2d08c93..3d76603 100644
--- a/cpu/nios2/serial.c
+++ b/cpu/nios2/serial.c
@@ -27,6 +27,8 @@
 #include <nios2.h>
 #include <nios2-io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*------------------------------------------------------------------
  * JTAG acts as the serial port
  *-----------------------------------------------------------------*/
@@ -93,7 +95,6 @@ int serial_init (void) { return (0);}
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned div;
 
 	div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 947b85e..fad895b 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -77,6 +77,8 @@
 #include <asm/processor.h>
 #include <pci.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
 
 #ifdef CONFIG_PCI
@@ -92,8 +94,6 @@ ushort pmc405_pci_subsys_deviceid(void);
  *-----------------------------------------------------------------------------*/
 void pci_405gp_init(struct pci_controller *hose)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int i, reg_num = 0;
 	bd_t *bd = gd->bd;
 
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index a26533c..0cd72b0 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -37,6 +37,10 @@
 #include <asm/cache.h>
 #include <ppc4xx.h>
 
+#if !defined(CONFIG_405)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 
 #if defined(CONFIG_440)
 #define FREQ_EBC		(sys_info.freqEPB)
@@ -116,7 +120,6 @@ static int do_chip_reset(unsigned long sys0, unsigned long sys1);
 int checkcpu (void)
 {
 #if !defined(CONFIG_405)	/* not used on Xilinx 405 FPGA implementations */
-	DECLARE_GLOBAL_DATA_PTR;
 	uint pvr = get_pvr();
 	ulong clock = gd->cpu_clk;
 	char buf[32];
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 79cfba3..1a139d7 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -27,6 +27,10 @@
 #include <asm/processor.h>
 #include <ppc4xx.h>
 
+#if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 
 #define mtebc(reg, data)  mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
 
@@ -209,8 +213,6 @@ cpu_init_f (void)
 int cpu_init_r (void)
 {
 #if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
-	DECLARE_GLOBAL_DATA_PTR;
-
 	bd_t *bd = gd->bd;
 	unsigned long reg;
 #if defined(CONFIG_405GP)
diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
index be94b57..7db1cd8 100644
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -16,6 +16,8 @@
 
 #ifdef CONFIG_HARD_I2C
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define IIC_OK		0
 #define IIC_NOK		1
 #define IIC_NOK_LA	2		/* Lost arbitration */
@@ -350,7 +352,6 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
 {
 	uchar xaddr[4];
 	int ret;
-	DECLARE_GLOBAL_DATA_PTR;
 
 	if ( alen > 4 ) {
 		printf ("I2C read: addr len %d not supported\n", alen);
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 1d8dc7c..3aae4ce 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -36,6 +36,8 @@
 #include <commproc.h>
 #include "vecnum.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /****************************************************************************/
 
 /*
@@ -96,8 +98,6 @@ static __inline__ void set_evpr(unsigned long val)
 
 int interrupt_init_cpu (unsigned *decrementer_count)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int vec;
 	unsigned long val;
 
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index e9548cd..e31d59d 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -1,7 +1,10 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2006
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
+ * (C) Copyright 2006
+ * DAVE Srl <www.dave-tech.it>
+ *
  * (C) Copyright 2002-2004
  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  *
@@ -15,7 +18,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -27,63 +30,161 @@
 #include <common.h>
 #include <ppc4xx.h>
 #include <asm/processor.h>
+#include "sdram.h"
 
 
 #ifdef CONFIG_SDRAM_BANK0
 
 
-#define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
-
-
-struct sdram_conf_s {
-	unsigned long size;
-	unsigned long reg;
-};
-
-typedef struct sdram_conf_s sdram_conf_t;
-
 #ifndef CFG_SDRAM_TABLE
 sdram_conf_t mb0cf[] = {
-	{(128 << 20), 0x000A4001},      /* (0-128MB) Address Mode 3, 13x10(4) */
-	{(64 << 20),  0x00084001},      /* (0-64MB) Address Mode 3, 13x9(4)   */
-	{(32 << 20),  0x00062001},      /* (0-32MB) Address Mode 2, 12x9(4)   */
-	{(16 << 20),  0x00046001},      /* (0-16MB) Address Mode 4, 12x8(4)   */
-	{(4 << 20),   0x00008001},      /* (0-4MB) Address Mode 5, 11x8(2)    */
+	{(128 << 20), 13, 0x000A4001},	    /* (0-128MB) Address Mode 3, 13x10(4) */
+	{(64 << 20),  13, 0x00084001},	    /* (0-64MB) Address Mode 3, 13x9(4)	  */
+	{(32 << 20),  12, 0x00062001},	    /* (0-32MB) Address Mode 2, 12x9(4)	  */
+	{(16 << 20),  12, 0x00046001},	    /* (0-16MB) Address Mode 4, 12x8(4)	  */
+	{(4 << 20),   11, 0x00008001},	    /* (0-4MB) Address Mode 5, 11x8(2)	  */
 };
 #else
 sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
 #endif
 
-#define	N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
 
 
 #ifndef CONFIG_440
 
-/*
- * Autodetect onboard SDRAM on 405 platforms
- */
-void sdram_init(void)
+#ifdef CFG_SDRAM_CASL
+static ulong ns2clks(ulong ns)
 {
-	ulong sdtr1;
-	ulong rtr;
-	int i;
+	ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
 
+	return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
+}
+#endif /* CFG_SDRAM_CASL */
+
+static ulong compute_sdtr1(ulong speed)
+{
+#ifdef CFG_SDRAM_CASL
+	ulong tmp;
+	ulong sdtr1 = 0;
+
+	/* CASL */
+	if (CFG_SDRAM_CASL < 2)
+		sdtr1 |= (1 << SDRAM0_TR_CASL);
+	else
+		if (CFG_SDRAM_CASL > 4)
+			sdtr1 |= (3 << SDRAM0_TR_CASL);
+		else
+			sdtr1 |= ((CFG_SDRAM_CASL-1) << SDRAM0_TR_CASL);
+
+	/* PTA */
+	tmp = ns2clks(CFG_SDRAM_PTA);
+	if ((tmp >= 2) && (tmp <= 4))
+		sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA);
+	else
+		sdtr1 |= ((4-1) << SDRAM0_TR_PTA);
+
+	/* CTP */
+	tmp = ns2clks(CFG_SDRAM_CTP);
+	if ((tmp >= 2) && (tmp <= 4))
+		sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP);
+	else
+		sdtr1 |= ((4-1) << SDRAM0_TR_CTP);
+
+	/* LDF */
+	tmp = ns2clks(CFG_SDRAM_LDF);
+	if ((tmp >= 2) && (tmp <= 4))
+		sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF);
+	else
+		sdtr1 |= ((2-1) << SDRAM0_TR_LDF);
+
+	/* RFTA */
+	tmp = ns2clks(CFG_SDRAM_RFTA);
+	if ((tmp >= 4) && (tmp <= 10))
+		sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA);
+	else
+		sdtr1 |= ((10-4) << SDRAM0_TR_RFTA);
+
+	/* RCD */
+	tmp = ns2clks(CFG_SDRAM_RCD);
+	if ((tmp >= 2) && (tmp <= 4))
+		sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD);
+	else
+		sdtr1 |= ((4-1) << SDRAM0_TR_RCD);
+
+	return sdtr1;
+#else /* CFG_SDRAM_CASL */
 	/*
-	 * Support for 100MHz and 133MHz SDRAM
+	 * If no values are configured in the board config file
+	 * use the default values, which seem to be ok for most
+	 * boards.
+	 *
+	 * REMARK:
+	 * For new board ports we strongly recommend to define the
+	 * correct values for the used SDRAM chips in your board
+	 * config file (see PPChameleonEVB.h)
 	 */
-	if (get_bus_freq(0) > 100000000) {
+	if (speed > 100000000) {
 		/*
 		 * 133 MHz SDRAM
 		 */
-		sdtr1 = 0x01074015;
-		rtr = 0x07f00000;
+		return 0x01074015;
 	} else {
 		/*
 		 * default: 100 MHz SDRAM
 		 */
-		sdtr1 = 0x0086400d;
-		rtr = 0x05f00000;
+		return 0x0086400d;
 	}
+#endif /* CFG_SDRAM_CASL */
+}
+
+/* refresh is expressed in ms */
+static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
+{
+#ifdef CFG_SDRAM_CASL
+	ulong tmp;
+
+	tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000);
+	tmp /= 1000000;
+
+	return ((tmp & 0x00003FF8) << 16);
+#else /* CFG_SDRAM_CASL */
+	if (speed > 100000000) {
+		/*
+		 * 133 MHz SDRAM
+		 */
+		return 0x07f00000;
+	} else {
+		/*
+		 * default: 100 MHz SDRAM
+		 */
+		return 0x05f00000;
+	}
+#endif /* CFG_SDRAM_CASL */
+}
+
+/*
+ * Autodetect onboard SDRAM on 405 platforms
+ */
+void sdram_init(void)
+{
+	ulong speed;
+	ulong sdtr1;
+	int i;
+
+	/*
+	 * Determine SDRAM speed
+	 */
+	speed = get_bus_freq(0); /* parameter not used on ppc4xx */
+
+	/*
+	 * sdtr1 (register SDRAM0_TR) must take into account timings listed
+	 * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
+	 * account actual SDRAM size. So we can set up sdtr1 according to what
+	 * is specified in board configuration file while rtr dependds on SDRAM
+	 * size we are assuming before detection.
+	 */
+	sdtr1 = compute_sdtr1(speed);
 
 	for (i=0; i<N_MB0CF; i++) {
 		/*
@@ -96,7 +197,7 @@ void sdram_init(void)
 		 */
 		mtsdram0(mem_mb0cf, mb0cf[i].reg);
 		mtsdram0(mem_sdtr1, sdtr1);
-		mtsdram0(mem_rtr, rtr);
+		mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
 
 		udelay(200);
 
@@ -120,16 +221,135 @@ void sdram_init(void)
 
 #else /* CONFIG_440 */
 
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+static void sdram_tr1_set(int ram_address, int* tr1_value)
+{
+	int i;
+	int j, k;
+	volatile unsigned int* ram_pointer = (unsigned int *)ram_address;
+	int first_good = -1, last_bad = 0x1ff;
+
+	unsigned long test[NUM_TRIES] = {
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
+
+	/* go through all possible SDRAM0_TR1[RDCT] values */
+	for (i=0; i<=0x1ff; i++) {
+		/* set the current value for TR1 */
+		mtsdram(mem_tr1, (0x80800800 | i));
+
+		/* write values */
+		for (j=0; j<NUM_TRIES; j++) {
+			ram_pointer[j] = test[j];
+
+			/* clear any cache at ram location */
+			__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+		}
+
+		/* read values back */
+		for (j=0; j<NUM_TRIES; j++) {
+			for (k=0; k<NUM_READS; k++) {
+				/* clear any cache at ram location */
+				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+
+				if (ram_pointer[j] != test[j])
+					break;
+			}
+
+			/* read error */
+			if (k != NUM_READS)
+				break;
+		}
+
+		/* we have a SDRAM0_TR1[RDCT] that is part of the window */
+		if (j == NUM_TRIES) {
+			if (first_good == -1)
+				first_good = i;		/* found beginning of window */
+		} else { /* bad read */
+			/* if we have not had a good read then don't care */
+			if (first_good != -1) {
+				/* first failure after a good read */
+				last_bad = i-1;
+				break;
+			}
+		}
+	}
+
+	/* return the current value for TR1 */
+	*tr1_value = (first_good + last_bad) / 2;
+}
+
+
+#ifdef CONFIG_SDRAM_ECC
+static void ecc_init(ulong start, ulong size)
+{
+	ulong	current_addr;		/* current byte address */
+	ulong	end_addr;		/* end of memory region */
+	ulong	addr_inc;		/* address skip between writes */
+	ulong	cfg0_reg;		/* for restoring ECC state */
+
+	/*
+	 * TODO: Enable dcache before running this test (speedup)
+	 */
+
+	mfsdram(mem_cfg0, cfg0_reg);
+	mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN);
+
+	/*
+	 * look at geometry of SDRAM (data width) to determine whether we
+	 * can skip words when writing
+	 */
+	if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32)
+		addr_inc = 4;
+	else
+		addr_inc = 8;
+
+	current_addr = start;
+	end_addr = start + size;
+
+	while (current_addr < end_addr) {
+		*((ulong *)current_addr) = 0x00000000;
+		current_addr += addr_inc;
+	}
+
+	/*
+	 * TODO: Flush dcache and disable it again
+	 */
+
+	/*
+	 * Enable ecc checking and parity errors
+	 */
+	mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK);
+}
+#endif
+
 /*
  * Autodetect onboard DDR SDRAM on 440 platforms
  *
  * NOTE: Some of the hardcoded values are hardware dependant,
- *       so this should be extended for other future boards
- *       using this routine!
+ *	 so this should be extended for other future boards
+ *	 using this routine!
  */
 long int initdram(int board_type)
 {
 	int i;
+	int tr1_bank1;
 
 	for (i=0; i<N_MB0CF; i++) {
 		/*
@@ -140,11 +360,11 @@ long int initdram(int board_type)
 		/*
 		 * Setup some default
 		 */
-		mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */
-		mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
+		mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)		*/
+		mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0		*/
 		mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal)		*/
 		mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0		*/
-		mtsdram(mem_clktr, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0    */
+		mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0	*/
 
 		/*
 		 * Following for CAS Latency = 2.5 @ 133 MHz PLB
@@ -159,11 +379,21 @@ long int initdram(int board_type)
 		/*
 		 * Enable the controller, then wait for DCEN to complete
 		 */
-		mtsdram(mem_cfg0, 0x86000000);	/* DCEN=1, PMUD=1, 64-bit       */
+		mtsdram(mem_cfg0, 0x86000000);	/* DCEN=1, PMUD=1, 64-bit	*/
 		udelay(10000);
 
 		if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
 			/*
+			 * Optimize TR1 to current hardware environment
+			 */
+			sdram_tr1_set(0x00000000, &tr1_bank1);
+			mtsdram(mem_tr1, (tr1_bank1 | 0x80800800));
+
+#ifdef CONFIG_SDRAM_ECC
+			ecc_init(0, mb0cf[i].size);
+#endif
+
+			/*
 			 * OK, size detected -> all done
 			 */
 			return mb0cf[i].size;
diff --git a/cpu/ppc4xx/sdram.h b/cpu/ppc4xx/sdram.h
new file mode 100644
index 0000000..62b5442
--- /dev/null
+++ b/cpu/ppc4xx/sdram.h
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * DAVE Srl <www.dave-tech.it>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SDRAM_H_
+#define _SDRAM_H_
+
+#include <config.h>
+
+#define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
+
+#define ONE_BILLION	1000000000
+
+struct sdram_conf_s {
+	unsigned long size;
+	int rows;
+	unsigned long reg;
+};
+
+typedef struct sdram_conf_s sdram_conf_t;
+
+/* Bitfields offsets */
+#define SDRAM0_TR_CASL		(31 - 8)
+#define SDRAM0_TR_PTA		(31 - 13)
+#define SDRAM0_TR_CTP		(31 - 15)
+#define SDRAM0_TR_LDF		(31 - 17)
+#define SDRAM0_TR_RFTA		(31 - 29)
+#define SDRAM0_TR_RCD		(31 - 31)
+
+#ifdef CFG_SDRAM_CL
+/* SDRAM timings [ns] according to AMCC/IBM names (see SDRAM_faq.doc) */
+#define CFG_SDRAM_CASL		CFG_SDRAM_CL
+#define CFG_SDRAM_PTA		CFG_SDRAM_tRP
+#define CFG_SDRAM_CTP		(CFG_SDRAM_tRC - CFG_SDRAM_tRCD - CFG_SDRAM_tRP)
+#define CFG_SDRAM_LDF		0
+#ifdef CFG_SDRAM_tRFC
+#define CFG_SDRAM_RFTA		CFG_SDRAM_tRFC
+#else
+#define CFG_SDRAM_RFTA		CFG_SDRAM_tRC
+#endif
+#define CFG_SDRAM_RCD		CFG_SDRAM_tRCD
+#endif /* #ifdef CFG_SDRAM_CL */
+
+/*
+ * Some defines for the 440 DDR controller
+ */
+#define SDRAM_CFG0_DC_EN	0x80000000	/* SDRAM Controller Enable	*/
+#define SDRAM_CFG0_MEMCHK	0x30000000	/* Memory data error checking mask*/
+#define SDRAM_CFG0_MEMCHK_NON	0x00000000	/* No ECC generation		*/
+#define SDRAM_CFG0_MEMCHK_GEN	0x20000000	/* ECC generation		*/
+#define SDRAM_CFG0_MEMCHK_CHK	0x30000000	/* ECC generation and checking	*/
+#define SDRAM_CFG0_DRAMWDTH	0x02000000	/* DRAM width mask		*/
+#define SDRAM_CFG0_DRAMWDTH_32	0x00000000	/* 32 bits			*/
+#define SDRAM_CFG0_DRAMWDTH_64	0x02000000	/* 64 bits			*/
+
+#endif
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index e7f6bcb..83c9479 100644
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -59,6 +59,8 @@
 #include <malloc.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*****************************************************************************/
 #ifdef CONFIG_IOP480
 
@@ -161,8 +163,6 @@
 
 int serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile char val;
 	unsigned short br_reg;
 
@@ -185,8 +185,6 @@ int serial_init (void)
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned short br_reg;
 
 	br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
@@ -431,8 +429,6 @@ int serial_init_dev (unsigned long dev_base)
 int serial_init(void)
 #endif
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned long reg;
 	unsigned long udiv;
 	unsigned short bdiv;
@@ -520,8 +516,6 @@ int serial_init_dev (unsigned long dev_base)
 int serial_init (void)
 #endif
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned long reg;
 	unsigned long tmp;
 	unsigned long clk;
@@ -597,8 +591,6 @@ void serial_setbrg_dev (unsigned long dev_base)
 void serial_setbrg (void)
 #endif
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned long tmp;
 	unsigned long clk;
 	unsigned long udiv;
@@ -880,8 +872,6 @@ int serial_buffered_tstc (void)
 #if (CONFIG_KGDB_SER_INDEX & 2)
 void kgdb_serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile char val;
 	unsigned short br_reg;
 
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 553c491..02b4383 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -26,7 +26,7 @@
 #include <ppc4xx.h>
 #include <asm/processor.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 #define ONE_BILLION        1000000000
 
@@ -522,8 +522,6 @@ ulong get_PCI_freq (void)
 int get_clocks (void)
 {
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
-	DECLARE_GLOBAL_DATA_PTR;
-
 	sys_info_t sys_info;
 
 	get_sys_info (&sys_info);
@@ -533,8 +531,6 @@ int get_clocks (void)
 #endif	/* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
 
 #ifdef CONFIG_IOP480
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->cpu_clk = 66000000;
 	gd->bus_clk = 66000000;
 #endif
diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index b33d674..0ee8180 100644
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -34,14 +34,16 @@
 #include <command.h>
 #include <asm/arch/pxa-regs.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 int cpu_init (void)
 {
 	/*
 	 * setup up stacks if necessary
 	 */
 #ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
 	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c
index b6155b1..722d949 100644
--- a/cpu/pxa/i2c.c
+++ b/cpu/pxa/i2c.c
@@ -47,7 +47,13 @@
 
 /*#define	DEBUG_I2C 	1	/###* activate local debugging output  */
 #define I2C_PXA_SLAVE_ADDR	0x1	/* slave pxa unit address           */
-#define I2C_ICR_INIT		(ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+
+#if (CFG_I2C_SPEED == 400000)
+#define I2C_ICR_INIT	(ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+#else
+#define I2C_ICR_INIT	(ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+#endif
+
 #define I2C_ISR_INIT		0x7FF
 
 #ifdef DEBUG_I2C
@@ -91,7 +97,11 @@ static void i2c_reset( void )
 	ICR |= ICR_UR;			/* reset the unit */
 	udelay(100);
 	ICR &= ~ICR_IUE;		/* disable unit */
+#ifdef CONFIG_CPU_MONAHANS
+	CKENB |= (CKENB_4_I2C); /*  | CKENB_1_PWM1 | CKENB_0_PWM0); */
+#else /* CONFIG_CPU_MONAHANS */
 	CKEN |= CKEN14_I2C;		/* set the global I2C clock on */
+#endif
 	ISAR = I2C_PXA_SLAVE_ADDR;	/* set our slave address */
 	ICR = I2C_ICR_INIT;		/* set control register values */
 	ISR = I2C_ISR_INIT;		/* set clear interrupt bits */
@@ -104,9 +114,8 @@ static void i2c_reset( void )
  * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
  *	                  are set and cleared
  *
- * @return: 0 in case of success, 1 means timeout (no match within 10 ms).
+ * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
  */
-
 static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask )
 {
 	int timeout = 10000;
@@ -360,9 +369,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 		msg.data      = 0x00;
 		if ((ret=i2c_transfer(&msg))) return -1;
 
-		*(buffer++) = msg.data;
-
+		*buffer = msg.data;
 		PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
+		buffer++;
 
 	}
 
diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c
index 9bf2a7c..cb3a478 100644
--- a/cpu/pxa/serial.c
+++ b/cpu/pxa/serial.c
@@ -32,10 +32,10 @@
 #include <watchdog.h>
 #include <asm/arch/pxa-regs.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned int quot = 0;
 
 	if (gd->baudrate == 1200)
diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S
index 9541c9b..ffaa30f 100644
--- a/cpu/pxa/start.S
+++ b/cpu/pxa/start.S
@@ -190,6 +190,14 @@ OSTIMER_BASE:	.word	0x40a00000
 #define OIER	0x1C
 
 /* Clock Manager Registers						    */
+#ifdef CONFIG_CPU_MONAHANS
+# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
+#  error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
+# endif
+# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
+#  define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
+# endif
+#else /* ! CONFIG_CPU_MONAHANS */
 #ifdef CFG_CPUSPEED
 CC_BASE:	.word	0x41300000
 #define CCCR	0x00
@@ -197,6 +205,7 @@ cpuspeed:	.word	CFG_CPUSPEED
 #else
 #error "You have to define CFG_CPUSPEED!!"
 #endif
+#endif /* CONFIG_CPU_MONAHANS */
 
 	/* takes care the CP15 update has taken place */
 	.macro CPWAIT reg
@@ -233,9 +242,13 @@ cpu_init_crit:
 	str	r2, [r1]
 #endif
 
-#ifndef CONFIG_CPU_MONAHANS
+	/* set clock speed */
+#ifdef CONFIG_CPU_MONAHANS
+	ldr	r0, =ACCR
+	ldr	r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
+	str	r1, [r0]
+#else /* ! CONFIG_CPU_MONAHANS */
 #ifdef CFG_CPUSPEED
-	/* set clock speed tbd@mk: required for monahans? */
 	ldr	r0, CC_BASE
 	ldr	r1, cpuspeed
 	str	r1, [r0, #CCCR]
diff --git a/cpu/s3c44b0/serial.c b/cpu/s3c44b0/serial.c
index 70b4ee8..95d0266 100644
--- a/cpu/s3c44b0/serial.c
+++ b/cpu/s3c44b0/serial.c
@@ -37,6 +37,8 @@
 #include <common.h>
 #include <asm/hardware.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* flush serial input queue. returns 0 on success or negative error
  * number otherwise
  */
@@ -68,8 +70,6 @@ static int serial_flush_output(void)
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	u32 divisor = 0;
 
 	/* get correct divisor */
diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c
index 17e5b0d..f1bd644 100644
--- a/cpu/sa1100/cpu.c
+++ b/cpu/sa1100/cpu.c
@@ -33,14 +33,16 @@
 #include <common.h>
 #include <command.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 int cpu_init (void)
 {
 	/*
 	 * setup up stacks if necessary
 	 */
 #ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
 	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
diff --git a/cpu/sa1100/serial.c b/cpu/sa1100/serial.c
index a598489..5d18875 100644
--- a/cpu/sa1100/serial.c
+++ b/cpu/sa1100/serial.c
@@ -31,10 +31,10 @@
 #include <common.h>
 #include <SA-1100.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned int reg = 0;
 
 	if (gd->baudrate == 1200)