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| author | Stefan Roese <sr@denx.de> | 2008-02-19 22:01:57 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-03-15 07:28:03 +0100 |
| commit | 84a999b6cdd0b02dc7de2cacc306eaa84afe2b46 (patch) | |
| tree | 7d7ab3c7fd14897ebcf028da9572d79614fb05e0 /cpu | |
| parent | c3307fa186af85771924c434997089b8104c0a46 (diff) | |
| download | u-boot-imx-84a999b6cdd0b02dc7de2cacc306eaa84afe2b46.zip u-boot-imx-84a999b6cdd0b02dc7de2cacc306eaa84afe2b46.tar.gz u-boot-imx-84a999b6cdd0b02dc7de2cacc306eaa84afe2b46.tar.bz2 | |
ppc4xx: program_tlb now uses 64bit physical addess
This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB border, like SoC peripherals (EBC etc.).
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/ppc4xx/tlb.c | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c index ed493f1..2bfcba1 100644 --- a/cpu/ppc4xx/tlb.c +++ b/cpu/ppc4xx/tlb.c @@ -31,9 +31,9 @@ #include <asm/mmu.h> typedef struct region { - unsigned long base; - unsigned long size; - unsigned long tlb_word2_i_value; + u64 base; + u32 size; + u32 tlb_word2_i_value; } region_t; void remove_tlb(u32 vaddr, u32 size) @@ -182,10 +182,10 @@ void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value) asm("isync"); } -static int add_tlb_entry(unsigned long phys_addr, - unsigned long virt_addr, - unsigned long tlb_word0_size_value, - unsigned long tlb_word2_i_value) +static int add_tlb_entry(u64 phys_addr, + u32 virt_addr, + u32 tlb_word0_size_value, + u32 tlb_word2_i_value) { int i; unsigned long tlb_word0_value; @@ -204,7 +204,8 @@ static int add_tlb_entry(unsigned long phys_addr, /* Second, create the TLB entry */ tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE | TLB_WORD0_TS_0 | tlb_word0_size_value; - tlb_word1_value = TLB_WORD1_RPN_ENCODE(phys_addr) | TLB_WORD1_ERPN_ENCODE(0); + tlb_word1_value = TLB_WORD1_RPN_ENCODE((u32)phys_addr) | + TLB_WORD1_ERPN_ENCODE(phys_addr >> 32); tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE | TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE | TLB_WORD2_W_DISABLE | tlb_word2_i_value | @@ -228,10 +229,10 @@ static int add_tlb_entry(unsigned long phys_addr, return 0; } -static void program_tlb_addr(unsigned long phys_addr, - unsigned long virt_addr, - unsigned long mem_size, - unsigned long tlb_word2_i_value) +static void program_tlb_addr(u64 phys_addr, + u32 virt_addr, + u32 mem_size, + u32 tlb_word2_i_value) { int rc; int tlb_i; @@ -331,7 +332,7 @@ static void program_tlb_addr(unsigned long phys_addr, * Common usage for boards with SDRAM DIMM modules to dynamically * configure the TLB's for the SDRAM */ -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value) +void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value) { region_t region_array; |