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| author | Sammy He <r62914@freescale.com> | 2010-11-26 22:40:18 +0800 |
|---|---|---|
| committer | Sammy He <r62914@freescale.com> | 2010-11-26 22:42:57 +0800 |
| commit | 7a047737bdd06e9fb44b055ecd8a4cdb27e72711 (patch) | |
| tree | ceb1d11f0762498f6caeba5b4bb868059f4d8d66 /cpu | |
| parent | f9c90ac3717b2907487f559f5227a7dab4675063 (diff) | |
| download | u-boot-imx-7a047737bdd06e9fb44b055ecd8a4cdb27e72711.zip u-boot-imx-7a047737bdd06e9fb44b055ecd8a4cdb27e72711.tar.gz u-boot-imx-7a047737bdd06e9fb44b055ecd8a4cdb27e72711.tar.bz2 | |
ENGR00134098-2 MX53: Add fastboot support for android.
Add fastboot support for mx53 EVK android.
Signed-off-by: Sammy He <r62914@freescale.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm_cortexa8/mx53/generic.c | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c index 6df3820..3d0772d 100644 --- a/cpu/arm_cortexa8/mx53/generic.c +++ b/cpu/arm_cortexa8/mx53/generic.c @@ -1017,3 +1017,54 @@ int arch_cpu_init(void) } #endif +void set_usboh3_clk(void) +{ + unsigned int reg; + + reg = readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; + reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; + writel(reg, MXC_CCM_CSCMR1); + + reg = readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK; + reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET; + reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET; + + writel(reg, MXC_CCM_CSCDR1); +} + +void set_usb_phy1_clk(void) +{ + unsigned int reg; + + reg = readl(MXC_CCM_CSCMR1); + reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + writel(reg, MXC_CCM_CSCMR1); +} + +void enable_usboh3_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(MXC_CCM_CCGR2); + if (enable) + reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET); + writel(reg, MXC_CCM_CCGR2); +} + +void enable_usb_phy1_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(MXC_CCM_CCGR4); + if (enable) + reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET); + writel(reg, MXC_CCM_CCGR4); +} + |