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authorLily Zhang <r58066@freescale.com>2010-10-14 16:42:19 +0800
committerLily Zhang <r58066@freescale.com>2010-10-17 18:04:52 +0800
commit9bbe28258c19c28f8f85c22c932bd119368cfacb (patch)
tree22fe342bd0594f37082c3d5aada765162773b5cc /cpu
parentd63c74683ab6063e0ca363bebe4f1f4b8197be33 (diff)
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ENGR00132617 MX53: add NAND support
Add NAND support for MX53 EVK and ARD. Need to use kobs-ng to flash U-Boot on MX53 TO1. Because MX51 TO1 ROM doesn't support bi swap solution and kernel enable bi swap, Must enable "ignore bad block" option when flashing U-Boot. The step is as following: echo 1 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad kobs-ng init --chip_0_device_path=/dev/mtd2 u-boot.bin echo 0 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad Since default configuration stores environment into SD card and U-Boot uses get_mmc_env_devno (Read SBMR register) to get MMC/SD slot information, you must insert SD card to bottom SD slot to get/store environment if you are using NAND boot on MX53 EVK. You must config boot dip setting well when doing NAND boot. For example, if you are using NAND 29F32G080AA NAND chip on MX53 EVK, you can set boot dips as the following for NAND boot: SW3: dip 7, 8 on; SW2: dip 3,5 on; SW1: dip 4,7,8 on. Other dips are off. Signed-off-by: Lily Zhang <r58066@freescale.com>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/arm_cortexa8/mx53/generic.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c
index d725bde..8904d9d 100644
--- a/cpu/arm_cortexa8/mx53/generic.c
+++ b/cpu/arm_cortexa8/mx53/generic.c
@@ -88,7 +88,7 @@ struct pll_param {
#define MAX_DDR_CLK 420000000
#define AHB_CLK_MAX 133333333
#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
-#define NFC_CLK_MAX 25000000
+#define NFC_CLK_MAX 34000000
#define HSP_CLK_MAX 133333333
#endif
@@ -311,7 +311,6 @@ static u32 __get_emi_slow_clk(void)
return __get_periph_clk() / (pdf + 1);
}
-/*
static u32 __get_nfc_clk(void)
{
u32 cbcdr = __REG(MXC_CCM_CBCDR);
@@ -320,7 +319,6 @@ static u32 __get_nfc_clk(void)
return __get_emi_slow_clk() / (pdf + 1);
}
-*/
static u32 __get_ddr_clk(void)
{
@@ -479,6 +477,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return __get_esdhc4_clk();
case MXC_SATA_CLK:
return __get_ahb_clk();
+ case MXC_NFC_CLK:
+ return __get_nfc_clk();
default:
break;
}
@@ -507,6 +507,7 @@ void mxc_dump_clocks(void)
printf("esdhc2 clock : %dHz\n", mxc_get_clock(MXC_ESDHC2_CLK));
printf("esdhc3 clock : %dHz\n", mxc_get_clock(MXC_ESDHC3_CLK));
printf("esdhc4 clock : %dHz\n", mxc_get_clock(MXC_ESDHC4_CLK));
+ printf("nfc clock : %dHz\n", mxc_get_clock(MXC_NFC_CLK));
}
#ifdef CONFIG_CMD_CLOCK