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| author | Lily Zhang <r58066@freescale.com> | 2010-12-27 14:39:14 +0800 |
|---|---|---|
| committer | Lily Zhang <r58066@freescale.com> | 2010-12-28 10:22:33 +0800 |
| commit | 07ce4f0a2fee112bd3043d162b201abd65a52b6c (patch) | |
| tree | e9368614d8d09a5342668ed355717df630578740 /cpu | |
| parent | 2205133fb6fdea1393933e332ed693d82d922dba (diff) | |
| download | u-boot-imx-07ce4f0a2fee112bd3043d162b201abd65a52b6c.zip u-boot-imx-07ce4f0a2fee112bd3043d162b201abd65a52b6c.tar.gz u-boot-imx-07ce4f0a2fee112bd3043d162b201abd65a52b6c.tar.bz2 | |
ENGR00137372 MX53: Switch back to use DCD and update DDR scripts
1. This patch is used to switch back to use DCD for flash header
instead of plug-in. This change request is due to the following
reasons:
1) U-boot community doesn't accept current plug-in solution when
upstreaming.
2) Plug-in isn't supported by MX53 ROM serial download mode.
No effective workaround is found now. To use the same code
base to support normal U-Boot and MFG tool better, adopt
DCD solution firstly.
3) Current MX53 DDR scripts don't exceed the length limitation
of DCD.
For MX53 TO2.0 EVK/ARM2 board, raise DDR frequency to 400MHZ after
VCC and VDDA voltages are raised as 1.3V.
Since ARM2 CPU2 board share the same script with EVK, delete ARM2
CPU2 config files. ARM2 CPU2 board can share the same bootloader
with EVK.
2. Update MX53 DDR2 scripts for TO1.0/TO2.0 EVK/ARD/ARM2 boards
The script "MX53_TO2_DDR2_EVK_ARD.inc" is located under
http://compass.freescale.net/livelink/livelink?
func=ll&objId=221058910&objAction=browse&viewType=1
This script is published by ATX and FIL team on Dec 16th, 2010
3. Update MX53 ARM2 CPU3 DDR3 script "MX53_TO2_DDR3_CPU3.inc"
under the same compass folder
Signed-off-by: Lily Zhang <r58066@freescale.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm_cortexa8/mx53/generic.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c index 3d0772d..3e3571e 100644 --- a/cpu/arm_cortexa8/mx53/generic.c +++ b/cpu/arm_cortexa8/mx53/generic.c @@ -739,9 +739,13 @@ static int config_pll_clk(enum pll_clocks pll, struct pll_param *pll_param) writel(ccsr & ~0x4, CCM_BASE_ADDR + CLKCTL_CCSR); break; case PLL2_CLK: + /* Switch to pll2 bypass clock */ + writel(ccsr | 0x2, CCM_BASE_ADDR + CLKCTL_CCSR); CHANGE_PLL_SETTINGS(pll_base, pll_param->pd, pll_param->mfi, pll_param->mfn, pll_param->mfd); + /* Switch back */ + writel(ccsr & ~0x2, CCM_BASE_ADDR + CLKCTL_CCSR); break; case PLL3_CLK: /* Switch to pll3 bypass clock */ @@ -842,8 +846,8 @@ static int config_periph_clk(u32 ref, u32 freq) u32 old_nfc = __get_nfc_clk(); /* Switch peripheral to PLL3 */ - writel((old_cbcmr & ~0x3000) | (1 << 12), - CCM_BASE_ADDR + CLKCTL_CBCMR); + writel(0x00015154, CCM_BASE_ADDR + CLKCTL_CBCMR); + writel(0x02888945, CCM_BASE_ADDR + CLKCTL_CBCDR); /* Make sure change is effective */ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0) @@ -859,6 +863,7 @@ static int config_periph_clk(u32 ref, u32 freq) config_pll_clk(PLL2_CLK, &pll_param); /* Switch peripheral back */ + writel(new_cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR); writel(old_cbcmr, CCM_BASE_ADDR + CLKCTL_CBCMR); /* Make sure change is effective */ |