Merge branch 'next' of git://git.denx.de/u-boot-coldfire

13 files changed, 372 insertions, 545 deletions

diff --git a/cpu/mcf5227x/Makefile b/cpu/mcf5227x/Makefile
index 44f9385..d0e9b45 100644
--- a/cpu/mcf5227x/Makefile
+++ b/cpu/mcf5227x/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(CPU).a
 
 START	= start.o
-COBJS	= cpu.o speed.o cpu_init.o interrupts.o dspi.o
+COBJS	= cpu.o speed.o cpu_init.o interrupts.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c
index 8945ef3..d8bcf37 100644
--- a/cpu/mcf5227x/cpu_init.c
+++ b/cpu/mcf5227x/cpu_init.c
@@ -152,3 +152,56 @@ void uart_port_conf(void)
 		break;
 	}
 }
+
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	gpio->par_dspi =
+	    GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+	    GPIO_PAR_DSPI_SCK_SCK;
+}
+
+int cfspi_claim_bus(uint bus, uint cs)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+		return -1;
+
+	/* Clear FIFO and resume transfer */
+	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+
+	switch (cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_MASK;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 2:
+		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+		gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
+		break;
+	}
+
+	return 0;
+}
+
+void cfspi_release_bus(uint bus, uint cs)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);	/* Clear FIFO */
+
+	switch (cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 2:
+		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+		break;
+	}
+}
+#endif
diff --git a/cpu/mcf5227x/dspi.c b/cpu/mcf5227x/dspi.c
deleted file mode 100644
index 7f48f91..0000000
--- a/cpu/mcf5227x/dspi.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <spi.h>
-#include <malloc.h>
-
-#if defined(CONFIG_CF_DSPI)
-#include <asm/immap.h>
-
-void dspi_init(void)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	gpio->par_dspi =
-	    GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
-	    GPIO_PAR_DSPI_SCK_SCK;
-
-	dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
-	    DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
-	    DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
-	    DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
-
-#ifdef CONFIG_SYS_DSPI_DCTAR0
-	dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR1
-	dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR2
-	dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR3
-	dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR4
-	dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR5
-	dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR6
-	dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR7
-	dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
-#endif
-}
-
-void dspi_tx(int chipsel, u8 attrib, u16 data)
-{
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	while ((dspi->dsr & 0x0000F000) >= 4) ;
-
-	dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
-}
-
-u16 dspi_rx(void)
-{
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	while ((dspi->dsr & 0x000000F0) == 0) ;
-
-	return (dspi->drfr & 0xFFFF);
-}
-
-#if defined(CONFIG_CMD_SPI)
-void spi_init_f(void)
-{
-}
-
-void spi_init_r(void)
-{
-}
-
-void spi_init(void)
-{
-	dspi_init();
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-				  unsigned int max_hz, unsigned int mode)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	struct spi_slave *slave;
-
-	slave = malloc(sizeof(struct spi_slave));
-	if (!slave)
-		return NULL;
-
-	switch (cs) {
-	case 0:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
-		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
-		break;
-	case 2:
-		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
-		gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
-		break;
-	}
-
-	slave->bus = bus;
-	slave->cs = cs;
-
-	return slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	switch (slave->cs) {
-	case 0:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
-		break;
-	case 2:
-		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
-		break;
-	}
-
-	free(slave);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-	return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-	     void *din, unsigned long flags)
-{
-	static int bWrite = 0;
-	u8 *spi_rd, *spi_wr;
-	int len = bitlen >> 3;
-
-	spi_rd = (u8 *) din;
-	spi_wr = (u8 *) dout;
-
-	/* command handling */
-	if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
-		switch (*spi_wr) {
-		case 0x02:	/* Page Prog */
-			bWrite = 1;
-			dspi_tx(slave->cs, 0x80, spi_wr[0]);
-			dspi_rx();
-			dspi_tx(slave->cs, 0x80, spi_wr[1]);
-			dspi_rx();
-			dspi_tx(slave->cs, 0x80, spi_wr[2]);
-			dspi_rx();
-			dspi_tx(slave->cs, 0x80, spi_wr[3]);
-			dspi_rx();
-			return 0;
-		case 0x05:	/* Read Status */
-			if (len == 4)
-				if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
-				    && (spi_wr[3] == 0xFF)) {
-					dspi_tx(slave->cs, 0x80, *spi_wr);
-					dspi_rx();
-				}
-			return 0;
-		case 0x06:	/* WREN */
-			dspi_tx(slave->cs, 0x00, *spi_wr);
-			dspi_rx();
-			return 0;
-		case 0x0B:	/* Fast read */
-			if ((len == 5) && (spi_wr[4] == 0)) {
-				dspi_tx(slave->cs, 0x80, spi_wr[0]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[1]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[2]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[3]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[4]);
-				dspi_rx();
-			}
-			return 0;
-		case 0x9F:	/* RDID */
-			dspi_tx(slave->cs, 0x80, *spi_wr);
-			dspi_rx();
-			return 0;
-		case 0xD8:	/* Sector erase */
-			if (len == 4)
-				if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
-					dspi_tx(slave->cs, 0x80, spi_wr[0]);
-					dspi_rx();
-					dspi_tx(slave->cs, 0x80, spi_wr[1]);
-					dspi_rx();
-					dspi_tx(slave->cs, 0x80, spi_wr[2]);
-					dspi_rx();
-					dspi_tx(slave->cs, 0x00, spi_wr[3]);
-					dspi_rx();
-				}
-			return 0;
-		}
-	}
-
-	if (bWrite)
-		len--;
-
-	while (len--) {
-		if (dout != NULL) {
-			dspi_tx(slave->cs, 0x80, *spi_wr);
-			dspi_rx();
-			spi_wr++;
-		}
-
-		if (din != NULL) {
-			dspi_tx(slave->cs, 0x80, 0);
-			*spi_rd = dspi_rx();
-			spi_rd++;
-		}
-	}
-
-	if (flags == SPI_XFER_END) {
-		if (bWrite) {
-			dspi_tx(slave->cs, 0x00, *spi_wr);
-			dspi_rx();
-			bWrite = 0;
-		} else {
-			dspi_tx(slave->cs, 0x00, 0);
-			dspi_rx();
-		}
-	}
-
-	return 0;
-}
-#endif				/* CONFIG_CMD_SPI */
-
-#endif				/* CONFIG_CF_DSPI */
diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk
index 8292736..52751be 100644
--- a/cpu/mcf52x2/config.mk
+++ b/cpu/mcf52x2/config.mk
@@ -26,6 +26,7 @@
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
 
 cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5208:=$(shell grep CONFIG_M5208 $(TOPDIR)/include/$(cfg))
 is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
 is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
 is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
@@ -36,6 +37,9 @@ is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
 
 ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
 
+ifneq (,$(findstring CONFIG_M5208,$(is5208)))
+PLATFORM_CPPFLAGS += -mcpu=5208
+endif
 ifneq (,$(findstring CONFIG_M5249,$(is5249)))
 PLATFORM_CPPFLAGS += -mcpu=5249
 endif
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index 32d6c40..2cfe631 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -34,6 +34,72 @@
 #include <asm/immap.h>
 #include <netdev.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef	CONFIG_M5208
+int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+
+	udelay(1000);
+
+	rcm->rcr = RCM_RCR_SOFTRST;
+
+	/* we don't return! */
+	return 0;
+};
+
+int checkcpu(void)
+{
+	char buf1[32], buf2[32];
+
+	printf("CPU:   Freescale Coldfire MCF5208\n"
+	       "       CPU CLK %s MHz BUS CLK %s MHz\n",
+	       strmhz(buf1, gd->cpu_clk),
+	       strmhz(buf2, gd->bus_clk));
+	return 0;
+};
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdt->sr = 0x5555;
+	wdt->sr = 0xAAAA;
+}
+
+int watchdog_disable(void)
+{
+	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+	wdt->sr = 0x5555; /* reset watchdog counteDECLARE_GLOBAL_DATA_PTR;
+r */
+	wdt->sr = 0xAAAA;
+	wdt->cr = 0;	/* disable watchdog timer */
+
+	puts("WATCHDOG:disabled\n");
+	return (0);
+}
+
+int watchdog_init(void)
+{
+	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+	wdt->cr = 0;	/* disable watchdog */
+
+	/* set timeout and enable watchdog */
+	wdt->mr =
+		((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
+	wdt->sr = 0x5555; /* reset watchdog counter */
+	wdt->sr = 0xAAAA;
+
+	puts("WATCHDOG:enabled\n");
+	return (0);
+}
+#endif				/* #ifdef CONFIG_WATCHDOG */
+#endif				/* #ifdef CONFIG_M5208 */
+
 #ifdef  CONFIG_M5271
 /*
  * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 11f70b0..7cea655 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -101,6 +101,95 @@ void init_fbcs(void)
 }
 #endif
 
+#if defined(CONFIG_M5208)
+void cpu_init_f(void)
+{
+	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+#ifndef CONFIG_WATCHDOG
+	volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+
+	/* Disable the watchdog if we aren't using it */
+	wdg->cr = 0;
+#endif
+
+	scm1->mpr = 0x77777777;
+	scm1->pacra = 0;
+	scm1->pacrb = 0;
+	scm1->pacrc = 0;
+	scm1->pacrd = 0;
+	scm1->pacre = 0;
+	scm1->pacrf = 0;
+
+	/* FlexBus Chipselect */
+	init_fbcs();
+
+	icache_enable();
+}
+
+/* initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (CONFIG_SYS_UART_PORT) {
+	case 0:
+		gpio->par_uart &= GPIO_PAR_UART0_MASK;
+		gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		break;
+	case 1:
+		gpio->par_uart &= GPIO_PAR_UART0_MASK;
+		gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+		break;
+	case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+		gpio->par_timer &=
+		    (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
+		gpio->par_timer |=
+		    (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+		gpio->par_feci2c &=
+		    (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
+		gpio->par_feci2c |=
+		    (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+		gpio->par_feci2c &=
+		    (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+		gpio->par_feci2c |=
+		    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+#endif
+		break;
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		gpio->par_fec |=
+		    GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
+		gpio->par_feci2c |=
+		    GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
+	} else {
+		gpio->par_fec &=
+		    (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK);
+		gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK;
+	}
+	return 0;
+}
+#endif				/* CONFIG_CMD_NET */
+#endif				/* CONFIG_M5208 */
+
 #if defined(CONFIG_M5253)
 /*
  * Breath some life into the CPU...
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c
index 0181e4b..dff8c6a 100644
--- a/cpu/mcf52x2/interrupts.c
+++ b/cpu/mcf52x2/interrupts.c
@@ -59,13 +59,19 @@ void dtimer_intr_setup(void)
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5272 */
 
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
+#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
+    defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
 	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
+#if defined(CONFIG_M5208)
+	intp->imrl0 = 0xFFFFFFFF;
+	intp->imrh0 = 0xFFFFFFFF;
+#else
 	intp->imrl0 |= 0x1;
+#endif
 
 	enable_interrupts();
 	return 0;
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index c93a518..b485e1c 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -30,11 +30,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
 int get_clocks (void)
 {
+#if defined(CONFIG_M5208)
+	volatile pll_t *pll = (pll_t *) MMAP_PLL;
+
+	pll->odr = CONFIG_SYS_PLL_ODR;
+	pll->fdr = CONFIG_SYS_PLL_FDR;
+#endif
+
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
 	unsigned long pllcr;
@@ -77,7 +82,7 @@ int get_clocks (void)
 #endif
 
 	gd->cpu_clk = CONFIG_SYS_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 	gd->bus_clk = gd->cpu_clk / 2;
 #else
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index ba6b884..0dd4de5 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -120,6 +120,12 @@ _start:
 	nop
 	move.w #0x2700,%sr
 
+#if defined(CONFIG_M5208)
+	/* Initialize RAMBAR: locate SRAM and validate it */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+#endif
+
 #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	move.l	#(CONFIG_SYS_MBAR + 1), %d0		/* set MBAR address + valid flag */
 	move.c	%d0, %MBAR
@@ -195,15 +201,6 @@ _after_flashbar_copy:
 	movec	%d0, %RAMBAR1
 #endif
 
-#if 0
-	/* invalidate and disable cache */
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#0, %d0
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-#endif
-
 	/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
@@ -340,6 +337,24 @@ _int_handler:
 
 /*------------------------------------------------------------------------------*/
 /* cache functions */
+#ifdef	CONFIG_M5208
+	.globl	icache_enable
+icache_enable:
+	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0	/* Setup cache mask */
+	movec	%d0, %ACR0			/* Enable cache */
+
+	move.l	#0x80000200, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
+	nop
+
+	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
+	moveq	#1, %d0
+	move.l	%d0, (%a1)
+	rts
+#endif
+
 #ifdef	CONFIG_M5271
 	.globl	icache_enable
 icache_enable:
diff --git a/cpu/mcf5445x/Makefile b/cpu/mcf5445x/Makefile
index a549fdd..26ec298 100644
--- a/cpu/mcf5445x/Makefile
+++ b/cpu/mcf5445x/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(CPU).a
 
 START	= start.o
-COBJS	= cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
+COBJS	= cpu.o speed.o cpu_init.o interrupts.o pci.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index 7e04e32..48b37df 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -171,3 +171,69 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+	    GPIO_PAR_DSPI_SCK_SCK;
+}
+
+int cfspi_claim_bus(uint bus, uint cs)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+		return -1;
+
+	/* Clear FIFO and resume transfer */
+	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+
+	switch (cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 1:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1;
+		break;
+	case 2:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2;
+		break;
+	case 5:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5;
+		break;
+	}
+
+	return 0;
+}
+
+void cfspi_release_bus(uint bus, uint cs)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);	/* Clear FIFO */
+
+	switch (cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 1:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
+		break;
+	case 2:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
+		break;
+	case 5:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
+		break;
+	}
+}
+#endif
diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c
deleted file mode 100644
index 6d3ebab..0000000
--- a/cpu/mcf5445x/dspi.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <spi.h>
-#include <malloc.h>
-
-#if defined(CONFIG_CF_DSPI)
-#include <asm/immap.h>
-
-void dspi_init(void)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 |
-	    GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 |
-	    GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
-	    GPIO_PAR_DSPI_SCK_SCK;
-
-	dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
-	    DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
-	    DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
-	    DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
-
-#ifdef CONFIG_SYS_DSPI_DCTAR0
-	dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR1
-	dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR2
-	dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR3
-	dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR4
-	dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR5
-	dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR6
-	dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR7
-	dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
-#endif
-}
-
-void dspi_tx(int chipsel, u8 attrib, u16 data)
-{
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	while ((dspi->dsr & 0x0000F000) >= 4) ;
-
-	dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
-}
-
-u16 dspi_rx(void)
-{
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	while ((dspi->dsr & 0x000000F0) == 0) ;
-
-	return (dspi->drfr & 0xFFFF);
-}
-
-#if defined(CONFIG_CMD_SPI)
-void spi_init_f(void)
-{
-}
-
-void spi_init_r(void)
-{
-}
-
-void spi_init(void)
-{
-	dspi_init();
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-				  unsigned int max_hz, unsigned int mode)
-{
-	struct spi_slave *slave;
-
-	slave = malloc(sizeof(struct spi_slave));
-	if (!slave)
-		return NULL;
-
-	slave->bus = bus;
-	slave->cs = cs;
-
-	return slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	free(slave);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-	return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-	     void *din, unsigned long flags)
-{
-	static int bWrite = 0;
-	u8 *spi_rd, *spi_wr;
-	int len = bitlen >> 3;
-
-	spi_rd = (u8 *) din;
-	spi_wr = (u8 *) dout;
-
-	/* command handling */
-	if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
-		switch (*spi_wr) {
-		case 0x02:	/* Page Prog */
-			bWrite = 1;
-			dspi_tx(slave->cs, 0x80, spi_wr[0]);
-			dspi_rx();
-			dspi_tx(slave->cs, 0x80, spi_wr[1]);
-			dspi_rx();
-			dspi_tx(slave->cs, 0x80, spi_wr[2]);
-			dspi_rx();
-			dspi_tx(slave->cs, 0x80, spi_wr[3]);
-			dspi_rx();
-			return 0;
-		case 0x05:	/* Read Status */
-			if (len == 4)
-				if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
-				    && (spi_wr[3] == 0xFF)) {
-					dspi_tx(slave->cs, 0x80, *spi_wr);
-					dspi_rx();
-				}
-			return 0;
-		case 0x06:	/* WREN */
-			dspi_tx(slave->cs, 0x00, *spi_wr);
-			dspi_rx();
-			return 0;
-		case 0x0B:	/* Fast read */
-			if ((len == 5) && (spi_wr[4] == 0)) {
-				dspi_tx(slave->cs, 0x80, spi_wr[0]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[1]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[2]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[3]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[4]);
-				dspi_rx();
-			}
-			return 0;
-		case 0x9F:	/* RDID */
-			dspi_tx(slave->cs, 0x80, *spi_wr);
-			dspi_rx();
-			return 0;
-		case 0xD8:	/* Sector erase */
-			if (len == 4)
-				if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
-					dspi_tx(slave->cs, 0x80, spi_wr[0]);
-					dspi_rx();
-					dspi_tx(slave->cs, 0x80, spi_wr[1]);
-					dspi_rx();
-					dspi_tx(slave->cs, 0x80, spi_wr[2]);
-					dspi_rx();
-					dspi_tx(slave->cs, 0x00, spi_wr[3]);
-					dspi_rx();
-				}
-			return 0;
-		}
-	}
-
-	if (bWrite)
-		len--;
-
-	while (len--) {
-		if (dout != NULL) {
-			dspi_tx(slave->cs, 0x80, *spi_wr);
-			dspi_rx();
-			spi_wr++;
-		}
-
-		if (din != NULL) {
-			dspi_tx(slave->cs, 0x80, 0);
-			*spi_rd = dspi_rx();
-			spi_rd++;
-		}
-	}
-
-	if (flags == SPI_XFER_END) {
-		if (bWrite) {
-			dspi_tx(slave->cs, 0x00, *spi_wr);
-			dspi_rx();
-			bWrite = 0;
-		} else {
-			dspi_tx(slave->cs, 0x00, 0);
-			dspi_rx();
-		}
-	}
-
-	return 0;
-}
-#endif				/* CONFIG_CMD_SPI */
-
-#endif				/* CONFIG_CF_DSPI */
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index 26fb2ce..c156bab 100644
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -149,9 +149,35 @@ asm_sbf_img_hdr:
 	.long	0x00030000	/* image length */
 	.long	TEXT_BASE	/* image to be relocated at */
 
+
+
 asm_dram_init:
+	move.w #0x2700,%sr		/* Mask off Interrupt */
+
+	move.l	#CONFIG_SYS_INIT_RAM_ADDR, %d0
+	movec	%d0, %VBR
+
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
-	movec	%d0, %RAMBAR1	/* init Rambar */
+	movec	%d0, %RAMBAR1
+
+	/* initialize general use internal ram */
+	move.l #0, %d0
+	move.l #(CACR_STATUS), %a1	/* CACR */
+	move.l #(ICACHE_STATUS), %a2	/* icache */
+	move.l #(DCACHE_STATUS), %a3	/* dcache */
+	move.l %d0, (%a1)
+	move.l %d0, (%a2)
+	move.l %d0, (%a3)
+
+	/* invalidate and disable cache */
+	move.l	#0x01004100, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+	movec	%d0, %ACR2
+	movec	%d0, %ACR3
+
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
 
@@ -163,10 +189,7 @@ asm_dram_init:
 	move.l	#0xFC008004, %a1
 	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
 
-	/*
-	 * Dram Initialization
-	 * a1, a2, and d0
-	 */
+	/* Dram Initialization a1, a2, and d0 */
 	/* mscr sdram */
 	move.l	#0xFC0A4074, %a1
 	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
@@ -209,24 +232,21 @@ dramsz_loop:
 	move.l	#0xFC0B8000, %a1	/* Mode */
 	move.l	#0xFC0B8004, %a2	/* Ctrl */
 
-#ifdef CONFIG_M54455EVB
 	/* Issue PALL */
 	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
 	nop
 
+#ifdef CONFIG_M54455EVB
 	/* Issue LEMR */
 	move.l	#(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
 	nop
 	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
 	nop
-
-	move.l	#1000, %d0
-wait1000:
-	nop
-	subq.l	#1, %d0
-	bne	wait1000
 #endif
 
+	move.l	#1000, %d1
+	jsr	asm_delay
+
 	/* Issue PALL */
 	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
 	nop
@@ -246,25 +266,24 @@ wait1000:
 	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
 	nop
 	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
-	nop
 #endif
 
-	move.l	#500, %d0
-wait500:
-	nop
-	subq.l	#1, %d0
-	bne	wait500
+	move.l	#500, %d1
+	jsr	asm_delay
 
-	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d0
-	and.l	#0x7FFFFFFF, %d0
+	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d1
+	and.l	#0x7FFFFFFF, %d1
 #ifdef CONFIG_M54455EVB
-	or.l	#0x10000c00, %d0
+	or.l	#0x10000C00, %d1
 #elif defined(CONFIG_M54451EVB)
-	or.l	#0x10000000, %d0
+	or.l	#0x10000C00, %d1
 #endif
-	move.l	%d0, (%a2)
+	move.l	%d1, (%a2)
 	nop
 
+	move.l	#2000, %d1
+	jsr	asm_delay
+
 	/*
 	 * DSPI Initialization
 	 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
@@ -274,6 +293,7 @@ wait500:
 	 * a4 - Dst addr
 	 */
 	/* Enable pins for DSPI mode - chip-selects are enabled later */
+asm_dspi_init:
 	move.l	#0xFC0A4063, %a0
 	move.b	#0x7F, (%a0)
 
@@ -367,27 +387,29 @@ asm_dspi_rd_status:
 
 	move.b	(%a3), %d1
 	rts
+
+asm_delay:
+	nop
+	subq.l	#1, %d1
+	bne	asm_delay
+	rts
 #endif			/* CONFIG_CF_SBF */
 
 	.text
 	. = 0x400
 	.globl	_start
 _start:
+#if !defined(CONFIG_CF_SBF)
 	nop
 	nop
 	move.w #0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
-#if defined(CONFIG_CF_SBF)
-	move.l	#TEXT_BASE, %d0
-	movec	%d0, %VBR
-#else
 	move.l	#CONFIG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
-#endif
 
 	/* initialize general use internal ram */
 	move.l #0, %d0
@@ -411,6 +433,7 @@ _start:
 	   the first c-code */
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
+#endif
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
 
@@ -532,7 +555,7 @@ icache_enable:
 	move.l	#0x00040100, %d0	/* Invalidate icache */
 	movec	%d0, %CACR
 
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0	/* Setup icache */
+	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0	/* Setup icache */
 	movec	%d0, %ACR2
 
 	move.l	#0x04088020, %d0	/* Enable bcache and icache */